Of Circuit Patents (Class 702/117)
  • Patent number: 10429433
    Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raphael P. Robertazzi, Peilin Song, Franco Stellari
  • Patent number: 10380061
    Abstract: A digital serial communication system includes a first serial communication circuit configured to exchange information utilizing a first communication protocol, a second serial communication circuit configured to exchange information utilizing a second communication protocol, and a common bus interface configured to couple the first serial communication circuit to a first serial communication bus implementing the first communication protocol, and configured to couple the second serial communication circuit to a second serial communication bus implementing the second communication protocol.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 13, 2019
    Assignee: The United States of America as represented by the Administrator of NASA
    Inventors: George Suarez, Jeffrey J. Dumonthier, George E. Winkert
  • Patent number: 10365104
    Abstract: A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Rauli Collin, Konsta Wjuga, Lasse Aaltonen
  • Patent number: 10303479
    Abstract: A branch predictor, has a plurality of memory banks having entries that hold prediction information used to predict a direction of branch instructions fetched and executed by a processor that comprises the branch predictor. A count of events that occur in the processor is provided to hardware logic that performs an arithmetic and/or logical operation, e.g., XOR, on predetermined bits of the count to generate a random value. In response to the processor determining a correct direction of a branch instruction predicted by the branch predictor, the branch predictor uses the random value generated by the hardware logic to make a decision about updating the memory banks. Bits of a branch history pattern, along with the count, may also be used to generate the random value. The event counted may be a retire of an instruction or a cycle of a core or bus clock.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 28, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventors: Mengchen Yang, Guohua Chen, Xiaoling Wang
  • Patent number: 10295913
    Abstract: An inspection method, and corresponding apparatus, enables classification of pupil images according to a process variable. The method comprises acquiring diffraction pupil images of a plurality of structures formed on a substrate during a lithographic process. A process variable of the lithographic process varies between formation of the structures, the variation of the process variable resulting in a variation in the diffraction pupil images. The method further comprises determining at least one discriminant function for the diffraction pupil images, the discriminant function being able to classify the pupil images in terms of the process variable.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: May 21, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Scott Anderson Middlebrooks, Rene Andreas Maria Pluijms, Martyn John Coogans, Marc Johannes Noot
  • Patent number: 10281974
    Abstract: A three-dimensional stacked (3DS) memory module includes multiple memory chips and a data I/O chip physically integrated into the 3D stack. The data I/O chip includes multiple data interfaces and multiple respectively corresponding data buffers. A memory controller routes data traffic through all available data interfaces for maximum bandwidth. In some circumstances, the memory controller directs the data I/O chip to shut down (de-activate) one or more of the data interfaces (for example, to reduce power consumption of the memory module). All subsequent data traffic to and from the memory module is routed through the remaining active interfaces. All physical addresses in the 3DS memory module are addressable through the remaining active interfaces. In some circumstances, the memory controller directs the data I/O chip to re-activate some or all of the de-activated data interfaces. Once re-activated, subsequent data traffic to and from the memory module can again be routed through all active interfaces.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. Mcilvain, Saravanan Sethuraman, Warren E. Maule, Kyu-hyoun Kim
  • Patent number: 10267836
    Abstract: Devices and methods for determining the quality thin film materials are disclosed. The thin film materials are provided on substrates forming thin film material structures. The devices comprise a housing, a THz module with a THz source emitter and a THz detector, and a reflective base moveable relative to the THz module and configured to support the thin film material structures. The THz source emitter is configured to irradiate the thin film materials. The THz detector is configured to measure at least one reflection of the irradiation. The device is configured to calculate a parameter indicative of the quality of the thin film material based on said reflection measurements.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 23, 2019
    Assignees: DAS-NANO, S.L., ASOCIACION CENTRO DE INVESTIGACION COOPERATIVE EN NANOCIENCIAS (CIC NANOGUNE), GRAPHENEA, S.A.
    Inventors: Eduardo Azanza Ladrón, Magdalena Chudzik, Alex López Zorzano, David Etayo Salinas, Luis Eduardo Hueso Arroyo, Amaia Zurutuza Elorza
  • Patent number: 10270246
    Abstract: A method and apparatus for controlling a voltage source converter to energize a DC link. A voltage order generating module generates a voltage order for controlling the voltage source converter to generate a DC voltage on the DC link. An oscillation damping module monitors the DC current flow to determine an indication of current oscillation and the voltage order is based on a voltage reference signal which is modulated by the indication of current oscillation to provide oscillation damping.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 23, 2019
    Assignee: GENERAL ELECTRIC TECHNOLOGY GMBH
    Inventors: Robin Gupta, Carl Barker, Andrzej Adamczyk
  • Patent number: 10243678
    Abstract: Dynamic characterization of complex high-order nonlinearity in transmitter (TX) and receiver (RX) signal chains of transceiver systems can be efficiently and accurately performed. A loopback connection may be used to facilitate self-characterization. Appropriate RX and TX configuration settings may be developed to facilitate de-coupling of individual RX and TX nonlinearities from measured cascade nonlinearity. The system's high-order response to a two-tone signal generation may be measured, and complex mathematical analysis may be performed to identify and isolate passband nonlinear components to extract a high-order memory-less model for the system. The extracted system model may be used in the corrective and non-iterative pre-distortion of generated signals and in the post-distortion of received signals to improve linearity performance of the transceiver.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: March 26, 2019
    Assignee: National Instruments Corporation
    Inventors: Mohamad A. Zeidan, Christopher J. Behnke, Syed Jaffar Shah
  • Patent number: 10235274
    Abstract: A device may determine one or more conditional parameters associated with determining whether a condition is satisfied during execution of a program. The one or more conditional parameters may vary over time. The device may execute the program to generate one or more execution parameters corresponding to the one or more conditional parameters. The device may compare the one or more execution parameters and the one or more conditional parameters. The device may determine that the condition is satisfied based on comparing the one or more execution parameters and the one or more conditional parameters. The device may perform an action, in association with the program, based on determining that the condition is satisfied.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: March 19, 2019
    Assignee: The MathWorks, Inc.
    Inventors: George Quievryn, Jay Ryan Torgerson
  • Patent number: 10230521
    Abstract: The present invention relates to a test method of a circuit, comprising: acquiring a plurality of value sets comprising values of a physical quantity linked to the activity of a circuit to be tested when the circuit executes an operation of a set of distinct cryptographic operations applied to a secret data, selecting at least a first subset in each value set, for each value set, counting by a processing unit occurrence numbers of values transformed by a first surjective function applied to the values of the first subset of the value set, to form an occurrence number set for the value set, for each operation of the operation set, and each of the possible values of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value or equivalent value of the possible values of the part of the secret data, provide a partial operation result having
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 12, 2019
    Assignee: Eshard
    Inventors: Antoine Wurcker, Hugues Thiebeauld De La Crouee, Christophe Clavier
  • Patent number: 10191113
    Abstract: An apparatus for testing an electrical component, having a simulation unit for producing a simulation signal, a plurality of test units, and at least one electrical connecting device, whereby the simulation unit and the plurality of test units are connected or connectable to each other in an electrically conductive fashion via the at least one connecting device, and the at least one connecting device has at least one electrical switch device, which is situated to make or break an electrical connection between the plurality of test units.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 29, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Dirk Hasse, Peter Scheibelhut, Robert Polnau
  • Patent number: 10168382
    Abstract: Electronic test set embodiments and related methods are provided that can include a variety of safety components and/or processes which permit expandable or scalable automated testing of different types of equipment with or without installed sensitive, dangerous, vulnerable or expendable equipment. Embodiments can programmably or interface share measuring systems using expandable programmable interface systems that can scalably test a large number of components or electrical channels or bus lines. Embodiments can include multiple circuit board slot connectors adapted to receive programmable relay circuit cards that can selectively couple individual pins on ETS interface structures (e.g., cable connectors) to selected test equipment. Programmable relay circuit cards can be added to the ETS based on how many channels or bus connections are needed to interface with a system under test.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 1, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Eric Hodges, Ernest Coates, Angel Rosales-Ayala, Masato Taniguchi, Justin Cheung
  • Patent number: 10156611
    Abstract: Automatic test equipment (ATE) may include: a test instrument to implement a communication protocol to communicate to a unit under test (UUT), where the test instrument is memory storing bytecode that is executable, and where the test instrument being configured to identify an event in communication between the test instrument and the UUT and, in response to the event, to execute the bytecode. The ATE may also include a test computing system to execute a test program and an editor program, where the editor program is for receiving human-readable code and for generating the bytecode from the human-readable code, and the test program is for registering the event with the test instrument and for downloading the bytecode to the test instrument for storage in the memory.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 18, 2018
    Assignee: Teradyne, Inc.
    Inventors: Yonet A. Eracar, Michael Francis McGoldrick, Stephan Krach
  • Patent number: 10151795
    Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10152551
    Abstract: A method performed in a processing unit for determining calibration data to be used when processing data from a sensor unit connected to the processing unit, the method including receiving, from the sensor unit, an identifier which identifies and is calculated based on calibration data stored in the sensor unit, checking if there is an identifier stored in the processing unit identical to the received identifier, where the identifier stored in the processing unit identifies and is calculated based on calibration data stored in the processing unit, if an identical identifier is stored in the processing unit, using the calibration data stored in the processing unit identified by the identical identifier when processing data from the sensor unit, if no identical identifier is stored in the processing unit, requesting the sensor unit to transmit calibration data, and using the requested calibration data when processing data from the sensor unit.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: December 11, 2018
    Assignee: Axis AB
    Inventors: Henning Gredegård, Magnus Mårtensson, Henrik Fasth, Mårten Lindahl, Joakim Olsson, Martin Santesson
  • Patent number: 10135550
    Abstract: A calibration signal is transmitted from a transmitter antenna. A receiver antenna receives a loopback signal that results from an air coupling of the receiver antenna and the transmitter antenna. The loopback signal is compared to a target. If the loopback signal does not meet the target, then a gain of the calibration signal is adjusted and the loopback signal is again checked against the target. When the loopback signal meets the target, the gain is taken as a calibrated transmitter gain.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: November 20, 2018
    Assignee: PERASO TECHNOLOGIES INC.
    Inventors: Gary Cheng, Bradley Robert Lynch
  • Patent number: 10127103
    Abstract: A system and method is disclosed for detecting and correcting for errors in mapping table information stored in volatile memory of a non-volatile memory system. The method may include checking for mapping entry errors when retrieving mapping data for the non-volatile memory from a volatile memory cache. When an error is discovered, the method includes the processor generating a set of candidate mapping entries each having a different single bit difference from the mapping entry discovered to have an error. Each candidate is tested against one or more mapping data accuracy tests and, when one of the candidates is found to be a correct mapping entry based on the one or more tests, the original mapping table entry with the determined defect is replaced with the successful candidate mapping entry.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 13, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Igor Genshaft, Marina Frid, Jonathan Journo
  • Patent number: 10078419
    Abstract: The method relates to a Universal Plug and Play AV system, which comprises a media server included in a server device having a digital interface, to which a removable storage device is coupled, a media renderer included in a display device and a control point included in a control device for controlling the server device and the display device via Universal Plug and Play AV actions. The method comprises the steps of arranging an unmount icon in the display of the control device, unmounting the storage device in case said unmount icon is operated, and providing a feedback on the display device and/or the control device after said unmount action was performed on the server device.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: September 18, 2018
    Inventors: Frank Vanderhallen, Dominique Chanet, Guy Frederix, Kristl Haesaerts
  • Patent number: 10061585
    Abstract: A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a first operand to be used. The machine instruction is executed, and execution includes for each block of memory of one or more blocks of memory of the first operand, generating a hash value using a 512 bit secure hash technique and at least one seed value of a parameter block of the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Bernd Nerz, Tamas Visegrady
  • Patent number: 10054624
    Abstract: A system and method of electronic component authentication or component classification can reduce the vulnerability of systems (e.g., satellites, weapons, critical infrastructure, aerospace, automotive, medical systems) to counterfeits. Intrinsic deterministically random property data can be obtained from a set of authentic electronic components, processed, and clustered to create a classifier that can distinguish whether an unknown electronic component is authentic or counterfeit.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 21, 2018
    Assignee: Battelle Memorial Institute
    Inventors: Larry J. House, Dale C. Engelhart
  • Patent number: 10024898
    Abstract: A system includes a power converter including a primary bridge unit to receive a primary voltage from a voltage source, the primary bridge unit includes a first plurality of electronic switches, and each of the first plurality of electronics switches has a turn ON time and a turn OFF time. Further, the power converter includes a transformer including a primary winding and a secondary winding, the primary winding is coupled to the first plurality of electronic switches. Also, the power converter includes a secondary bridge unit including a second plurality of electronic switches coupled to the secondary winding. Additionally, the system includes a controller to determine an inductance of the power converter based on the primary voltage, the turn ON time of the first plurality of electronic switches, a switching cycle time of the power converter, and one of an average current and a peak current in the power converter.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 17, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Said Farouk El-Barbari, Alvaro Jorge Mari Curbelo, Simon Herbert Schramm
  • Patent number: 9977064
    Abstract: A difference measurement circuit having a first port and a second port for connection to a first set of nodes and a second set of nodes of a sensor unit. The circuit further has switching units for switching excitation signals emanating from excitation nodes from being applied to the first set of nodes (A, B) via the first port to being applied to the second set of nodes via the second port and for switching differential measurement signals measured at sensing nodes from being obtained from the second set of nodes via the second port to being obtained from the first set of nodes via the first port. The circuit further includes redundancy testing circuitry for evaluating the similarity or deviation between measurement signals obtained in different states of the switching units.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 22, 2018
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Johan Raman, Pieter Rombouts
  • Patent number: 9947377
    Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Michael Joseph Brunolli, Dexter Tamio Chun, David Ian West
  • Patent number: 9940046
    Abstract: A semiconductor memory device which stores operation environment information such as use time data, operating temperature data, or operating voltage data includes an internal circuit configured to perform a function set in the semiconductor memory device, and an operation environment information storing circuit configured to sense information about an operation environment of the semiconductor memory device when the semiconductor memory device operates, store the operation environment information in non-volatile memory cells, and provide the operation environment information stored in the non-volatile memory cells to an outside based on a request of reading out information.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chankyung Kim, Mijo Kim, Yonggyu Chu, Seungbum Ko, Soo Hwan Kim
  • Patent number: 9934336
    Abstract: A method for projecting an electron beam used notably in lithography by direct or indirect writing as well as in electron microscopy, is provided. Notably for critical dimensions or resolutions of less than 50 nm, the proximity effects created by the forward and backward scattering of the electrons of the beam in interaction with the target must be corrected. This is traditionally done using the convolution of a point spread function with the geometry of the target. In the prior art, said point spread function uses Gaussian distribution laws. At least one of the components of the point spread function is a linear combination of Voigt functions and/or of functions approximating Voigt functions, such as the Pearson VII functions. In certain embodiments, some of the functions are centered on the backward scattering peaks of the radiation.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 3, 2018
    Assignee: Aselta Nanographics
    Inventors: Jean-Herve Tortai, Patrick Schiavone, Thiago Figueiro, Nader Jedidi
  • Patent number: 9934866
    Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: April 3, 2018
    Inventors: Brent Haukness, Ian Shaeffer
  • Patent number: 9928150
    Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 27, 2018
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Hai Lin, Subhasish Mitra
  • Patent number: 9929866
    Abstract: A power over Ethernet (PoE) connection check method comprising: for a first time period, generating a first detection power over the first set of wires while not generating a second detection power over the second set of wires and obtaining a first indication of a power attribute over the first set of wires; during a second time period, generating the first detection power and generating a second detection power, greater than the first detection power, over the first set of wires; during the second time period, obtaining a second indication of the power attribute over the first set of wires; determining a first difference between the first indication and the second indication; and controlling a first power enable circuit and a second power enable circuit to provide power to the powered device over the first and second sets of wires respectively, responsive to the determined difference.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 27, 2018
    Assignee: Microsemi P.O.E. Ltd.
    Inventors: Yair Darshan, Alon Ferentz
  • Patent number: 9927272
    Abstract: An air flow meter has a housing, a flow rate sensor, and a physical-quantity measuring sensor. The housing therein defines a bypass passage into which a part of air flowing in a duct flows. The flow rate sensor is disposed in the bypass passage. The physical-quantity measuring sensor measures a physical quantity of air flowing in the duct and is disposed separately from the flow rate sensor. The housing has a recessed portion that is recessed from an inner wall surface of the bypass passage and that has a blind-passage shape. The physical-quantity measuring sensor is disposed in the recessed portion.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 27, 2018
    Assignee: DENSO CORPORATION
    Inventor: Takashi Ooga
  • Patent number: 9899067
    Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
  • Patent number: 9886414
    Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: February 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegeun Yun, Lingling Liao, Bub-chul Jeong
  • Patent number: 9869727
    Abstract: A method for monitoring a power supply connected to a superordinate controller via a signal line, wherein the superordinate controller queries whether the power supply is operating faultlessly at variable intervals, where during faultless operation, a power-good signal is continuously transmitted by the power supply to the superordinate controller via the signal line and, if a fault occurs, an indicating signal is transmitted by the power supply to the superordinate controller via the signal line as a switching sequence of high and low signals such that each signal change of the switching sequence occurs only after a time period that is longer than an expected greatest query interval and each signal of the switching sequence that does not correspond to the power-good signal is shorter than a specified signal duration for indicating a total failure of the power supply, whereby the superordinate controller receives more information than previously.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: January 16, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventor: Harald Schweigert
  • Patent number: 9864001
    Abstract: An electronic device is provided. The electronic device includes a printed circuit board (PCB), an antenna structure, a radio frequency signal transceiving circuit and a testing structure. The antenna structure is disposed on the PCB. The radio frequency signal transceiving circuit is disposed on the PCB, and is connected to the antenna structure through a conductive line. The testing structure includes a testing point and a grounding structure. The testing point is disposed on the conductive line, and the grounding structure is disposed on the PCB.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 9, 2018
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jui-Hung Hsu, Li-Hsin Wang, Ping-Yueh Hsieh, Yi-Da Chen, Jhu-Jyun Chang, Hou-Lung Lin
  • Patent number: 9857414
    Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 2, 2018
    Assignee: Alarm.com Incorporated
    Inventors: Ronald Byron Kabler, Robert Leon Lutes, Alain Charles Briancon, Curtis Scott Crawford, Christopher Allen Giacoponello, Jerald Frederic Johnson, Victor Andres Jara-Olivares, Marc Anthony Epard, Steven Jeffrey Goldberg, John Berns Lancaster
  • Patent number: 9837171
    Abstract: A built-in self-test circuit includes a command storage unit that stores commands inputted from an external device, an input/output control unit that controls the command storage unit to sequentially store the commands and sequentially output stored commands as internal commands in a test operation, and a command decoder unit that decodes the internal commands outputted from the command storage unit and outputs a test command.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 5, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hee-Won Kang
  • Patent number: 9836042
    Abstract: Necessary unit data indicative of the type and number of equipment units used in component mounting operation is obtained on the basis of production plan data, mounting data, and component library for each of production lots in advance. New allocation processing for allocating an equipment unit necessary for production execution of a new production lot to be newly produced on an electronic component mounting line for the new production lot on the basis of the necessary unit data is executed, and component reservation processing for registering the allocation result as the inventory data is conducted by a unit reservation unit.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 5, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuhiro Maenishi, Norihasa Yamasaki, Yuji Nakamura
  • Patent number: 9836373
    Abstract: On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 5, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Vooka, Vishwanath S, Pranav Murthy, Ratheesh Thekke Veetil, Rahul Gulati
  • Patent number: 9823808
    Abstract: The invention provides methods and devices that address problems encountered when attempting to accurately reconstruct visual stimuli being displayed to a user as they interact with online-content, typically through a browser interface. In one embodiment, the invention provides for the browser to maintain a record of selected technical parameters and relevant data that may impact the manner in which online-content is being displayed to the user, taking into consideration the current context in which the browser is being operated. In another embodiment, the invention is a device for recording events as reported from a browser interface. The events are recorded in a selected format and syntax to form a primary index of events and related outcomes which comprise the users interface experience. In operation, the devices detect events as detected at the browser interface. Next, the devices identify, categorize, and filter detected events as to their relevance to the visual stimuli being presented to the user.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: November 21, 2017
    Assignee: RATEZE REMOTE MGMT LLC
    Inventors: Kenneth H. Crain, William K. Vanover
  • Patent number: 9823293
    Abstract: A method for diagnosing an electrical circuit including at least one electrical device, an actuator for the device controlled by a high side actuating switch and a low side actuating switch, and at least one additional switch not in series with any of the HS or LS switch, the method including: to each of the possible statuses of the circuit, giving a code; sequentially putting the circuit in at least some of these statuses for a given time period; during each of these periods, measuring voltage and/or current in different parts of the circuit and giving a code to the measurement; and establishing a diagnosis of correct functioning or of a malfunctioning of at least some elements of the circuit according to a pre-established correlation between the status codes and the measurement codes.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: November 21, 2017
    Assignee: INERGY AUTOMOTIVE SYSTEMS RESEARCH (Societe Anonyme)
    Inventors: Francois-Regis Lavenier, Mircea Mateica, Gerd Meyering, Arnd Langenstein
  • Patent number: 9823329
    Abstract: A magnetic current sensor calibration system includes a plurality of sensors and a substrate. The substrate has a first surface and a second surface, and the sensors are mounted on the first surface. The substrate includes a bipolar calibration conductor and a unipolar calibration conductor. The bipolar calibration conductor is spaced apart from the plurality of sensors and is disposed between the first and second surfaces. The unipolar calibration conductor is spaced apart from the plurality of sensors and the bipolar calibration conductor, and is disposed between the first and second surfaces.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: November 21, 2017
    Assignee: Honeywell International Inc.
    Inventors: Andy Peczalski, Tom Rezachek
  • Patent number: 9804222
    Abstract: Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: October 31, 2017
    Assignee: Allegro MicroSystems, LLC
    Inventors: Craig S. Petrie, Bryan Cadugan
  • Patent number: 9792395
    Abstract: The disclosed approaches compile a hierarchical representation of a circuit design into a flattened netlist and store the flattened netlist a memory circuit. The circuit design instantiates a plurality of memory blocks of a target device and specifies logic circuits that access the plurality of memory blocks, respectively. The flattened netlist is modified by determining a subset of the plurality of memory blocks. The quantity of memory reserved in each memory block of the subset is less than a capacity of said each memory block. One memory block is instantiated, for a pair of the memory blocks of the subset, in place of each memory block of the pair in the flattened netlist in the memory circuit. A portion of the flattened netlist that specifies the logic circuits that access each memory block of the pair is modified to access the one memory block instead of each memory block of the pair.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 17, 2017
    Assignee: XILINX, INC.
    Inventors: Jayaram Pvss, Robert Bellarmin Susai, Khang K. Dao
  • Patent number: 9773399
    Abstract: Diagnostic test devices improve communication to a user thereof through provision of audible output. The test device can include a test member, such as lateral flow assay test strip. The test device further includes an electronic communication circuit that can comprise an audio output element as well as a microcontroller. Other elements in the electronic communication circuit includes one or more sensor elements, a display element, and one or more switching elements.—Methods provide indicia for operation of a test device that comprise steps for assembly of a diagnostic test device that provides for audio output.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: September 26, 2017
    Assignee: Church & Dwight Co., Inc.
    Inventors: Mathew Palmer, Giles H. W. Sanders, Nicholas J. Wooder, Albert R. Nazareth, Timothy Snowden, Ovidiu Romanoschi
  • Patent number: 9760344
    Abstract: A system for providing a computer language with which to write rules is provided. The system may include a rules container, a rules classes container and an engine/graph. The rules classes container may provide a code library of rules and unit test from which to inherit. The system may also include a rules GUI that may accept code of a rule in a code field window. The rules GUI may also include a documentation presentation window. The documentation presentation window may include a non-editable, reader-friendly view of the rule. Viewing the documentation window adjacent to the code field window may enable a user to understand the code and edit the code. Each rule may depend from another rule or provide a dependency for another rule. The system may save the rules into the rules container. The engine/graph may create a graph of the rules documentation based on the dependencies.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: September 12, 2017
    Assignee: Bank of America Corporation
    Inventors: Aneesh Shukla, Arnav Khare, Steve Stagg, Mark C. Dessain, Hector Ariel Goyeneche, Piers Thompson
  • Patent number: 9733305
    Abstract: Embodiments of the present disclosure provide methods for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The method includes identifying at least one design criteria and obtaining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. In certain embodiments, the boundary sets may be derived using a genetic algorithm. The method further includes verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Glen A. Wiedemeier, Si T. Win
  • Patent number: 9686053
    Abstract: Embodiments of the present disclosure provide methods for testing channel compliance. The method generally includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 20, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Glen A. Wiedemeier, Si T. Win
  • Patent number: 9684028
    Abstract: The operation of electrical appliances receiving electrical power from an electrical system may be indirectly monitored using monitoring units engaged with outlets on branch circuits of the electrical system. Electrical systems providing power to appliances to be monitored in accordance with the present invention may comprise split phase alternating current systems, tri-phase systems, or any other type of electrical system. Known loads may be applied to calibrate the monitoring system. The monitoring system may measure the power consumption of appliances operating on the electrical system and/or detect possible fault conditions. The monitoring system may be distributed across multiple monitoring units and other computing devices. Output devices may be used to output a summary of the power consumption or other operation of monitored electrical appliances.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 20, 2017
    Assignee: Alarm.com Incorporated
    Inventors: Ronald Byron Kabler, Robert Leon Lutes, Alain Charles Briancon, Curtis Scott Crawford, Christopher Allen Giacoponello, Jerald Frederic Johnson, Victor Andres Jara-Olivares, Marc Anthony Epard, Steven Jeffrey Goldberg, John Berns Lancaster
  • Patent number: 9673941
    Abstract: Embodiments of the present disclosure provide apparatus for testing channel compliance. The apparatus generally performs operations that includes identifying at least one design criteria and determining boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria. The boundary sets may be used for verifying whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Glen A. Wiedemeier, Si T. Win
  • Patent number: 9638750
    Abstract: Embodiments of the present disclosure provide apparatus for using a compliance model to determine compatibility of a channel with a bus's chip I/O circuitry at its ends. The apparatus includes at least one processor and a memory coupled to the at least one processor. The processor is configured to: identify at least one design criteria; obtain boundary sets of frequency domain parameters for compliant signal channels known to achieve the design criteria; and verify whether a particular signal channel is compliant by comparing values of frequency domain parameters for the particular channel to one or more of the boundary sets of frequency domain parameters for the known compliant channels.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wiren D. Becker, Daniel M. Dreps, Jose A. Hejase, Glen A. Wiedemeier, Si T. Win