Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

Abstract: A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory unit controller. A direct memory transfer of the result is established over the communication protocol to a network.

Abstract: A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

Abstract: A system, method, and computer-readable medium are disclosed automatic validation of light emitting diodes (LEDs) of disk drives in disk processor enclosures (DPEs) or disk array enclosures (DAEs) during the manufacturing and integration of computer systems. An automated test script is performed in support of the integration of the computer system that includes the LEDs and includes a validation and checking step for the LEDs. A determination is made if a camera is properly calibrated to identify the LEDs as part of the validating and checking step for the LEDs. A DPE or DAE that contains disk drive units that include the LEDs are identified, and an indication is performed as to which LEDs pass or fail.

Abstract: Disclosed herein is a computer-implemented method for generating calibration data usable for analysis of a sample. The method includes: (i) identifying targets in an image frame pertaining to a scanned area of a sample; (ii) computing displacements of the targets relative to positions thereof as given by, or derived from, reference data of the scanned area; (iii) based at least on the computed target displacements, determining values of coordinate transformation parameters (CTPs) relating coordinates of the image frame to coordinates of the scanned area as given by, or derived from, the reference data; and (iv) using at least the CTPs to obtain displacements of multiple segments in the image frame, thereby generating a displacement mapping of the image frame or at least a part thereof.

Abstract: Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Abstract: A semiconductor package test system includes a test pack on which a semiconductor package is loaded, and a semiconductor package testing apparatus. The semiconductor package testing apparatus includes a receiving section that receives the test pack. The receiving section includes a pack receiving slot into which the test pack is inserted. The test pack includes a chuck on which the semiconductor package is fixed, a probe block disposed above the chuck, and a connection terminal. The receiving section includes a receiving terminal that is electrically connected to the connection terminal when the receiving terminal contacts the connection terminal. The probe block includes at least one needle configured to be electrically connected to the semiconductor package disposed on the chuck upon the chuck moving toward the semiconductor package. The receiving section is provided in plural.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve boundary excursion detection. An example apparatus to improve boundary excursion detection includes a metadata extractor to parse a first control stream to extract embedded metadata, a metadata label resolver to classify a boundary term of the extracted embedded metadata, a candidate stream selector to identify candidate second control streams that include a boundary term that matches the classified boundary term of the first control stream, and a boundary vector calculator to improve boundary excursion detection by calculating a boundary vector factor based on respective ones of the candidate second control streams that include the classified boundary term.

Abstract: A method includes capturing a photon emission microscope (PEM) image of an integrated circuit (IC), and identifying emission sites in the PEM image, where the emission sites are associated with a leakage current. A set of common nets is found that connects multiple emission sites using layout data and/or netlist data in computer-aided design (CAD) data. From the layout data and/or netlist data, a critical net is identified from the set of common nets connecting a threshold number of emission sites. The critical net is cross-mapped, by a processor, tip netlist data in the CAD data. A particular device is identified from the netlist data that has an output pin connected to the critical net. The particular device identified from the netlist data is cross-mapped, by a processor, to the layout data, wherein the critical net connects at least two devices at the identified emission sites including the particular device.

Abstract: A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for impact analysis. One of the methods includes receiving information about at least two logical datasets, the information identifying, for each logical dataset, a field in that logical dataset and format information about that field. The method includes receiving information about a transformation identifying a first logical dataset from which the transformation is to receive data and a second logical dataset to which the transformed data is provided. The method includes receiving one or more proposed changes to at least one of the fields. The method includes analyzing the proposed changes based on information about the transformation and information about the first logical dataset and the second logical dataset. The method includes calculating metrics of the proposed change based on the analysis. The method also includes storing information about the metrics.

Abstract: A power module according to the present invention switches an operation mode between a control mode where an ON/OFF operation of a switching element having a first electrode, a second electrode, and a third electrode is controlled, and a deterioration determination mode where the deterioration is determined based on information including ?Vgs based on information including a threshold voltage detected before a stress current is supplied to the switching element and a threshold voltage detected after the stress current is supplied to the switching element. According to the power module of the present invention, the deterioration can be determined during an operation time and hence, breaking of the device can be prevented, and operation efficiency of the power module can be increased, and a manufacturing cost of the power module can be lowered.

Abstract: The present application provides a dynamic illumination method based on a scan exposure machine, providing a mask used for exposure and a GDS file corresponding to the mask; dividing pattern information on the mask into n areas with the same width along the direction of movement of the mask during the exposure; performing SMO computation on the pattern information in the n areas, so as to generate n SMO files corresponding to the n areas respectively; performing combinatorial optimization on the n SMO files to obtain a DSMO file; generating a driver of a light source reflector array according to the DSMO file, the illumination; and controlling a reflector array of an exposure machine by calling the driver of the light source reflector array. The DSMO method is performed in each exposure slit area, so as to improve the illumination optimization for a pattern.

Abstract: A test system includes: a test board on which a plurality of test target devices are mounted while being sequentially connected to one another; a measuring apparatus configured to simultaneously execute direct current tests for the test target devices mounted on the test board; and a determining apparatus configured to determine whether or not the test target devices are acceptable. The measuring apparatus executes the direct current tests every time when the number of test target devices mounted on the test board changes. The measuring apparatus determines whether or not the test target devices are acceptable on the basis of a change between measured values of the direct current tests, which follows the change of the number of test target devices mounted on the test board.

Abstract: A method of determining the energy level of an electromagnetic field (EMF) received from an EMF source (EMFS) and for identifying the EMFS is provided, the method using a plurality of EMF sensing apparatuses to combine data gathered by the apparatuses in order to identify the level and the sources of the EMF at locations over time. Historical and anticipated EMF-related data is used to warn a user of EMF levels above a preset value. Past, current and future anticipated EMF levels are adapted to be displayed on a map. Methods thereof, apparatuses thereof and computer-readable mediums storing the methods are within the scope of the present invention.

Abstract: Methods, systems, and devices for a compression method for defect visibility in a memory device are described. A memory device may identify one or more errors associated with a set of memory cells of a memory array in the device based on a first set of data associated with the first set of memory cells. The memory device may generate an indication of a location of the one or more errors in the first set of memory cells and compress the first set of data to generate an error flag based on identifying the one or more errors. The memory device may output the error flag and the indication of the location based on generating the error flag and the indication.

Abstract: A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract: An error detection and localisation in a pneumatic system and in particular an error detection module includes a read-in interface for reading-in digital signals from the automation plant, a first processor unit designed to execute a detection algorithm for calculating an anomaly score for the automation plant on the basis of the set of read-in signals, a second processor unit which is designed—in the event that the anomaly score calculated with the first processor unit indicates an anomaly—to perform a machine localisation method for localising the error, wherein the machine localisation method has been trained in a training phase in order to calculate and as a result provide, on the basis of a detected circuit diagram of the automation plant with respect to the calculated anomaly score, probabilities of possible causes of error in relation to individual components of the automation plant.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: The inventive concept relates to a method and system for cost-effectively predicting the dynamic nonlinearities of on-chip segmented digital-to-analog converter (DAC) and analog-to-digital-converter (ADC), by looping a DAC to an ADC, using a programmable-gain-amplifier (PGA) and an external load board. The method may include a first loopback step of supplying an output signal from a coarse DAC, to which a sinusoidal signal is supplied, to a coarse ADC and a fine ADC through an external load board, a second loopback step of supplying an output signal from a fine DAC, to which a sinusoidal signal is supplied, to the fine ADC and the coarse ADC through the load board, and a step of predicting dynamic nonlinearity of each of a DAC and an ADC by processing equations exhibiting dynamic nonlinearity of a sub-DAC and a sub-ADC, which are obtained in the first loopback step and the second loopback step.

Abstract: In response to a command from the control PC 4, the first mobile terminal test apparatus 2 compresses data of test signals including a first test signal and a second test signal which are generated and encrypted, and adds a restoration parameter to a header of the compressed data. The second mobile terminal test apparatus 3 acquires the restoration parameter-added compressed data at the second port 3a via the cable 5 from the first port 2a, and restores and encrypts the data of test signals before encryption, based on the restoration parameters. Under the control of the control PC 4, the first mobile terminal test apparatus 2 outputs the data of the first test signal to the device under test W, and the second mobile terminal test apparatus 3 outputs the data of the second test signal to the device under test W.

Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.

Abstract: A signal generation device with correction parameter measurement is provided. Said signal generation device comprises a signal generating unit configured to provide at least one test signal for a device under test with the aid of a connection structure, and a correction parameter measurement unit configured to measure at least one correction parameter with respect to said connection structure. In this context, both the signal generating unit and the correction parameter measurement unit are integrated into one housing.

Abstract: A method and a computer network of interconnected computer nodes, one assigned a role of a deployer node, the deployer node creating and executing a rule-based block, and assigning others of the computer nodes a role of sensor node or a role of display node. The deployer node maintains addresses of the sensor nodes and the display nodes, the sensor nodes add sensor track data to create linked blocks, and the display nodes read the sensor track data in the linked blocks. The rule-based block includes a sensor add rule which checks that only computer nodes assigned the role of the deployer node can assign a computer node the role of sensor node. The rule-based block includes a sensor track data add rule which checks that only the computer nodes assigned the role of sensor node can request to add new sensor track data to create the linked blocks.

Abstract: A radiated emission measurement method includes a prescan measurement step of performing broadband measurement including detection of a peak and detection of a quasi-peak by one fast Fourier transform in a target measurement frequency range; a calculation step of calculating a difference in level between the peak and the quasi-peak obtained for a measurement frequency to be a candidate for a result of measurement; a determination step of determining whether the obtained difference is less than a reference value; and an output step of outputting a result obtained as an interference level of the radiated emission in the broadband measurement when it is determined that the difference is less than reference value, and performing narrowband measurement and outputting the obtained result as the interference level of the radiated emission, when it is determined that the difference is equal to or higher than the reference value.

Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.

Abstract: A method for characterizing an integrated circuit that includes ramping the supply voltage to an integrated circuit as a function of time for each of the transistors in the integrated circuit, and measuring a power supply current for the integrated circuit during the ramping of the power supply voltage. The measured peaks in the power supply current are a current pulse that identifies an operation state in which each of the transistors are in an on state. The peaks in the power supply current are compared to the reference peaks for the power supply current for a reference circuit having a same functionality as the integrated circuit to determine the integrated circuit's fitness.

Abstract: A method for estimating an position of wireless network equipment, including setting a wireless network transmission parameter, wherein the wireless network transmission parameter includes a transmitting power, a carrier frequency and a spreading factor index, which are used for performing an initial operation setting of wireless network; according to the wireless network transmission parameter, providing a path loss index and a reference distance for simulating an actual wireless network environment; selecting a noise power to simulate a signal state of a transmission path; and according to a field domain, setting a received power threshold to calculate a predetermined transmission distance of wireless network equipment erection.

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.

Abstract: In one embodiment, a processor includes: at least one core; a stress detector coupled to the at least one core to receive at least one of a voltage and a temperature at which the processor is to operate, calculate an effective stress based at least in part thereon, and maintain an accumulated effective stress; a clock circuit to calculate a lifetime duration of the processor in a platform; a meter to receive the accumulated effective stress, the lifetime duration and a stress model value and generate a control signal based on a comparison of the accumulated effective stress and the stress model value; and a power controller to control at least one parameter of a turbo mode of the processor based at least in part on the control signal. Other embodiments are described and claimed.

Abstract: Systems, methods, and non-transitory computer-readable media can receive, via a user interface provided to a user, test device information identifying one or more user computing devices as test devices. An advertisement request is received from a first user computing device. A determination is made that the first user computing device is identified as a test device. A test advertisement is transmitted to the first user computing device based on the determination that the first user computing device is identified as a test device.

Abstract: Techniques relating to fused objects are disclosed. Embodiments include verifying the validity of a transition from a current tail template to a new tail template for a fused object. The validity of the transition is determined by analyzing the type transitions per memory slot. If the type transition, for each memory slot, constitutes a type-compatible transition, then the transition from the current tail template to the new tail template is valid. If the type transition, for any memory slot, is not type-compatible, then the transition from the current tail template to the new tail template is not valid. Embodiments include generating a fused object with a repeating tail. A tail template associated with a fused object is repeated multiple times in the tail of the fused object.

Abstract: A semiconductor device includes a row address generation circuit, a first region, and a second region. The row address generation circuit is configured to generate a first row address from an active signal and a first bank address and configured to generate a second row address from the active signal and a second bank address. The first region is activated by the first row address and an internal address. The second region is activated by the second row address and the internal address. One of the first and second bank addresses is selectively generated according to a command/address signal.

Abstract: The invention concerns a test program executor for an Automated Test Equipment, wherein the test program executor is configured to execute a test flow having a plurality of test suites, wherein the test program executor is configured to asynchronously execute the plurality of test suites, wherein a test suite contains a call of a function of a subsystem, wherein the function of the subsystem is related with a subsystem operation that is to be executed by the subsystem, and to signal a call of a function of a subsystem by transmitting an asynchronous request to the subsystem, the asynchronous request having a call-specific call tree hierarchy address and the call-specific operation to be executed by the subsystem, and wherein the test program executor is further configured to determine an execution order of the subsystem operations, such that the execution order of the subsystem operations depends on their call-specific call tree hierarchy addresses.

Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits.

Abstract: A processor executable method, system, and computer-readable media expedite the process of entering equations for use in developing simulations of chemical processes. The process of entering equations is expedited by dynamically inferring the dimensions of variables. The process infers the dimensions of all variables in user-added equations, and infers the dimensions of each variable in a user-added equation sequentially. The process automatically creates variables with unassigned dimensions in response to indications, such as inputs from a user, to declare new equations. The process assigns dimensions to variables based on relations between variables, such as logical relations between the dimensions of variables.

Abstract: A test system is provided for performing design for debug (DFD) operations. The test system includes a host processor coupled to an auxiliary device. The auxiliary device includes a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary device further includes a circuit under test (CUT) and a hardened DFD hub that is controlled by the host processor via the protocol interface block. The DFD hub includes a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor directs the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub is fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.

Abstract: Provided is an information processing apparatus including: an input unit into which shape data of a surface to be measured including a plurality of recesses is input; and a setting unit that detects each of the plurality of recesses on the basis of the input shape data and sets, for the detected recess, a region to be removed including the recess.

Abstract: A bandwidth estimation method is disclosed for measuring memory bandwidth consumption or the bandwidth consumption of any I/O bus in real time on a computer system without the use of hardware counters. The bandwidth estimation method, designed to run in isolation on a core in a multi-core computer system, generates temporally sequential and spatially random accesses to a bus such as the memory bus and reports the average latency per request. Using a pre-calculated latency-bandwidth relationship, the bandwidth on the bus is calculated and reported at runtime for every latency sample. The bandwidth estimation method allows profiling processors and computer systems in real time to determine the amount of memory or I/O traffic they are using while running a workload.

Abstract: According to one general aspect, an apparatus may include a memory configured to store both data and metadata, such that for portions of data associated with the metadata, the data and metadata are interleaved such that a unit of metadata succeeds each power of two contiguous units of data. The apparatus may also include a memory manager circuit. The memory management circuit may be configured to receive a data access to the memory, wherein the data access includes a public memory address. The memory management circuit may be configured to determine if the public memory address is associated with metadata. The memory management circuit may be configured to, if so, convert the public memory address to a private memory address. The memory management circuit may be configured to complete the data access at the private memory address.

Abstract: An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.

Abstract: Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.

Abstract: Various aspects of the disclosed technology relate to techniques of logic diagnosis based on cell-aware diagnostic pattern generation. A first diagnosis process is performed on a failed integrated circuit based on a first fail log to generate a first set of defect suspects. The first fail log is generated by applying the first set of test patterns to the failed integrated circuit in a first scan-based test. A second set of test patterns are generated using fault models for internal defects in one or more cells included in the first set of defect suspects. The second set of test patterns are applied to the failure integrated circuit to generate a second fail log. A second diagnosis process is performed on the failure integrated circuit based on the second fail log.

Abstract: Disclosed is a test and measurement instrument including a plurality of ports. The ports are configured to source a test signal into a device under test (DUT), and receive a signal response from the DUT. The test and measurement instrument also includes a measurement unit configured to measure the signal response. The test and measurement instrument further includes a processor configured to compare the signal response to a data structure. The processor also determines a classification of, and/or connections to, at least one DUT component coupled to at least one of the ports based on results of the comparison.

Abstract: A method for creating binary classification models and using the binary classification models to select candidate training utterances from a plurality of live utterances is provided. The method may include receiving a plurality of intents and associated training utterances. The method may include creating, from the training utterances, a binary classification model for each intent. The binary classification model may include a vector representation of a line of demarcation between utterances associated with the intent and utterances disassociated from the intent. The method may also include receiving live utterances. An intent may be determined for each live utterance. The method may include creating a vector representation of the live utterance. The method may include selecting candidate training utterances based on a comparison between the vector representation of the live utterance and the vector representation included in the binary classification model of the intent determined for the live utterance.