Abstract: A multithread auto test method is disclosed for the test process of computer hardware. According to the exclusion relation among the unique IDs of the test items, a multithread executable logic is automatically generated. An appropriate parallel method is employed to find procedures for test items that do not have conflictions. Therefore, multithreads of test procedures are performed to increase the test efficiency and quality. The method includes the steps of: determining a unique ID of a test item; automatically generating a test logic table according to the exclusion relation among the unique IDs; and performing multithread test procedure according to the test logic given in the test logic table.

Abstract: The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam.

Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.

Abstract: A circuit arrangement in which two parallel subcircuits having a same functionality have a same input signal applied to them, and their output signals are compared in a common comparison arrangement. The two subcircuits are designed differently in terms of sensitivity to changes in environmental or operating parameters. Impermissible environmental parameters are indicated if the output signals differ from one another, and an alarm is generated.

Abstract: Systems and methods for controlling test conditions using logic built-in self-test (LBIST) components to affect test conditions. In one embodiment, an LBIST controller is coupled to LBIST circuitry that is incorporated into the design of a device under test, and also to a thermal sensor that is in thermal communication with the device under test. The LBIST controller is configured to receive device temperature information from the thermal sensor and to modify control signals that are provided to the LBIST circuitry in order to cause the LBIST circuitry to operate in a manner that drives the device temperature to a desired level. In one embodiment, the LBIST controller adjusts the speed with which the LBIST circuitry scans data into and out of a plurality of scan chains, thereby adjusting the amount of heat generated by this operation, which in turn affects the temperature of the device.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: A testing apparatus having testing module slots onto which different types of testing modules are selectively mounted includes controlling modules for supplying control signals to the testing modules mounted on the testing module slots. The control signals are used for controlling the testing module. The apparatus also includes a setting information supplying unit for supplying hardware setting information to a specific testing module, an enable signal controlling unit for instructing the specific testing module to generate and supply an enable signal to the controlling module corresponding to the specific testing module, and a setting unit for setting the controlling module received said enable signal from the specific testing module so as to supply the control signal corresponding to the specific testing module based on the hardware setting information.

Abstract: An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns.

Abstract: A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an integrated circuit tester. In a system that includes a rule-based controller for controlling interaction between the test-head controller of an integrated circuit tester and an automated debug system, the invention includes a knowledge framework and a rule-based editor. The knowledge framework stores test knowledge in the representation of rules that represent a debugging strategy. The rule-based editor facilitates the use of rules as knowledge to debug or optimize an in-circuit test that is to be executed on the integrated circuit tester.

Abstract: A method for performing an electromigration check and detecting EM problems in a device or circuit. The method uses the capacitance and resistance of the conductors of the device or circuit as parameters in determining a power limit that maintains a required temperature environment that ensures the reliability of the device or circuit. The power limit is then used to check each device interconnect to identify the location of potential EM problems. Corrective action is taken to avoid EM problems as they are detected in the device or circuit.

Abstract: A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.

Abstract: A method and system for providing centralized access to instrumentation count event information generated by simulation testing of a hardware simulation model, in which simulation testing is performed within a batch simulation farm by multiple simulation clients communicating with an instrumentation server. An entitylist that includes an identifier for each design entity within said hardware simulation model that has at least one instantiated instrumentation count event is generated within a simulation client. The entitylist is delivered from the simulation client to the instrumentation server. Within the instrumentation server, the entitylist is associated with an identifier for the hardware simulation model such that instrumentation count event information is accessible from said instrumentation server by individual design entity information.

Abstract: An asynchronous system for testing disk drives includes a test platform that includes a plurality of slots for receiving and for providing communication with drives. The slots are segregated into a plurality of groups configured to satisfy predetermined environmental, communication bandwidth and test schedule requirements of the drives to be loaded therein. An automated loader/unloader is configured to selectively load drives into and out of the platform and to move drives between the plurality of groups. A module controller is assigned to each group of slots, each module controller being coupled to the slots of its assigned group and configured to administer at least one test to drives loaded in its assigned group while insuring that the predetermined environmental, communication bandwidth and test schedule requirements of its assigned group remain satisfied.

Abstract: A method for testing each one of the CPUs on each one of the plurality of director printed circuit. Results from such test are collected in a memory of a computer. The results are collected in a predetermined format. The method processes the collected data to present the results of the tests on a display of the computer in a different format. The different format comprises lines of information on the computer display. Each one of the lines of information identifies a corresponding one of the CPUs and indicates whether such corresponding one of the CPUs passed or failed the testing thereof.

Abstract: A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.

Abstract: A method for testing an output circuit of a semiconductor device including a plurality of output circuits includes the step of turning ON p-ch and n-ch MIS transistors of a subject output circuit, turning ON and OFF one and the other, respectively, of p-ch and n-ch MIS transistors of another output circuit used as a reference output circuit, measuring the potential difference between the output terminal of the subject output circuit and the output terminal of the reference output circuit and the penetrating current of the subject output circuit, and calculating the ON-resistance of the p-ch or n-ch transistor of the subject output circuit.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.

Abstract: A testing system is disclosed for testing a packaged device having a body with a package profile and an array of contacts coupled to the body. In one embodiment, the system includes a socket having a receiving area and an array of leads arranged to engage the array of contacts on the packaged device. The system of this embodiment also has a package handling assembly with a placement head and an alignment element coupled to the placement head. The alignment element is movable with the placement head as a unit relative to the socket. The alignment element is positionable in the receiving area of the socket. The alignment element restricts movement of the packaged device in at least two dimensions relative to the array of leads when the packaged device is positioned in the receiving area adjacent to the array of leads.

Abstract: Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each one of a plurality of wafers using a semiconductor wafer fabrication process. An average yield value associated with a plurality of ICs or portions of an IC formed on each one of the plurality of wafers using the semiconductor fabrication process is determined. A transformed yield value associated with the IC or portion of an IC is generated using the actual yield value and the average yield value.

Abstract: The invention provides a test apparatus for testing circuit units (101a–101k) to be tested by means of a test system (100), having a connection device (102), tester channels (103a–103m) for connecting the test system (100) to the connection device (102) and receptacle units (104a–104k), having a number (n1, n2, . . . , nk) of circuit unit data channels dependent on the circuit units (101–101k) to be tested, provision being made of a changeover device (200) for changing over the tester channels (103a–103m) to the receptacle units (104a–104k), and it being possible to divide a number (m) of tester channels (103a–103m) between the number (n1, n2, . . . , nk) of circuit unit data channels in a predeterminable manner.

Abstract: An apparatus, system, and method are disclosed for testing an analog to digital converter with a known analog signal applied. A first register module stores a first digitized instance of an analog signal. A second register module stores a second digitized instance of the analog signal. A difference module calculates the absolute difference between the first and second digitized instances. A bad code module identifies an erroneous digitized instance wherein the absolute difference is greater than a limit value. In one embodiment, a counter module counts the erroneous digitized instance. A test system may identify a failed analog to digital converter if the erroneous digitized instance count is greater than a specified target value.

Abstract: To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.

Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Abstract: A semiconductor test data analysis system (1) automatically recording, during an analysis operation, operation information of the analysis operation, including analysis conditions or an analysis procedure for input test data, or analysis information obtained by the analysis operation. The analysis system includes a processing means (101), an analysis target data storage means (109), which stores the test data as analysis target data, a historical data storage means (107), which stores as historical data either operation information of the analysis operation or analysis information obtained by the analysis operation, and a display data storage means (112), which stores analysis information obtained by the analysis operation, which stores analysis display data generated by the processing means for the purpose of displaying the analysis information obtained by the analysis operation.

Abstract: A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database, and utilizes the tracking process to update the electronic die-strip map database as the die-strip moves in an in-line fashion from one sub-station to another within the manufacturing process. Information used to update the database can originate from one or more automated visual camera systems used for quality assurance. In so doing, the present invention categorizes the die on the die-strip based on information maintained by the electronic die-strip map database. This information can be used for die sorting and for die rejection. In one embodiment, an identifying code is placed on each die strip that can automatically identify the die-strip using the automated camera systems.

Abstract: A method and system for disabling an instrumentation event in a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. An instrumentation event disable list is assembled within the instrumentation server. The assembly of the event disable list includes identifying an instrumentation event to be disabled during simulation processing of the simulation model, and delivering to the instrumentation server an instrumentation event name corresponding to the instrumentation event to be disabled. Prior to simulating the simulation model within the simulation client, the instrumentation event disable list is retrieved from the instrumentation server, and instrumentation events are disabled as specified within the instrumentation event disable list.

Abstract: A tester routine is provided that evaluates multiple test pins, on multiple devices under test, at the same time and only if a fail occurs does any evaluation have to be made. In the case of a failing pin on any device only that device with the falling pin is retested until passed or if not passed after a specified time the device is considered a fail.

Abstract: Structures and methods for non-intrusive testing of communication signals exchanged between two circuit boards via an intermediate interconnect board. In one aspect hereof, the functional signal normally exchanged between the circuits is latched during the exchange of test signals and the latched functional signal is utilized within the circuit that normally receives the functional signal to continue normal operations. In another aspect hereof, the test signals are exchanged over a dedicated test signal path between the two circuits. In another aspect hereof, the test signals are exchanged over the functional signal paths as out of band signals.

Abstract: A test methodology for use in a manufacturing process includes generating a test management matrix having a plurality of selectable test sites. Each test site indicates the optimum level of tests to be exercised on devices used to manufacture a product, such as a personal computer. Each test site is accessed through the intersection of inputs relating to aggregate test levels and quality of components used in the device. The tests identified at a selected test site are exercised to test the device.

Abstract: An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.

Abstract: A test manager software program includes an interactive test graphical-user-interface (GUI) for testing network devices using high-level networking commands. The test GUI allows the test engineer user to enter high-level commands such as Simple Networking Management Protocol (SNMP) commands that read values in a management information database in a network device under test. The high-level commands can be sent from the test manager using a command-line interface (CLI) in a telnet session opened to the network device during testing. The user specifies high-level test, analyze, and restore commands in test cases that are collected into test suites. Rules for logging on to the network device under test are stored that include expected prompts from the network device and user responses such as passwords. Addresses of the network device under test can be re-mapped for testing other devices so the test suites can be reused.

Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

Abstract: A test device for testing relays is provided. The test device includes a chassis and a plurality of generator components removably coupled to the chassis. Each of the plurality of generator components have a signal generator, a CPU to promote test signal generation by the signal generator, and an amplifier to amplify signals generated by the signal generator. The test device also includes a controller coupled to communicate with the plurality of generator components.

Abstract: A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.

Abstract: Disclosed is an improved method of determining mutual inductance of wires in an electronic design. First, the invention selects a pair of wires. Then, the invention adds concentric ring lines to the design. The invention then adds straight line segments representing each wire between points where each corresponding wire crosses the adjacent ring lines. Each of the straight lines run from a point where a corresponding wire crosses an outer concentric ring line to a point where the corresponding wire crosses an inner concentric ring line. The invention can then very simply calculate the mutual inductance between the straight line segments (not the actual potentially non-linear wires themselves). The mutual inductance of the straight line segments only comprises an approximate mutual inductance of the wires because the actual mutual inductance of the wires may be slightly different if the wires are non-linear.

Abstract: In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.

Abstract: A test device for testing an electronic device having a plurality of device terminals that receive a signal, includes: an operating condition outputting unit for outputting an operating condition indicating an operation of a signal to be supplied to a device terminal to be associated with said device terminal; and a test module for supplying a test signal used in a test of the electronic device to the electronic device based on the operation indicated by the operating condition.

Abstract: A system LSI includes a plurality of circuit blocks; a first power supply terminal, which is connected to a first circuit block; and a second power supply terminal, which is connected to a second circuit block. A first level of test voltage is applied from the first power supply terminal to the first circuit block for a predetermined period of time whereby the first circuit block is tested in operation. A second level of test voltage is applied from the second power supply terminal to the second circuit block for a predetermined period of time whereby the second circuit block is tested in operation independently from the first circuit block.

Abstract: A method and apparatus for generating a system specific test by providing sophisticated error tracking mechanisms to trigger on a specific system event. The present invention addresses the problem of monitoring network traffic and isolating a point of error at the testing stage. The present invention defines a specific system event to be monitored. A trigger is created in the host system and routed to the analyzer, wherein the trigger is used to allow the analyzer to capture information related to the specific system event. When a signal is received at the analyzer, the signal automatically triggers the analyzer to capture and store a predetermined amount of data related to the specific system event before and after the trigger is executed.

Abstract: A system for dynamically implementing a plurality of virtual local area networks (“VLANs”) across multiple sites is provided. The system includes a first VLAN-capable switch at a first site; a first system under test (“SUT”) connected to the first VLAN-capable switch via a first burn rack switch; a second VLAN-capable switch located at a second site remote from the first site; a second SUT connected to the second VLAN-capable switch via a second burn rack switch. The first and second VLAN-capable switches are connected such that the first and second SUTs are connected to a single virtual private network (“VPN”). The connection may include either first and second routers respectively connected to the first and second VLAN-capable switches and interconnected via a T1 line or an ATM connection.

Abstract: One or more methods and systems of validating the operation of one or more register designs are presented. In one embodiment, the system utilizes a processor, an integrated circuit design simulator software, a storage media, a storage device, user interface, and a display. In one embodiment, the method includes executing a set of instructions operating on a register design parameter file to produce an output that is easily incorporated into the integrated circuit design simulator software. The output specifies one or more tests to be performed using the integrated circuit design simulator software. The one or more tests are subsequently performed to validate the register design. The method automates the incorporation of register design parameters into the integrated circuit design simulator software by way of executing a set of instructions that operates on the register design parameter file.

Abstract: According to the invention, a method and an apparatus are provided for determining bus system parameters and/or configurations, in particular of field bus systems, in the form of digital information, lists, plans and graphical representations, which apparatus comprises a device for detecting, storing and selecting both machine-related and bus-related data and, furthermore, has at least one output device for outputting and/or displaying and/or transmitting data.

Abstract: A method of testing a DUT is provided. The method comprises loading a memory within a link-based system with a functional test program, executing the functional test program in a processor core of the link-based system, and routing test signals generated during execution of the functional test program to a response agent embedded in the link-based system via an external path.

Abstract: Apparatus for electrical testing of electrical circuits includes an array of probes arranged for selective engagement with portions of electrical circuits to be tested, testing circuitry associated with the array of probes for sensing electrical characteristics of the electrical circuits engaged by the array of probes, and control circuitry associated with the array of probes for causing engagement between selected ones of the array of probes with selected ones of the portions of electrical circuits to be tested. The array of probes includes at least two static probe assemblies arranged in a fixed array, and the static probe assemblies include a selectively positionable probe element and a probe element positioner. The apparatus is employed to test electrical circuits during fabrication.

Abstract: A system for testing integrated circuits by testing the change of integrated circuits under various temperatures comprises: at least one two-dimensional matrix testing module which includes a testing section having arrays for plugging integrated circuits to be tested, a heating section corresponding with the above testing section for heating integrated circuits respectively; a computer mainframe for connecting said two-dimensional matrix testing module and controlling the whole operations of the testing system, and a database. With the above-described structure, said database and said two-dimensional matrix testing module can be connected with the computer mainframe such that the temperature control information can be transmitted to provide each heater of said heating section to generate a suitable temperature, heat the integrated circuit to be tested, and store the test information.

Abstract: A system for de-embedding electrical characteristics to obtain the intrinsic electrical characteristics of a device under test. The system includes obtaining a set of S parameter data from measurements of a thru test structure and partitioning that set into a set of input S parameters and a set of output S parameters. The set of input S parameters and the set of output S parameters are converted to sets of input ABCD parameters and output ABCD parameters, respectively. An inverse matrix of the set of input ABCD parameters is cascaded with a matrix of a set of ABCD parameters representative of the electrical characteristics of a test structure including the device under test. The resultant matrix is then cascaded with the inverse matrix of the set of output ABCD parameters to obtain a set of device ABCD parameters representative of the intrinsic electrical characteristics of the device under test.

Abstract: Latent faults are detected by a testing system in a redundant DC power supply system having at least two power supplies connected to a common load via respective isolation devices. The testing system selects as a subject for a test procedure one isolation device and its corresponding power supply. The power supplies are controlled during the test procedure to marginally vary the output voltage of at least one power supply such that a differential voltage is applied between the output of the selected power supply and the outputs of the remaining power supplies for selectively changing the conductive state of at least one isolation device to a non conductive state by reducing its forward voltage to less than its respective forward bias voltage value.

Abstract: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.