Abstract: A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.

Abstract: A method and apparatus for testing assisted position location capable devices that includes providing a position determination entity (PDE) simulator that is in communication with a base station simulator simulating one or more base stations and connecting an assisted position location capable device under test (DUT) to the base station simulator and a global positioning system (GPS) simulator. Then, initiating a test sequence wherein the DUT receives a set of predetermined GPS signals and at a desired time the DUT requests assistance data from the base station simulator and the base station simulator requests assistance data from the PDE simulator, wherein the PDE simulator provides data that is independent of the GPS simulator data to the base station and the base station transfers the PDE data to the DUT. The PDE data is a set of predetermined responses to any one of a plurality of DUT requests indexed by elapsed test time.

Abstract: Disclosed is a method and mechanism for sizing a hardware system for a software workload. An aspect is directed to modeling a workload into a set of generic system activities, in which the generic system activities are not directly tied to a specific hardware platform. Another aspect is directed to profiling hardware systems or hardware components into the generic system activities. Suitable hardware systems or components are selected by analyzing the workload and hardware profiles in terms of the generic system activities.

Abstract: The present invention reveals a method for manufacturing identification codes of integrated circuit. A number of the test machine, a serial number and a period of time ahead of loading a test pattern are written into an integrated circuit in the process of testing as the identification code. Thus, the identification codes of each integrated circuit of normal lot, re-testing lot and quality control lot is distinct to avoid the problems caused by repetitive identification codes.

Abstract: An intergrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. Accordingly, the trace export can operate at a frequency independent of the operation circuit.

Abstract: A test apparatus simultaneously tests a plurality of semiconductor integrated circuits according to test data stored in a single memory set. A sub-test data generator includes a plurality of data reproduction units, each of which corresponds to one of the integrated circuits being tested. Each data reproduction unit reproduces the stored test data into a reproduced test data set, which is then processed by a driver, and sent to the corresponding integrated circuit for testing.

Abstract: The present invention is directed to a method and system for automating data storage array components testing. A serial number of a data storage array component (i.e., product) is used to determine if the product is of high priority (rank) in comparison with other products in a queue and there is any test cell available for testing the product. Next, if a test is required, the product type and test requirements of the product are retrieved from a database based on the serial number, and the product is routed to the test cell from an assembly line. Then the product and a storage component interface module of the test cell are positioned so that the product and the storage component interface module face each other. The storage component interface module is chosen based on the test requirements retrieved from the database. Next the product is docked into the storage component interface so that the product is connected to the storage component interface module. Then the test is run to completion.

Abstract: An automatic tester for an analog micromirror device includes a computer having an ADC and DAC connected to its peripheral bus. A micromirror device under test is mounted on a black box containing a light source such as a laser and a position sensitive device. The light beam is reflected by the micromirror device onto the position sensitive device so that the deflection of the mirror in two axes can be measured. The output of the position sensitive device is amplified and coupled to the ADC via a tester board. The computer can test the micromirror device to detect mechanical failure and to measure the resonant frequency and Q of the driving coils, and SNR of the internal package feedback which measures the position of the mirror.

Abstract: The invention provides a method for testing oscillators in which cracks and chips on oscillator chips that may possibly have an effect on the oscillation characteristics can be detected efficiently, without using an optical examination device and an image processing device, which require troublesome adjustment and higher cost. When testing the oscillation characteristics of oscillator chips, the method comprises a network analyzer, an upper electrode, a lower electrode, an oscillator chip, a bush, and a personal computer. The personal computer is connected to the network analyzer using a GP-IB interface cable, and is capable of storing, displaying, and comparing all measurement results of the network analyzer. The upper electrode can be shifted vertically by a vertical mechanism.

Abstract: In one aspect of the present invention, an apparatus is provided for testing a plurality of devices. The apparatus, in one embodiment, comprises a controller, a device identifier capable of identifying each one of a plurality of devices as one of a plurality of device types, and a plurality of test heads. Each test head is capable of testing each one of the devices independently of the rest of the plurality of test heads responsive to the identification of each device by the device identifier and under the control of the controller. In a second aspect of the invention, a method is provided for testing a plurality of devices.

Abstract: A system and method for comparing performance of two or more devices is disclosed. The method includes defining a workload. A workload object is provided. The workload object includes a transaction generator. A first test case is applied to a first device. Executing the transaction generator on a first test object produces the first test case. The first test object includes multiple first interface properties. Executing the transaction generator on the first test object produces a first set of transactions according to the first interface properties. The first set of transactions stimulates the defined workload in the first device. A second test case is applied to a second device. Executing the transaction generator on a second test object produces the second test case. The second test object includes multiple second interface properties. Executing the transaction generator on the second test object produces a second set of transactions according to the second interface properties.

Abstract: A method of judging whether an electronic component is good or defective in accordance with a response output signal by inputting a test signal to the IC to be tested, wherein a common test signal is input to respective electronic devices A1 and A2 of a group of electronic devices composed of a plurality of electronic devices, and in accordance with a response signal thereof, the group of electronic devices as a whole subjected to the test is judged to be good or defective. In the second test, each of the DUTs A1 and A2 of the group of electronic devices judged to be defective is input a mutually independent test signal, and in accordance with the response signal thereof, it is judged whether each of the electronic devices A1 and A2 subjected to the test is good or defective.

Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: A hybrid model formed from a semi-physical device model along with an accurate data-fitting model in order to implement a relatively accurate physical device model as a large signal microwave circuit computer-aided design (CAD) tool. The semi-physical device model enables accurate representation of known physical device characteristics and measured bias-dependent characteristics. This model is used to accurately simulate the effect of process variation and environmental changes on bias-dependent characteristics. The data-fitting model is used to model these characteristics with relatively good fidelity. The expressions of the model are constructed to be charge conservative. As such, the model is computationally robust within the harmonic balance algorithms employed by known large signal microwave circuit CAD tools.

Abstract: A manufacturing method of a semiconductor integrated circuit device includes the steps of: providing wiring conductors capable of connecting between chips or devices and variable switching devices capable of connecting between predetermined wiring conductors on a wafer formed of a microcomputer built-in chip having a CPU and a writable memory circuit for storing an operation program or on a testing board provided with a microcomputer built-in device enclosed by a package; writing a testing program including the transmission and reception operation of signals between the devices or chips into the memory circuit re-writable and capable of using as a program storing area for one of the chips or devices; and executing the testing program in the CPU of the chip or device, thereby testing a testing chip, between the device and the testing chip or an input/output circuit of the device.

Abstract: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted.

Abstract: A test circuit includes an input circuit for inputting data to select a test mode relative to a circuit to be tested and outputting result of selection of the test mode in synchronization with a first clock, a pattern generation circuit for responding to result of selection of the test mode, generating a test pattern in synchronization with a second clock and outputting the test pattern to the circuit to be tested and a comparator circuit for inputting result of test of the circuit to be tested in synchronization with the second clock, and comparing coincidence/non-coincidence between the result of the test and the test pattern supplied to the circuit to be tested. The test circuit further includes an output circuit for holding result of comparison by the comparator circuit and outputting the result of comparison in synchronization with the first clock.

Abstract: An electrical connection test is conducted within a practical response time every time a harness-forming wire is connected on a compact assembling board. Multiplexing communication controllers adopting a perfect time-division multiplexing communication method according to which tokens are given to units by a time-division technique based on timing bit sets issued at specified intervals from any of the units and node addresses are provided. Every time a harness-forming wire is connected, an electrical connection of a network of a wiring harness including this harness-forming wire is tested. In this electrical connection test, whether the network is satisfactory is determined up to a last stage every time the harness-forming wire is connected in the production process of the wiring harness being tested.

Abstract: A programmable voltage divider has normal and test modes of operation. The divider includes first and second supply nodes, a divider node that provides a data value, and a first divider element that is coupled between the first supply node and the divider node. The divider also includes a controlled node, a second divider element that has a selectable resistivity and that is coupled between the divider node and the controlled node, and a test circuit that is coupled between the controlled node and the second supply node. During the normal mode of operation, the first and second divider elements generate the data value having a first logic level when the second divider element has a first resistivity, and generate the data value having a second logic level when the second divider element has a second resistivity. The test circuit generates a first voltage at the controlled node during the normal mode of operation, and generates a second voltage at the controlled node during the test mode of operation.

Abstract: The present invention provides a method and computer readable medium with program instructions for automatically verifying bus transactions. The method includes: parsing a parameter code for the bus transactions, wherein the parameter code comprises a plurality of expected parameter values for the bus transactions; automatically integrating the parsed parameter code into a checking program; and automatically executing the checking program, wherein the checking program compares the plurality of expected parameter values with a plurality of actual parameter values for the bus transactions. The bus transaction verification method in accordance with the present invention automates the coding of expected parameter values for each test case into a checking program and automates the execution of the checking program, where the checking program compares the expected parameter values with the actual parameter values.

Abstract: This invention presents a new “Hit-or-Jump” system and method for embedded testing of components of communication systems that can be modeled by communicating extended finite state machines. It constructs test sequences efficiently with a high fault coverage. It does not have state space explosion, as is often encountered in exhaustive search, and it quickly covers the system components under test without being “trapped”, as is experienced by random walks. The algorithm has been implemented and applied to embedded testing of telephone services in an IN architecture, including the Basic Call Service (ECS) as well as other supplementary services.

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: A method and circuit for determining the accuracy of a measurement of a bit line voltage or a charge distribution for readout from FeRAM cells uses sense amplifiers to compare a bit line voltage to a series of reference voltages and then determines upper and lower limits of a range of range of reference voltages for which sensing operation provide inconsistent results. One embodiment uses an output signal of a sense amplifier to control a pull-down transistor of an I/O line and alternative precharging schemes for the I/O line allow determining both limits using the same compression circuitry to process a result value stream on the I/O line.

Abstract: The present invention reveals a method for manufacturing identification codes of integrated circuit. A number of the test machine, a serial number and a period of time ahead of loading a test pattern are written into an integrated circuit in the process of testing as the identification code. Thus, the identification codes of each integrated circuit of normal lot, re-testing lot and quality control lot is distinct to avoid the problems caused by repetitive identification codes.

Abstract: A semiconductor test data analysis system (1) automatically recording, during an analysis operation, operation information of the analysis operation, including analysis conditions or an analysis procedure for input test data, or analysis information obtained by the analysis operation. The analysis system includes a processing means (101), an analysis target data storage means (109), which stores the test data as analysis target data, a historical data storage means (107), which stores as historical data either operation information of the analysis operation or analysis information obtained by the analysis operation, and a display data storage means (112), which stores analysis information obtained by the analysis operation, which stores analysis display data generated by the processing means for the purpose of displaying the analysis information obtained by the analysis operation.

Abstract: The present invention provides a semiconductor test system and a monitor apparatus for monitoring a test history such as numbers of operation of relays. The semiconductor test system tests a semiconductor device by controlling test circuits therein through a tester bus and monitors the test history. The test system includes a plurality of buffer circuits for receiving signal information from the tester bus and storing the signal information therein, and a computer for storing the signal information from the buffer circuits in a file and analyzing the signal information in the file.

Abstract: A test system for circuits which is capable of selecting any one of a plurality of circuits to be tested and testing a selected circuit to be tested, includes a tested circuit data producing unit which produces tested circuit data concerning any one of several circuits to be tested; and a control unit which controls a plurality of programmable gate arrays (PGAs) on the basis of an output of the tested circuit data producing unit. Furthermore, the test system for circuits includes a plurality of PGAs each of which is connected to the control unit and generates a test pattern in response to control data sent from the control unit according to a program; and interface units which are associated with the plurality of PGAS, respectively, and are connected to the circuits to be tested.

Abstract: Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.

Abstract: A noise analyzing method analyzes a crosstalk noise based on circuit data in which buses having the same signal transmitting direction and buses having opposite signal transmitting directions are distinguished from each other, by analyzing the crosstalk noise only for the same signal transmitting direction with respect to the buses having the same signal transmitting direction.

Abstract: A system for dynamically implementing a plurality of virtual local area networks (“VLANs”) across multiple sites is described. In one embodiment, the system includes a first VLAN-capable switch at a first site; a first system under test (“SUT”) connected to the first VLAN-capable switch via a first burn rack switch; a second VLAN-capable switch located at a second site remote from the first site; a second SUT connected to the second VLAN-capable switch via a second burn rack switch; and means for connecting the first and second VLAN-capable switches such that the first and second SUTs are connected to a single virtual private network (“VPN”). The means for connecting may consist of either first and second routers respectively connected to the first and second VLAN-capable switches and interconnected via a T1 line or an ATM connection.

Abstract: An output signal from a level detection circuit that detects a super VIH (normal logical high voltage level) condition is set to a valid state or to an invalid state by a force circuit and is applied to a test control circuit. A test mode with the super VIH (SVIH) condition can be entered efficiently, while the possibility of an erroneous entry on the user side and constraints of the test apparatus upon serial test entry are suppressed.

Abstract: A system and method is provided for testing industrial control modules. Input and output stimulus signals, communication lines, measurement device lines and relay contacts are provided at a tester interface panel. This allows for a test developer to configure the relay contacts in any way that the developer desires to provide appropriate connections of stimulus, communications and measurements for a given industrial control module. The switching of the relays between a normally closed position and a normally open position can be controlled by output modules coupled to a computer. The relays can be insertable and releasable in a socket for easy fault isolation and replacement. Furthermore, the same relays or similar relays can be employed for both low current measurements and high power stimulus.

Abstract: A method for identifying an integrated circuit having a latent defect. Test data corresponding to a set of integrated circuits is obtained, where the set of integrated circuits was processed on a single substrate. A subject integrated circuit is selected for analysis from within the set. A subset of integrated circuits is identified from within the set, where the subset includes integrated circuits that were located in close proximity on the substrate to the subject integrated circuit. The test data for the subset is analyzed to determine a defect parameter for the subset. The defect parameter for the subset is compared to a threshold. The subject integrated circuit is classified as having a latent defect when the defect parameter for the subset violates the threshold, and the subject integrated circuit is classified as not having a latent defect when the defect parameter for the subset does not violate the threshold.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

Abstract: A method for performing electrical acceptance tests on a sub-system including a test substrate, a microprocessor and one or more associated computer components, such as SRAM, DRAM and ROM. A pin grid array, ball grid array, line grid array or equivalent test connector system is provided that allows direct addressing of selected circuits of the microprocessor and of each associated component. The microprocessor plus substrate are first tested together. If this test is successful, the associated components are then added, preferably one at a time, and the new sub-system is tested. If a particular sub-system fails a test, the cause(s) of failure can be isolated and removed, where possible, and the modified sub-system can be retested.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: There is provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, comprising the steps of (a) assuming that all integrated circuits under test define a under-test integrated circuit set, and testing each one of the integrated circuits in the under-test integrated circuit set in a conventional manner, (b) removing integrated circuits having been judged to be in failure in the step (a), from the under-test integrated circuit set, (c) measuring spectrum of a current supplied from a power source into each one of the integrated circuits in the under-test integrated circuit set, (d) calculating both a mean value and standard deviation of the spectrum for the under-test integrated circuit set, (e) judging whether an integrated circuit is in failure or in no failure, based on both the mean value and the standard devia

Abstract: An apparatus and method for tracking data for individual integrated circuits through the manufacturing process is described by programming an individual part identifier into a non-volatile portion of the integrated circuit and maintaining a database of all manufacturing step statistics for later review and analysis. The part identifier allows individual integrated circuits to be moved through the manufacturing process without the need to physically track original fabrication lots. The database of information is used to improve the manufacturing process by identifying failure trends based upon process variations.

Abstract: An apparatus compares propagation delay of electronic by using flip-flops or similar storage elements. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock delay. The strobe source triggers the pattern source to output signal a sequence of signals to an input terminal of an element or device under test (DUT). The DUT propagates the signals to a flip-flop. The output signal of the flip-flop is captured after a delay. The propagation delay of the DUT is determined by coinciding the clock signal edge with the data signal edge to the flip-flop so that the flip-flop enters the ambiguity region. Once the delay settings that define the ambiguity region under the same delay are determined for various DUTs, they are compared to determine which DUT has the least propagation delay.

Abstract: An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.

Abstract: A system for generating a pruned diagnostic list of potential bridging faults in a circuit includes a pattern generator operable to generate test patterns for testing a circuit and a tester in communication with the pattern generator that is operable to apply the test patterns to the circuit and generate a plurality of resultant vectors. The system also includes a stuck-at fault dictionary including a list of a plurality of nets of the circuit, each net having at least one resultant vector that indicates a potential stuck-at fault at the net. The system further includes a test analysis tool in communication with the pattern generator and the tester, the test analysis tool operable to create an initial logical diagnostic list of tested nets of the circuit associated with the potential stuck-at faults indicated in the stuck-at fault dictionary, the initial logical diagnostic list created in response to the generated plurality of resultant vectors.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: A tester for a mixed signal semiconductor device having a reconstructed digital tester, and a method of testing a semiconductor device using the same are provided. A digital tester electrically tests a digital device and is controlled by a first controller. A metrology instrument module comprising an analog source generator for applying an analog signal to a semiconductor device, an analog waveform digitizer for analyzing the analog signal into a digital signal, and a personal computer including a second controller forms a part of the digital tester, and the first controller is connected to the metrology instrument module through an interface line.

Abstract: A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circuit board to a receiver located on a second circuit board. The receiver on the second circuit board includes an analog-to-digital signal converter, an equalizer, and a binary digital-to-analog reconverter for receiving the training sequence. The equalizer preferably comprises a series of connected registers having taps in between, a plurality of individual weighting means attached to each of the taps, and a summing means connected to the weighting means. A training sequence is transmitted from the first circuit board to the receiver on the second circuit board, enabling the receiver to adaptively determine a set of weighting means coefficients for correcting the multipath errors in subsequent signals.

Abstract: A method of tracking information associated with an integrated circuit on a substrate after it has been diced. A set of parameters is collected during a first testing process. A first signature is determined for the integrated circuit, based on the set of parameters collected during the first testing process. The first signature and other information are associated with the integrated circuit. The integrated circuit is diced. The set of parameters is collected anew during a second testing process. A second signature is determined for the integrated circuit, based on the data set of parameters collected anew during the second testing process. The second signature is compared to multiple first signatures to locate the first signature that substantially matches the second signature. The other information associated with the first signature is associated with the diced integrated circuit.

Abstract: A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating IC's on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad IC's on the wafer and the fuse ID's of the IC's on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad IC's that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

Abstract: A testing unit is provided with a test data communication port adapted to output test data to a device being tested. The testing unit also has an expected test result data communication port adapted to output expected test result data to the device. The device being tested generates test result data in response to the test data, and compares the test result data with the expected test result data to generate test status data, such as a pass or fail indication.

Abstract: A method for testing continuity of an ISUP relay call in an ISUP network consisting of a proceeding switching system and a following switching system, in which, in setting up a call, a preceding switching system transmits a call set-up message, that is, an initial address message (IAM), for continuity testing to a following switching system and at the same time forms a communication path loop, and upon receipt of the IAM, the following switching system transmits a testing sound to the communication loop to test continuity of the communication path.

Abstract: A wrap test for a communication interface unit used for a computer, etc. When a wrap tool 40 is connected to a SCSI device 10, a signal (TEMPWR) is output from an output device 38 to SCSI connectors 22 and 24 through a Y-type cable 14, then wrapped in the wrap tool 40 and returned to a SCSI controller 12 through resistors 28 and 30 as a signal (PSCSIWRAP) to recognize the wrap tool 40. Because the non-grounded end of a resistor 26 is connected to an input terminal of the SCSI controller 12, the resistors 28 and 30 are connected in parallel. The potential of the signal (PSCSIWRAP) is stabilized by the resistors 26, 28 and 30. If a single wrap tool is connected to the SCSI device 10, the potential of the signal (PSCSIWRAP) is stabilized by the resistors 26 and 28 or 30.

Abstract: Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.