Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: Described within is a power management system for a computing platform that provides additional reductions in power consumption from that provided by only periodically putting the CPU or peripheral devices in low power non-operational states. In particular, the embodiment prevents the OS from generating an interrupt due to timer ticks while in a non-C0 state, until such time as a number of timer ticks have been gathered.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: A method of calibrating a first clock signal using a second clock signal and a plurality of calibration periods may include generating incremented counter values at a counter responsive to edges of the second clock signal. For at least two of the plurality of calibration periods, an initial incremented counter value from the counter may be stored in memory at an initial edge of the first clock signal for the respective calibration period, a final incremented counter value may be stored in memory at a final edge of the clock signal for the respective calibration period, and the at least two of the plurality of calibration periods may be overlapping with different initial and final edges of the first clock signal. For each of the plurality of calibration periods, a number of edges of the second clock signal occurring during the respective calibration period may be determined using the initial and final incremented counter values stored in memory.

Abstract: In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.

Abstract: Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB).

Abstract: A system for controlling a multiple cylinder internal combustion engine with electromagnetic valve actuation, comprising of at least one cylinder with an engine cylinder valve, a second controller operably coupled to the engine cylinder valve, said second controller configured to adjust at least one of the valve opening and closing timing of the engine cylinder valve, and a first controller connected with the second controller over a first link and a second link, wherein the first controller is configured to send an engine position indication signal to the second controller over the first link and receive a status signal from the second controller over the second link, and wherein the first controller outputs a synchronization degradation signal responsive to a synchronization error between the engine position indication signal and the status signal.

Abstract: A method for estimating values assumed at a certain instant of each period by currents flowing respectively in two distinct windings of a poly-phase load controlled in a space vector modulation (SVM) mode, using a same measuring device, may include coupling the measuring device to the first winding and measuring a current flowing therethrough with an anticipation from the certain instant smaller than or equal to an SVM half-period. The method may also include coupling the measuring device to the second winding, measuring a current flowing therethrough at the certain instant, coupling the measuring device to the first winding, and measuring a current flowing therethrough with a delay equal to the anticipation. The method may also include estimating a value assumed at the certain instant by the current flowing through the first winding based upon the two measured values with the anticipation and with the delay respectively.

Abstract: An environment sensor is mounted in a measurement unit. The measurement unit is adapted to be transported by a transportation apparatus. Measurement data from the environmental sensor is stored in a data format suitable for associating the measurement data with a state of the measurement unit.

Abstract: A method of calibrating glucose monitor data includes collecting the glucose monitor data over a period of time at predetermined intervals, obtaining reference glucose values from a reference source that temporally correspond with the glucose monitor data obtained at the predetermined intervals, calculating the calibration characteristics using the reference glucose values and corresponding glucose monitor data to regress the obtained glucose monitor data, and calibrating the obtained glucose monitor data using the calibration characteristics. In additional embodiments, calculation of the calibration characteristics includes linear regression and, in particular embodiments, least squares linear regression. Alternatively, calculation of the calibration characteristics includes non-linear regression. Data integrity may be verified and the data may be filtered. Further, calibration techniques may be modified during a fast rate of change in the patient's blood glucose level to increase sensor accuracy.

Abstract: An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test bus between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies.

Abstract: A selectable mode field transmitter is configurable to operate in one of a plurality of operating modes having different combinations of function, performance, and power consumption. The selectable mode field transmitter includes a housing, a sensor located within the housing, and transmitter circuitry for transmitting data provided by the sensor to a receiver external to the housing. The transmitter circuitry includes a controller that electrically configures the transmitter circuitry to one of a plurality of operational modes in response to mode selection data received from a source external to the housing. Therefore, the selectable mode field transmitter can be configured based on the needs or requirements of a particular application.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal.

Abstract: Sensor device times can vary and may be set significantly wrong. In one embodiment, the present invention can adjust a sensor's time by receiving a raw security event from a sensor device, determining whether a timestamp included in the raw security event is within a timerange around a time known by the agent, determining whether a time offset is in a non-initialized state, and determining whether to adjust the timestamp by applying the time offset to the timestamp, the determination being based on whether the timestamp included in the security event is within the timerange around the time known by the agent and whether the time offset is in a non-initialized state.

Abstract: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Abstract: Real-time clock calibration is accomplished by generating a fast clock signal and a slow clock signal from an uncompensated clock signal; selectively, momentarily, replacing the uncompensated clock signal with the fast and slow clock signal to generate a compensated clock signal; generating from the compensated clock signal a calibration strobe and window trigger; responding to the window trigger to detect any uncompensated clock signal frequency error and responding to the calibration strobe to selectively, momentarily, replace the uncompensated clock signal with the fast or slow clock signal to reduce the clock signal frequency error.

Abstract: Apparatus and method for increasing the sensitivity in the detection of optical coherence tomography and low coherence interferometry (“LCI”) signals by detecting a parallel set of spectral bands, each band being a unique combination of optical frequencies. The LCI broad bandwidth source is split into N spectral bands. The N spectral bands are individually detected and processed to provide an increase in the signal-to-noise ratio by a factor of N. Each spectral band is detected by a separate photo detector and amplified. For each spectral band the signal is band pass filtered around the signal band by analog electronics and digitized, or, alternatively, the signal may be digitized and band pass filtered in software. As a consequence, the shot noise contribution to the signal is reduced by a factor equal to the number of spectral bands. The signal remains the same. The reduction of the shot noise increases the dynamic range and sensitivity of the system.

Abstract: Systems, methods, and apparatuses including computer program products for oscillator calibration. In one aspect, a calibration module includes a monitor submodule that evaluates operation of a system to determine if the system is operating in a first mode or a second different mode, where the second clock source is not operating as expected in the second different mode; a calibration engine that determines a calibration value using the first clock source and the second clock source in response to the system operating in the first mode; and a register that stores the calibration value; where the calibration engine calibrates the first clock source using the calibration value and provides to the system the calibrated first clock source as a timing reference instead of the second clock source as the timing reference, in response to the system operating in the second different mode.

Abstract: A calibration system for a data storage device includes a memory and a memory control module. The memory buffers data between a host and the data storage device and generates a data strobe signal. The memory control module selectively adjusts a delay of the data strobe signal. Data is read from the memory based on the data strobe signal.

Abstract: A time-of-flight PET nuclear imaging device (A) includes radiation detectors (20, 22, 24), electronic circuits (26, 28, 30, 32) for processing output signals from each of detectors (20), a coincidence detector (34), a time-of-flight calculator (38) and image processing circuitry (40). A calibration system (48) includes an energy source (50, 150) which generates an electrical or optical calibration pulse. The electrical calibration pulse is applied at an input to the electronics at an output of the detector and the optical calibration pulse is applied to a preselected point adjacent a face of each optical sensor (20) of the detectors. A calibration processor (52) measures the time differences between the generation of the calibration pulse and the receipt of a trigger signal from the electronic circuitry by the coincidence detector (34) and adjusts adjustable delay circuits (44, 46) to minimize these time differences.

Abstract: A clock circuit for an integrated circuit having at least one MOS transistor. The clock circuit includes a first circuit for inducing a degradation of the transistor as a function of time and means for measuring a parameter of the transistor that reflects a lowering of the performance of the transistor resulting from the degradation. This also includes a method of generating a counting value of clock circuit by inducing continuous degradation of an MOS transistor. The method could include measuring a parameter of transistor, reflecting a lowering of performance of transistor resulting from said degradation. The method could also include measuring the temperature and calculating the counting value of the clock from the value of said parameter, from the measured temperature and from a law of variation of the parameter as a function of time and temperature.

Abstract: Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.

Abstract: A sensing system comprises a sensor that generates a calibration pulse and first sensor data and that transmits the first sensor data using a variable pulse width. A control module determines an age of the first sensor data based on a time difference between the calibration pulse and when the sensor data is at least one of received and used, that determines a rate of change of the sensor data based on N prior sensor data samples and the first sensor data samples, and that adjusts the first sensor data based on the time difference and the rate of change.

Abstract: In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.

Abstract: System and method for generating an application domain specific graphical program. A graphical user interface (GUI) for specifying functionality of a graphical program in an application domain is displayed, where the GUI corresponds specifically to the application domain. User input to the GUI specifying the functionality of the graphical program is received, and the graphical program generated in response, where the graphical program is executable to perform the specified functionality, and comprises multiple interconnected graphical program nodes that visually represent the graphical program functionality. The GUI includes graphical interface elements operable to indicate and/or specify, e.g.

Abstract: Static timing analysis attempts to exhaustively analyze all critical paths of a design. With ever decreasing geometries and ever increasing design complexity, manually identifying timing violations with standard static timing analysis can be very complex and time consuming. A static timing analysis tool can advantageously manage multiple runs having different modes and corners and automatically merge the results generated by the runs. The STA tool can perform the runs either in parallel or in series. Advantageously, the STA tool can save the full timing analysis generated by each run and then extract information from these saved results to form merged results for the design. These merged results can provide different levels of analysis coverage, supply path information at various levels of detail, allow selectable accessibility to information, and highlight propagation of timing changes/violations in the design.

Abstract: The frequency-sampling method is widely used to accommodate nonlinear electromagnetic source tuning in swept-wavelength interferometric techniques, such as optical frequency domain reflectometry (OFDR) and swept-wavelength optical coherence tomography (OCT). Two sources of sampling errors are associated with the frequency-sampling method. One source of error is the limit of an underlying approximation for long interferometer path mismatches and fast electromagnetic source tuning rates. A second source of error is transmission delays in data acquisition hardware. Aspects of the invention relate to a method and system for correcting to sampling errors in swept-wavelength interferometry systems such that the two error sources correct sampling errors associated with the first radiation path and the second radiation path cancel to second order.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Corresponding method and system for calibrating the cable are also provided.

Abstract: A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module, which is connected to the communication module via the system bus for transmitting measurement and/or control signals and is intended to input and/or output measurement and/or control signals to field applications, the at least one communication module having a time control unit for controlling a transmission cycle which is constantly repeatedly carried out and has defined communication times for the communication and input/output modules which are connected to the system bus, comprises measuring the signal propagation times on the system bus and defining the cycle time for a transmission cycle on the system bus on the basis of the longest signal propagation time measured.

Abstract: A measurement system including a plurality of test and measurement instruments; and a hub coupled to each of the test and measurement instruments. Each of the test and measurement instruments is configured to trigger an acquisition in response to a hub event received from the hub. Acquisitions can be triggered from one, some, any, or all of the test and measurement instruments.

Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

Abstract: A method and apparatus for synchronous communication in a control system is disclosed. Within a first time interval, a first source task is executed to broadcast a first destination task, within a second sequential time interval, the first destination task is communicated over a channel to a first destination, and within a third sequential time interval, the first destination task is consumed. Within the first time interval, a second source task may be executed to broadcast a second destination task, within the second sequential time interval, the second destination task may be communicated over the channel to a second destination, and within the third sequential time interval, the second destination task may be consumed. The first source task is allowed to be scheduled ahead of the second source task, and the second source task is allowed to be scheduled ahead of the first source task.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: Aspects of a method and system for generation of signals up to extremely high frequencies using a delay circuit are provided. In this regard, a variable delay circuit may be adjusted such that an output signal generated by the delay circuit may be twice the frequency of a signal input to the delay circuit. The adjustment may be via an variable capacitance and/or a variable number of delay elements utilized to generate the output signal. Moreover, the adjustment may be based on a signal strength of the output signal. In this regard, the delay may be adjusted to maximize the signal strength of the output signal. The input signal may be delayed to generate a second signal that is 90° phase shifted relative to the input signal. The second signal and the input signal may be mixed to generate the output signal. The output signal may be filtered by a bandpass filter centered at twice the frequency of the input signal. Accordingly, the center frequency of the bandpass filter may be tunable.

Abstract: A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.

Abstract: The invention provides a calibration tool for a vehicle monitoring device, the tool having a processor with a clock or access to a time signal and arranged for connection to and to receive and process signals from a vehicle on-board diagnostics unit (OBD), the processor having or connected to means for storing data relating to the vehicle and its engine and codes relating to signals from the available OBD outputs and inputs, the processor being programmed to calculate and store certain coefficients derived over the vehicle's operating range and to populate an array with the said coefficients so that the processor can look up the corresponding co-efficient from the array to calculate the desired value or output. The invention extends to a method of calibrating a calibration tool or a vehicle-monitoring device mounted in a vehicle provided with such a calibration tool.

Abstract: A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration of a counting of a digital clock. A time difference between a trigger at which a fine analog delay starts measuring time and the occurrence of a digital pulse of a stable clock used to count a coarse delay is measured. An input waveform is sampled at a sample time having a nominal delay time. After sampling, a desired compensation time is provided for the sample of the input waveform in accordance with combinations of three independent variables defining a calibration table. The waveform is reconstructed by shifting a delay time of a sampled value of the input waveform from its nominal delay time in accordance with a value defined by the calibration table.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: A system and method are disclosed for testing a settling time of a device-under-test (DUT). A method for determining a settling time of a device-under-test (DUT) includes activating a DUT to generate an output signal and mixing the output signal of the DUT and a reference signal to generate a mixed signal. An amplitude threshold is set for the mixed signal relative to an amplitude of the mixed signal and the settling time of the DUT is determined based on a last time that the amplitude of the mixed signal crosses the amplitude threshold relative to the activation of the DUT.

Abstract: A master station includes a group of circuits for performing an optimization method. In such a system, the optimization is achieved by adjusting the pull-up resistance and by setting the best possible clock frequency to ensure that data/clock high and low voltage levels are within predetermined specifications. An optimization procedure is performed in a calibration phase invoked by a user or a system whenever a change is introduced to the system, such as addition or deletion of slave stations, a change of data/clock lines, or a change that may affect on the electrical and timing characteristics of the two-wire communication system.

Abstract: There is provided a detection apparatus including a transition point detecting unit operable to receive the output signal to detect the point of transition, a timing comparing unit operable to detect the signal level of the output signal in front of or behind the point of transition in the output signal, and a correction unit operable to compensate the timing of the point of transition detected from the transition point detecting unit based on the signal level of the output signal detected from the timing comparing unit.

Abstract: In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch.

Abstract: A computer-implemented method, for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.

Abstract: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.

Abstract: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.

Abstract: A system that generates an electromagnetic interference (EMI) fingerprint for a computer system is presented. During operation, the system executes a load script on the computer system, wherein the load script includes a specified sequence of operations. Next, the system receives EMI signals generated by the computer system while executing the load script. The system then generates the EMI fingerprint from the received EMI signals.

Abstract: A signal monitor device that detects a signal propagating on a signal line and that generates a timestamp when the signal is detected. The timestamp may be used in a variety of applications including measuring the propagation delays on signal lines and determining the timing in a system.

Abstract: Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a transmitting device. Timing for one or more data signals may be adjusted in relation to a clock signal according, at least in part, to the test value returned from a receiving device.

Abstract: A time correcting apparatus includes a data input section which inputs all event trace data generated for each event executed on computing devices and outputs the event trace data in order of occurrence time of the event data. An inter-machine communication-time-table generating section extracts transmission and reception events from the output event trace data and generates a communication time table indicating communication times between computing devices based on the differences in occurrence time between the corresponding transmission and reception events. A time-offset deriving section generates a time offset table indicating a time offset value for each computing device based on the communication time table. A time correcting section corrects the event occurrence times of all event data based on the time offset table. A data integrating section inputs all event data whose occurrence times have been corrected and outputs the event data in order of corrected occurrence time.

Abstract: In a time correcting apparatus, a signal including time codes is sampled to generate a bit sequence of input TCO data. A prognostic TCO data generating unit 33 generates a bit sequence of prognostic TCO data based on a current time calculated by a time calculating circuit 17. An error number calculating unit 34 compares bits of the input TCO data with bits of the prognostic TCO data to count the number of discrepancy, thereby calculating the number of errors, and shifts bits of the prognostic TCO data to generate new TCO data and compares bits of the new TCO data with bits of the input TCO data to calculate the number of errors. A judging unit 35 judges if the number of errors is valid. When the number of errors is valid, a time correcting unit 36 calculates a time difference of the calculated current time based on the number of shifting bits, as much as which number of shifting bits the prognostic TCO data has been shifted to calculate such valid number of errors.