Abstract: Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second operating frequency. The first operating frequency is higher than the second operating frequency, and is not an integral multiple of the second operating frequency. In the test method, a third operating frequency of a third clock signal is generated according to the second clock signal, in which the third operating frequency is higher than the first operating frequency and is an integral multiple of the second operating frequency. The first clock signal is replaced by the third clock signal and the first logic portion is tested by the third clock signal. The second logic portion is tested by the second clock signal.

Abstract: A periodic signal is driven onto a transmission line, and the frequency of the periodic signal is varied from an initial frequency that corresponds to a quarter wave or half wave of an estimated length of the transmission line. A null or a peak in the envelope of the voltage or current wave induced on the transmission line by the periodic signal is detected at or near the end of the transmission line onto which the signal is driven. The frequency of the periodic signal that caused the null or peak may be used to calculated the length of the transmission line or a propagation delay through the transmission line. A plurality of transmission lines may be deskewed by determining the propagation delay through each transmission line and adjusting a variable delay in each transmission line so that the transmissions lines approximately equal overall propagation delays.

Abstract: Methods and apparatuses for calibrating out static timing offsets across multiple outputs of a transmitting device are provided. In accordance with at least one embodiment, a signal is selected as the master reference signal, and a closed-loop feedback system is provided to align one or more outputs of the transmitting device to a master reference signal. The master reference signal can be one of the signals being output by the transmitting device, an internal signal that is representative of the desired placement of the edges, or an external signal received by the transmitting device. The signal from the transmitting device is received by a receiver, and a calibration control block is used to generate a control signal to adjust the operation of the transmitting device.

Abstract: A method and a device for calibrating an interior clock generator installed inside a power monitoring unit of a rechargeable battery. The device includes an input pin for inputting an external clock signal from an exterior clock generator installed outside the power monitoring unit. A calibration timer control circuit is connected to the input pin. A register is connected to the calibration timer control circuit for outputting a start signal to activate the calibration timer control circuit. A counter and a timer are controlled by the calibration timer control circuit to be activated simultaneously therewith to count the outside clock signal and an internal clock signal generated from the interior clock generator, respectively. Such that the timer stops counting when the counter stops counting, a first count of the timer is compared to a second count of the counter to calibrate the interior clock generator.

Abstract: There is provided a delay amount measuring method of measuring a delay amount in an electronic device that outputs an output signal according to an input signal. The method includes a conversion step of converting the input signal and the output signal into digital data, a shift step of sequentially shifting the digital data of either of the input signal or the output signal in a time direction, an error computing step of computing a squared error of the digital data of the input signal and the digital data of the output signal with respect to each shift amount in the shift step, and a delay amount computing step of computing the shift amount when the squared error is a minimum value by means of a nonlinear least squares method and using the computed shift amount as the delay amount in the electronic device.

Abstract: A method, apparatus and computer instructions for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.

Abstract: There is provided a calibration method for a time measurement apparatus having a time-voltage converter for converting the time interval of measurement signals and clock signals to voltage, an analog-digital converter for converting this voltage to digital values, and a time interval measurement device for measuring this time interval from these digital values. The method includes a calibration signal generation step for calibrating the calibration signals for the subperiod of these clock signals, with these calibration signals having a shorter period difference than the time which corresponds to the resolution of this analog-digital converter; a frequency distribution analysis step for repeatedly measuring these calibration signals, finding this digital value, and analyzing the cumulative frequency distribution of these digital values; and a calibration determining step for determining the calibration value of these digital values such that this cumulative frequency distribution is linear.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine grain delay systhesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Abstract: A transmitter for measuring a process variable of an industrial process includes a sensor adapted to measure the process variable and to generate a sensor output. A mode selector is adapted to select between operational modes. At least one operational mode is related to an operational range of the sensor. Circuitry is adapted to compensate the sensor output according to the at least one operational mode and to generate a transmitter output representative of the measured process variable.

Abstract: System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

Abstract: A control system includes controllers that are coupled mutually by a communications network, on which information, transmitted from a master controller to a slave controller, is used to make timing corrections on the slave controller in order to synchronize event timers on the slave controller with that of the master controller. Timing accuracy for the occurrence of the event commanded by each controller is synchronized in narrow range of time, preferably within a few milliseconds depending on the specific application and system.

Abstract: A structure and related method for determining the uncertainty window associated with clock signals on a microprocessor using circuitry on the microprocessor die itself and external software. A target clock signal of interest is compared to a series of reference clock signals having the same frequency, but differing in phase relationship. Where the target clock signal makes state transitions with respect to the various reference clock signals over the course of several thousand comparisons is indicative of the uncertainty window for that target clock. By adjusting the phase relationship between the reference clock signals, and thereby adjusting the width of the time windows defined by corresponding features of the reference clock signals, the uncertainty window for the target clock signal may be iteratively determined.

Abstract: Method and apparatus to implement a “virtual” real-time clock at a terminal based on time information from multiple communication systems. At least one system (e.g., GPS) provides “absolute” time information for the virtual real-time clock, and at least one other system (e.g., a cellular system) provides “relative” time information. The virtual real-time clock is “time-stamped” with absolute time as it becomes available from the first system. Relative time (which may be received from multiple asynchronous transmitters) is mapped to the timeline of the virtual real-time clock as it is received from the second system. Absolute time at any arbitrary time instant on the timeline may then be estimated based on the absolute time from the first system and the relative time from the second system. Absolute times from the first system for two or more time instants may also be used to calibrate the relative time from the second system.

Abstract: N-sample level-crossing estimator methods and devices are provided that extract more information from given time samples than the current two-sample approach and that are more resistant to interference from noises. The two-mean level-crossing time-interval estimation method extracts more information from given time samples than existing methods, advantageously estimates a level-crossing time interval with a limited number of time samples and is quieter than current noisy estimation techniques. The two-mean level crossing time-interval estimation method for N-sample estimation uses all N time samples by calculating the mean value of the first N/2 time samples and subtracting it by the second N/2 time sample to average out the noises in time samples.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: A method for improved ATE (automatic test equipment) timing calibration at a DUT (device under test). The method includes step of accessing a DUT component using an ATE component and performing physical calibration on a first portion of signal pathways coupling the ATE component to the DUT component. A simulation based calibration is performed on a second portion of signal pathways coupling the ATE component to the DUT component. The physical calibration results are combined with simulation based calibration results to calibrate timing propagation delay between the ATE component and the DUT component.

Abstract: A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

Abstract: A method of data acquisition for a digital instrument having a bandwidth. The method includes receiving a signal and associated trigger. Using that trigger, a plurality of signal values is sampled at multiple time intervals to create an acquisition record representing a continuous fractional segment of the signal. The plurality of samples meets the Nyquist requirement for the bandwidth but is in error according to at least one known error mechanism. The acquisition record is then processed with DSP techniques to produce a compensated acquisition record corrected for the at least one known error mechanism. Each associated compensated acquisition record is incorporated into a result acquisition record as a segment thereof corresponding to a continuous fractional segment of the signal whose signal values were sampled in an associated instance. An additional signal and additional associated trigger are received. The above steps are then repeated for the additional signal and additional associated trigger.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: An integrated circuit has a circuit for adjusting the time period of an output signal. The adjustment can compensate for semiconductor processing variations varying from wafer to wafer. The circuit adjusts the delay generated by an adjustable delay line, and adjusts the occurrence in time of the trailing edge of the output signal. A value which corresponds with a suitable delay to be generated by the adjustable delay line is stored in nonvolatile storage on the integrated circuit.

Abstract: A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.

Abstract: A system and method for determining signal consistency (e.g., in a video signal processing system) are disclosed. Various aspects of the present invention may, for example, include receiving a first and second signal, each of which includes respective first and second sub-signals. A receiving module may, for example, effect such receiving. The first and second signals may be synchronized according to, at least in part, aspects of their respective first sub-signals. A signal synchronization module may, for example, effect such synchronization. Relative timing between the respective second sub-signals of the first and second synchronized signals may be determined. A timing differential module may, for example, effect such a determination. Various aspects of the present invention may generate a signal indicative of signal consistency based, at least in part, on the determination of relative timing between the respective second sub-signals. An output module may, for example, effect such a signal generation.

Abstract: A method and apparatus for establishing an average test time (TA) include determining a first time interval (TG) nominally associated with non-failing testing of a unit under test (UUT), and determining a second time interval (TPR) nominally associated with troubleshooting and repairing a failed unit under test. Additionally, a percent yield (Y) nominally associated with a proportion of non-failing units under test is determined. The average test time is a sum of the first time interval associated with the non-failing testing of the UUT, and a ratio of the second time interval associated with troubleshooting and repair of a failed UUT with respect to the yield.

Abstract: The present technology involves an apparatus and method for calibrating a plurality of distinct signal paths connecting a device under test (DUT) to a time measurement device. The disclosed calibration circuit, which may be connected to the test setup throughout the testing process, measures the signal skew associated with each distinct signal path connecting a DUT, such as an integrated circuit, to a time measurement device, such as a time interval analyzer. The measured skew values, which may be collected throughout the testing process, are stored in memory. Such memory may be within the time measure device, an external storage device or a computing device that may be in communication with the time measurement device. The time measurement device uses the stored skew values to adjust the test signals to compensate for signal path related signal skew. In addition, the stored skew values are used to perform signal path diagnostics.

Abstract: A method and apparatus for converting skew in a received signal to a low frequency voltage. A signal is received at a destination node from an original signal from a source node. A unity time-voltage sawtooth ramp signal is created at the destination node. The amplitude of the unity time-voltage sawtooth ramp signal is a value in voltage proportional to a pulse width value of the original signal. The unity time-voltage sawtooth ramp signal starts just before the start of the received signal. A skew time is measured from the start of the unity time-voltage sawtooth ramp signal to a threshold level on an edge of the received signal. The measured skew time is correlated to a voltage level on the unity time-voltage sawtooth ramp. The measured skew time for each edge is converted into a pulse where the voltage level of each pulse being proportional to the measured skew.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element.

Abstract: Among multiple surveillance devices for mechanical security monitoring provided in a security system using sensors at least one of the multiple surveillance devices is equipped with a receiver for receiving standard time data and the standard time data received by the receiver is sent over a distribution line to required surveillance devices not equipped with receivers. This enables highly accurate time calibration among the multiple surveillance devices for mechanical security monitoring to be efficiently achieved using a power-line carrier (PLC) technology and, as such, allows sharing of accurate time data among the surveillance devices.

Abstract: A system and method for controlling a controlled parameter that affects a target parameter of a target zone is disclosed. The method comprises providing a feedback control loop having a switching controller, a controlled device, and an averaging device. The controlled device comprises a time constant and a specified operational characteristic. The controlled device comprises a first operational state and a second operational state. The method further comprises calculating a time constant for the averaging device based at least on the time constant for the controlled device, and the specified operational characteristic. The specified operational characteristic may comprises a minimum amount of time that the controlled device operates before it can be switched between the first operational state and the second operational state.

Abstract: A method of optimizing the timing between signals to be latched and a respective latching clock signal is suggested wherein test timings are provided according to which a delay test value of a clock delay line (CDL) are generated. According to the delay test values a clock signal (C) and a sample signal (S) are received through said clock delay line (CDL) and through said sample signal line (SSL), respectively. Respective phase differences for the distinct delay test values are obtained. A delay value is chosen and set for operation for which the respective obtained phase difference fits best to given target timing data.

Abstract: A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.

Abstract: Optical scanner system approaches are described in which signal saturation data is produced in real-time. The data generated may be used for tuning a subsequent scan, in protection of optical detector components from damage or otherwise. Approaches for obtaining and storing or expressing the data are also disclosed. Also provided are methods of using the subject system is biopolymer array based application, including genomic and proteomic applications.

Abstract: An inspection system for an article of manufacture and method of using the same, assists an inspector in the inspection of a wide variety of articles for conformance to a pre-selected set of requirements particularly when checking is done by human senses and the manual application of measuring devices. A computer server is utilized in conjunction with the inspector to impose constraints and discipline on the inspector's actions. Such constraints include enforcing a standardized sequence for checking each of a pre-selected set of article requirements depending on the fabric article type, limiting the available responses by which the inspector can record the results of the observation, and enforcing a minimum lapsed time for inspection of certain article requirements.

Abstract: The invention relates to a device and a method for determining an electrical starting rotor angle of an electromotor. According to the invention, the electromotor (10) is subjected to an approximately sinusoidal voltage and the corresponding current path (i) that is established is then detected. The electromotor (10) is again subjected to an approximately sinusoidal voltage and again, the corresponding current path (i) is detected. A ratio of a measure of the fundamental wave (I1) and the measure of the first harmonic wave (I2) is then determined from the current paths (i) as a measure of the electrical starting rotor angle (?).

Abstract: A method of calculating an aerial image of a spatial light modulator array includes calculating a pixel interference matrix that represents pair wise interference between pixels of the spatial light modulator array; calculating effective graytones corresponding to modulation states of the pixels; and calculating the aerial image based on the pixel interference matrix and the effective graytones. The graytones depend only on the modulation states of the pixels. The pixel interference matrix depends only on position variables. The position variables are position in an image plane and position in a plane of a source of electromagnetic radiation. The pixel interference matrix can be a matrix of functions. The pixel interference matrix can be a four dimensional matrix. The effective graytones are approximated using sinc functions, or using polynomial functions.

Abstract: A method and related ultrasonic meter identify and correct for transit time errors such as peak switch errors. The method includes calculating values for a set of diagnostics from measurements of the fluid flow, including transit time measurements. Based on the values for the diagnostics, and whether and how they fall outside of their respective ranges, the meter can identify a variety of problems with the meter or fluid flow, such as whether there has been an intermittent peak switch, a permanent peak switch, or the presence of noise, velocity pulsation in the fluid flow, temperature stratification, of other problem. In the event there is a problem with the meter, the meter self-tunes in order to minimize the chances of the problem happening again.

Abstract: Disclosed herein is an improved method and apparatus for simultaneously performing tests on several devices at the same time. An aspect of one embodiment of the invention is an improved DMA controller that automatically selects certain pin groups, which are connected to a common data bus, to receive test data words from a common data bus. By selecting more than one pin group at the same time, test data (such as a test data word) can be simultaneously loaded onto multiple pin cards at the same time. By loading this data into multiple pin cards at the same time, test data can be “fanned-out” to multiple pin cards and thereby be sent to multiple device sites at the same time. Another aspect of one embodiment of the invention utilizes DMA-based hardware to select which pin groups should received “fanned-out” test data. By utilizing DMA-based hardware to fan-out the test data, the software-based test programs and patterns may be created to manipulate a single device.

Abstract: A circuit configuration has a calibration circuit, which is connected to terminals for two digital signals and has outputs for two digital output signals which are each derived from one of the digital signals. The calibration circuit effects temporal control of a switching edge of one of the output signals using a control value. A comparison circuit generates a comparison signal which indicates that one of the output signals has a switching edge first relative to the other output signal. The calibration circuit has a control input, through which the control value, which is stored in a storage circuit, can be set using the state of the comparison signal of the comparison circuit. The circuit configuration makes it possible to compensate undesirable propagation time differences between the digital signals.

Abstract: A method synchronizes signals from unsynchronized sensors spatially dispersed in an environment. Each sensor acquires an unsynchronized signal from the environment. An identical timing signal is received in each sensor. Frequencies of the timing signal are substantially disjoint of frequencies of the unsynchronized signals. The timing signal is combined with the unsynchronized signal in each sensor. The combined signals are received by a signal processor where the combined signals are separated to recover the unsynchronized signals and the timing signals. Then, the unsynchronized signals can be time-aligned according to the recovered timing signals to produce time-aligned signals.

Abstract: A system for calibrating cables attached to a time measurement device is disclosed. The system includes a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. The calibration device can also generate at least one arming signal that is also communicated to the time measurement device. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the system of the present invention can also be used to determine the arming latency of the time measurement device by delaying the measurement signals in relation to the arming signals and observing the delay time which causes complete synchronization of the measurement signals.

Abstract: A chip includes CPU (12), memories (13,14) for programs and data, peripheral units (18,19) for interacting with the outside world, and an internal RC oscillator (17) for providing clock signals. One of the peripheral units (18) includes a timer counter incremented at a frequency derived from the RC oscillator. The method does not try to change the frequency of the RC oscillator. Instead, an external calibration source (21) is connected to a capture input of the timer unit to provide a signal having a reference frequency, e.g. the mains frequency. The counter is sampled on active edges of that signal, and the sampled values are processed to derive a calibration ratio. After these calibration steps, a software correction is applied to parameters handled by programs stored in memory based on the calibration ratio to compensate for frequency variations of the RC oscillator.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: A data manipulation method to make local chromatography data more usable and comparable to a reference. The method provides time axis correction to better match local data to a reference of the same time scale, time axis transformation to correspond more directly to a reference based on a different time scale, and response axis correction to better match a reference of the same or different response scale, while maintaining the original peak areas. The method may be used along or concurrently with other data manipulation technique to facilitate operations such as searching, matching, visual comparison, mathematical manipulation, and pattern recognition of chromatographic data.

Abstract: A method and apparatus for real-time derivation of precise digital clock edges and synchronous logic samples from a digital signal having a clock channel and at least one data channel acquires a plurality of temporally offset analog samples during each of a sequence of sample periods and from consecutive samples where there is a logic level transition estimates an edge time. From the edge times for the clock channel an offset is added and applied to the at least one data channel to determine the synchronous logic samples for the data channel at each offset clock edge time.

Abstract: An electronic plumbing device, such as a faucet, has a microprocessor that is programmed to periodically purge stagnant water remaining in the faucet at predetermined time intervals. The microprocessor energizes a solenoid associated with a water valve to initiate the flow of water through the faucet in response to a detector sensing the presence of a user near the faucet. A first timer is programmed into the microprocessor and controls the minimum run time of the faucet for activations initiated by either a user or by the purge feature. A second timer is also programmed into the microprocessor to measure a second predetermined time interval. If the faucet is not used during the second predetermined time interval, the microprocessor will energize the solenoid for the minimum run time to open the water valve and flush out any stagnant water remaining in the faucet from the prior activation.

Abstract: A real-time data acquisition and storage network for real-time acquisition and storage of analog and digital data from one or multiple network-connected data sources to one or multiple network-connected storage devices during a data recording session, and precise reconstruction of the acquired data from one or multiple of the network-connected storage devices during a playback session. The data source are connected to the network through one or multiple real-time data acquisition network (“R-T DAN”) modules which form one or multiple network-connected data acquisition nodes on the network. Each storage device forms a network-connected storage node on the network so that data acquired at any data acquisition node may be applied to the network and stored at any storage node during a data recording session. The stored data may be retrieved from the storage nodes through the network and routed to the data acquisition nodes for reconstruction of the data during a playback session.

Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

Abstract: The present invention provides a system and method for analyzing hardware alarms in a telecommunications digital cross-connect system. The present invention also relates to a system and method for automating the process of analyzing hardware failures that cause path and parity alarms in a telecommunications digital cross-connect system used in a long distance network.

Abstract: A power monitor circuit and method delays the start of a computer until multiple power lines are at a safe level of operation. The integrated circuit monitors only the voltage of a primary power supply output and eliminates the need for monitor circuits on each supply output. The power supply is made to exacting specifications that tie the 5 volt and 3.3 volt supplies to the primary 12 volt supply. The ATX power supply drives the 3.3 and 5.0 supplies to reach 90% of their values within 40 ms after the 12 volt supply reaches 90% of its value. A time delay circuit 25 delays switching the 3.3 and 5 volt dual outputs from the standby voltage supply to the active voltage supplies until after the primary 3.3 and 5 volt are at a safe operating level.

Abstract: A method for calibrating cables attached to a time measurement device is disclosed. Such a method may utilize a system including a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the method can also be used to determine the arming latency of the time measurement device and by delaying the measurement signals in relation to the arming signals and observing the delay which causes complete synchronization of the measurement signals.