Abstract: A timing control device and method for minimizing timing uncertainties due to skew and jitter, wherein a device for the compensation of timing errors in multiple channel electronic devices comprises at least one register having a plurality of channels comprising: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers. For each register, a corresponding feedback loop is associated for the relative alignment of the register's timing. The feedback loop comprises a device for detecting a deviation from a predetermined level of probability of reading by the register of a desired symbol on a boundary of two reference channel symbols in a sequence, and a set of delay devices which use the detected values of probability to generate a feedback signal.

Abstract: A method and apparatus for controlling fraction collection in an eluent stream flowing from an LC column. A triggering detector recognizes the presence of a target substance according to characteristics of chromatographic peaks in the eluent stream and initiates a delay timer to trigger the fraction collector. A waste stream detector is disposed at any distance from the fraction collector to detect peaks in the waste stream flowing from a fraction collector. The signature of fraction collector actuation is seen by the waste stream detector, permitting the delay time to be adjusted for optimal collection of the target compound. The presence or absence of a peak or the characteristics of a remnant peak detected by the waste stream detector are used to confirm that the target component of the eluent stream was collected as intended by the fraction collector.

Abstract: The operation of a fossil-fired thermal system is quantified by recognizing and correcting data collections which must be synchronized to improve the accuracy of analytical models which determine fuel chemistry, fuel heating value, boiler efficiency, fuel energy flow and/or system heat rate.

Abstract: A number of embodiments of memory devices and methods of performing read/write timing calibration of these memory devices using a row or a redundant row. Addressing of the row or redundant row in a memory array of a memory device may be accomplished by using a calibration fuse bank to address a row or a redundant row of the memory array, by using a fuse bank of the memory device to address a redundant row of the memory array, or by storing the row address of a row in a memory controller and providing the row address to the memory device during calibration. A redundant row used for calibration may be a redundant row not utilized by a memory device during repair of its memory array. A row used for calibration may be a row not utilized by a memory device due to the nature of the specific application in which that memory device is being used. A unique data pattern may then be written to and read from the addressed row or redundant row for read/write timing calibration.

Abstract: A method for calibrating cables attached to a time measurement device is disclosed. Such a method may utilize a system including a calibration device that generates a plurality of synchronized measurement signals that are communicated to a time measurement device by a set of cables. By determining the relative arrival time of a common reference event of each of the measurement signals, the time measurement device can determine any skew that exists between each of the cables that input the measurement signals. The skew can then be used to compensate for varying cable skew in future time measurements. In one embodiment, the method can also be used to determine the arming latency of the time measurement device and by delaying the measurement signals in relation to the arming signals and observing the delay which causes complete synchronization of the measurement signals.

Abstract: The objective of the present invention is to achieve a measured data synchronizing system and a measured data synchronizing method which can determine the measured data whose synchronization is secured among measuring units without being restricted by the number of measuring units in the measuring part. The present invention is characterized by preparing a communication line, a plurality of measuring units which receive a reference time from the above communication line as an input and output tuple data in which at least the above reference time and the measured data are contained and arranged as a tuple, and a data processing unit which outputs the reference time to the above communication line, receives tuple-data from each of the above plurality of measuring units as inputs and secures synchronization of the measured data among the measuring units based on the reference time of the tuple-data.

Abstract: To adapt the timing advance of a mobile terminal during synchronous handover from a first to a second base station of a radio communications system, a time delay between time standard received by the terminal from the two base stations is measured. A timing advance value that is used by the terminal prior to handover for transmission to the first base station is corrected using the measured time delay. The corrected timing advance value is reduced by a value derived from the accuracy of the synchronicity of the two base station and is used as the timing advance value for transmission to the second base station.

Abstract: A data manipulation method to make local chromatography data more usable and comparable to a reference. The method provides time axis correction to better match local data to a reference of the same time scale, time axis transformation to correspond more directly to a reference based on a different time scale, and response axis correction to better match a reference of the same or different response scale, while maintaining the original peak areas. The method may be used along or concurrently with other data manipulation technique to facilitate operations such as searching, matching, visual comparison, mathematical manipulation, and pattern recognition of chromatographic data.

Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Abstract: A continuous automatic calibration system and apparatus using a delta-sigma modulation technique. A first time duration is set. The first time duration is a length of time in terms of clock counts for a calibration procedure. Then, a second time duration occurring during the first time duration is measured. The second time duration is a length of time in terms of clock counts that a counter is operational. A multiplying factor is determined by dividing the first time duration by the second time duration.

Abstract: The invention relates to a method and arrangement for improving the accuracy of time measurements related to positioning in a radio system. In the method, a test signal is generated; the test signal is directed to travel through pre-selected radio frequency parts of a receiver used in positioning in the radio system; the propagation delay of the test signal through the pre-selected radio frequency parts is determined; and the determined propagation delay is used to improve the accuracy of time measurement related to positioning.

Abstract: The utilization of a central processing unit during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the central processing unit. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval.

Abstract: In order to test, in parallel, semiconductor chips formed on a wafer, functionally identical contact points of the semiconductor chips are connected to column lines, and the rows of the semiconductor chips are selected by selection signal lines. This method is suitable in particular for checking electrically conductive connections between contact points of the semiconductor chips and mating contacts of a test head.

Abstract: A data manipulation method to make local chromatography data more usable and comparable to a reference. The method provides time axis correction to better match local data to a reference of the same time scale, time axis transformation to correspond more directly to a reference based on a different time scale, and response axis correction to better match a reference of the same or different response scale, while maintaining the original peak areas. The method may be used along or concurrently with other data manipulation technique to facilitate operations such as searching, matching, visual comparison, mathematical manipulation, and pattern recognition of chromatographic data.

Abstract: In its most general terms the invention compensates for the effect of the mass offset in the prior art calibration method. This can be achieved either by correcting for the offset or assigning mass to the peaks in such a way that the offset is avoided. Accordingly in a first aspect there is provided a method of calibrating a reflectron time-of-flight mass spectrometer using a spectrum generated by fragment ions wherein a measured mass value is modified to take account of the effect of post source decay and that modified value is used for calibration. A modified calibration function can then be defined and used to determine actual fragment ion masses of an unknown compound.

Abstract: An apparatus and method for deskewing single-ended signals from different driver circuits of an automatic test system provides enough of a reduction in skew to allow differential signals to cross at or near their 50%-points. In accordance with this technique, first and second driver circuits are respectively coupled to first and second inputs of a measurement circuit through pathways having known and preferably equal propagation delays. The first and second driver circuits each generate an edge that propagates toward the DUT, and reflects back when it reaches a respective unmatched load at the location of the DUT. In response to the edge and its reflection, the first and second inputs of the measurement circuit each see a first voltage step and a second voltage step. The interval between the first and second voltage steps is then measured for each input of the measurement circuit.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: Generating and using calibration information includes using a test circuit to generate calibration information that is representative of how changes in at least one variable affect operation of a first element of a controlled circuit and using the calibration information to provide control signals to the first element and to at least one other element of the controlled circuit to adjust operation of the first element and the other element to accommodate changes in the variable.

Abstract: Step 2 demodulation is conventionally performed using a secondary synchronization channel that correlates a received signal at a known time slot location against each of a plurality of sequences associated with the secondary synchronization code. The disclosed implementation proposes the use of a different synchronization channel to complete the step 2 process. More specifically, a complete synchronization channel correlator is used for the demodulation where the received signal at the known time slot location is correlated against a combination of the primary synchronization code and each of the plurality of secondary synchronization codes. This combined correlation produces enhanced step 2 performance in terms of acquisition time or signal-to-noise ratio.

Abstract: An analog signal is digitized by an analog-to-digital (A/D) converter clocked by a periodically jittery clock signal. Elements of the digital data sequence (vector) output of the A/D converter are sorted into a set of smaller vectors according to clock signal jitter phase and each of the smaller vectors is then separately subjected to Fourier transform and time shift functions. The resulting vectors are then processed to produce an output vector representing the frequency spectrum of the analog signal.

Abstract: A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

Abstract: A frequency detector includes a slicer to receive and slice a phase error against a compare threshold value. The slicer generates a symbol based on the phase error sliced against the compare threshold value. A symbol counter is provided to increment a symbol count if the symbol generated is the same as a last symbol. A logic circuit compares the symbol count with a symbol count limit if the symbol is different from the last symbol. The logic circuit increments a high counter and clears a low counter if the symbol count is less than the symbol count limit. The logic circuit increments the low counter and clears the high counter if the symbol count is greater than the symbol count limit. A combinational logic circuit is provided to generate a high frequency jitter true signal or a high frequency jitter false signal based on at least one of the symbol count, the high counter, and the low counter.

Abstract: The circuit arrangement serves to identify an input signal (s1) assigned to a predetermined signal class. It comprises signal-matching electronics (1) responsive to a current component and/or a voltage component of the input signal (s1) and providing a corresponding output signal (s2). By means of signal recognition electronics (2) of the circuit arrangement, the output signal (s2) is transformed into a recognition signal (c1) representative of the signal class.

Abstract: An arrangement for adaptive time keeping in a utility meter includes a timing circuit and a controller. The timing circuit is operable to generate timing signals. The controller is operably coupled to the timing circuit to receive timing signals therefrom. Further, the controller is operable to: generate a first real-time value based at least in part on an externally generated first reference time value; derive a subsequent second real-time value, based at least in part on the first real-time value, the timing signals, and a timing circuit calibration value; obtain an externally generated second reference time value; determine a rate adjustment based at least in part on a difference between the second real-time value and the second reference time value; and generate a subsequent real-time value based at least in part on the timing signals, the timing circuit calibration value, and the rate adjustment.

Abstract: A system and method for regulating an adjustable DC supply and continuously and remotely monitoring measurements of reference cell potential and/or current for cathodic protection of a structure is disclosed. Cathodic protection devices use a logic circuit and/or microprocessor based monitor for removing identifiable components and noise from the system to arrive at the DC bias. A method is implemented herein to arrive at the true value of a reference cell potential measurement determined within a sample collection point or window calculated for the reference cell signal while the impressed current is still being applied. This measurement can be compared to a calculated shutdown and is communicated to a central computer accessible via a network such as the Internet. All output is automatically regulated and checked for target window accuracy using an automated voting scheme.

Abstract: A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes channels linked by paths through an interconnect system to pads of the IC. During a test each channel may send a test signal edge to an IC pad following a clock signal edge with a delay including “programmable drive” delay and “drive calibration” delay components, or may sample an IC output signal following the clock signal edge with a delay including “programmable compare” delay and adjustable “compare calibration” delay components. The interconnect system also links a spare channel to a point on the IC. To adjust the compare calibration delay of each channel, the interconnect system sequentially connects the tester channels to interconnect areas on a “calibration” wafer instead of to the IC on the wafer to be tested. Each interconnect area provides a path linking a channel to be calibrated to the spare channel.

Abstract: The objective of the present invention is to achieve a measured data synchronizing system and a measured data synchronizing method which can determine the measured data whose synchronization is secured among measuring units without being restricted by the number of measuring units in the measuring part.

Abstract: A timing correcting method for correcting the timings of an IC tester at low cost, wherein the method uses a probe (300) for taking out a signal fed to a pin out of the pins of an IC socket (203) to which an IC to be measured is plugged when the probe is brought into contact with the pin and supplying a correcting pulse to the pin, and the timing of the correcting pulse taken in by a reference comparator (CP-RF) provided in the probe and the timing of a reference correcting pulse applied to an IC socket from a reference driver (DR-RF) provided in the probe are measured by a timing measuring function that the IC tester has, thus performing timing correction.

Abstract: A timing calibration system for an adjustable delay time of a delay module for an electronic circuit is provided. The system includes a control delay module including at least one calibration delay module, the control delay module having a second delay time. The system also includes a timing module associated with the control delay module, a comparison module associated with the timing module and an adjustment module for the delay module. The timing module measures the second delay time, the comparison module compares the second delay time with a desired delay time and produces a comparison result and the adjustment module calibrates the adjustable delay time utilizing the comparison result.

Abstract: A data manipulation method to make local chromatography data more usable and comparable to a reference. The method provides time axis correction to better match local data to a reference of the same time scale, time axis transformation to correspond more directly to a reference based on a different time scale, and response axis correction to better match a reference of the same or different response scale, while maintaining the original peak areas. The method may be used along or concurrently with other data manipulation technique to facilitate operations such as searching, matching, visual comparison, mathematical manipulation, and pattern recognition of chromatographic data.

Abstract: In a recording and reproducing apparatus, and in a time calibration method of the recording and reproducing apparatus, first and second clock units are provided for counting time. A time extraction unit extracts time information included in a received broadcast signal. Also included in the recording and reproducing apparatus is a time setting unit for manually setting the time of the first clock unit. From the extracted time information, the time of the second clock unit is calibrated. And if the time information is extracted within a specific interval, manual time setting of the time setting unit is prohibited, and the time of the first clock unit is calibrated by the time of the second clock unit. But if the time information is not extracted within the specific interval, manual time setting by the time setting unit is allowed, and the time of the second clock unit is calibrated by the time of the first clock unit.

Abstract: A testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer, and can measure high-speed operation timing in a high precision.

Abstract: Among multiple surveillance devices for mechanical security monitoring provided in a security system using sensors at least one of the multiple surveillance devices is equipped with a receiver for receiving standard time data and the standard time data received by the receiver is sent over a distribution line to required surveillance devices not equipped with receivers. This enables highly accurate time calibration among the multiple surveillance devices for mechanical security monitoring to be efficiently achieved using a power-line carrier (PLC) technology and, as such, allows sharing of accurate time data among the surveillance devices.

Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, TA3, - - - and the measured values T1, T2, T3, - - - become a constant value TC.

Abstract: A virtual device driver for processing serial communications in a protected operating system. The virtual device driver adds a time-stamp to each character received at Ring-zero level of the operating system architecture. The time-stamp value is compared to a predetermined maximum acceptable time interval to determine if a valid packet was received.

Abstract: A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

Abstract: A method for time reference compensation in a power metering system, the method comprising monitoring a time-dependent characteristic of incoming AC power over a predetermined local time interval, comparing the monitored characteristic over the predetermined local time interval with the expected value of the characteristic based upon the nominal frequency of the AC power, and calculating a correction to one or more of local real-time and time-based measurements of the power metering system, based on the comparing.

Abstract: A method of calibrating a timebase in a digitizing instrument estimates the frequency of the clock signal from the clock generator that clocks a coarse delay counter in a strobe generator. The dynamic range of the interpolator in the strobe generator is defined in digital-to-analog converter code values as a function of the clock signal period. A linear horizontal look-up table of equally spaced digital-to-analog converter code values is generated over the defined dynamic range of the interpolator. Residual nonlinearities of the interpolator over the defined dynamic range of the interpolator are characterized and scaled to digital-to-analog converter code values. The digital-to-analog converter code values of the characterized residual anomalies are combined with the digital-to-analog converter code values of the linear horizontal look-up table to generate a horizontal look-up table having DAC code value compensating for the nonlinearities of the interpolator.

Abstract: Apparatus and methods for measuring the amount by which the centerline of a shaft disposed in a vessel is offset from the central vertical axis of the vessel, and for measuring the height of such shaft above the inside bottom of the vessel. Apparatus includes a shaft centerline offset measurement device, a shaft height measurement device, and a control/display console. Each measurement device includes a transducer or optical encoder for sensing a displaced position of a biased plunger to which a code strip is mounted. The devices may be combined into a single shaft offset and height measurement device. Improved methods include calculating shaft offset based on a plurality of readings from the transducer, and applying trigonometric relationships. The apparatus and methods are particularly useful in the verification of paddle or basket shafts utilized in dissolution testing stations, so that the dissolution testing protocol complies with government agency guidelines.

Abstract: A method and a system to synchronize a time of day clock of a clock system. The method and system include a portable satellite timing system at a first location receiving a satellite signal comprising a first time of day signal. An internal clock of the portable satellite timing system is calibrated based on the first time of day signal to generate a second time of day signal. The portable satellite timing system is transported to a second location and coupled to the clock system. The second time of day signal is transferred from the portable satellite timing system to the clock system and the time of day clock is synchronized based on the second time of day signal. After a time period, the portable satellite timing system is transported to the first location.

Abstract: A system and method are provided for detecting a stable region in a data signal to facilitate the alignment between a data signal and a corresponding clock signal. The system includes a processor coupled to a local interface and a memory coupled to the local interface. The system also includes a boundary detection circuit configured to perform a simultaneous sampling of a reference signal and a delayed reference signal to ascertain a degree of stability of a position in the reference signal. The reference signal is the signal received from the target system and the delayed reference signal is a delayed copy of the reference signal. The system also includes boundary detection logic stored on the memory and executed by the processor to control the operation of the boundary detection circuit. The boundary detection logic includes logic to detect a boundary of the stable region of the reference.

Abstract: A magnetically sensitive sensor for counting pulses for measuring rotational speeds and angular positions of a rotating component via a pulse transmitter connected for rotating with the rotating component automatically adapts its switching points to the respective measurement location conditions. A logic unit initiates automatic adaptation of the switching points from an original state when an operating parameter first exceeds a limit value after the supply voltage of the sensor turned on. The original state is not preset or is coarsely preset. The configuration of the switching points is then stored in a non-volatile data memory specifically for the sensor.

Abstract: A detection device for an apparatus for carrying out analysis such as a chromatograph includes not only a detector for outputting detection signals but also a stabilization judging unit for measuring drift and noise of these detection signals over time and automatically transmitting a start signal which permits the apparatus for analysis to start its operations when the measured drift becomes smaller than a standard drift value such as one-tenth of the optical absorbance measured for a spectrum of an analyzed sample at the detection wavelength. A standard noise value setting unit may be further provided for receiving detection signals at detection wavelength while a standard sample is placed inside a detection cell, calculating a standard noise value on the basis of intensity of the detection signals, and transmitting the calculated standard noise value to the stabilization judging unit.

Abstract: In an electromagnetic operating system having a coil for electromagnetically controlling a mechanical operating member for operating the processing of objects in response to an alteration in an electrical voltage condition, the control system is arranged for generating test command pulses of different magnitude, for registering a command code in accordance with a smallest magnitude test command pulse causing the operating member to move, and for subsequently correcting alterations in the voltage condition for controlling the operating member in accordance with the registered command code. The control system is responsive for effecting the corrections in the alterations of the voltage condition in accordance with the registered command code. This enables simple correction for differences in the response delay among different electromagnetic operating systems.

Abstract: Systems and methods for efficiently and accurately determining a speed of a faster clock having unknown frequency using a slower clock having a known frequency. A series of measurement pairs are taken from the clocks; each measurement pair including one measurement from the slower clock and one measurement—at the same time—from the faster clock. A lower bound and an upper bound for the measurement pairs are determined. The lower bound and the upper bound are averaged to derive a calibration variable that indicates a number of clock cycles that occur on the faster clock during one cycle of the slower clock. The calibration variable is used to time various processes in a computer system.

Abstract: A method of and system for determining calibration offsets to account for delays introduced “downstream” of the reference driver (24) of a tester system (18) to test electronic components such as SRAM semiconductor memory devices. Such delays are created by, among other elements, receiver channels (30) of the tester system. A plurality of calibration modules (100) are provided, one for each receiver channel. Each calibration modules has a transmission line (110) with a known delay, a first contact 102′ and a second contact 102″. The tester system includes a socket (52) having a plurality of contactors (54) for contacting the reference clock contact and data output contacts of the electronic components undergoing test. The first contact of each calibration module is positioned to engage the contactor that engages the reference clock contact of the electronic component.

Abstract: Signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels. The known values TA1, TA2, TA3, - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, - - - and the measured values T1, T2, T3, - - - become a constant value TC.

Abstract: The present invention relates to the reducing of timing uncertainties in high-performance digital circuitry. More specifically, the present invention relates to a timing control means and method for minimizing timing uncertainties due to skew and jitter. A means for the compensation of timing errors in multiple channel electronic devices comprising at least one register having a plurality of channels comprises: a clock for providing a clock signal; a reference signal generator for generating reference signals for deskewing the registers; wherein for each said register a corresponding feedback loop is associated for the relative alignment of register's timing, the feedback loop comprising a means for detecting a deviation from a predetermined level of probability of reading by said register a desired symbol on a boundary of two reference channel symbols in a sequence and a set of delay means which uses the detected values of probability to generate a feedback signal.

Abstract: An event detector method and apparatus are described. One embodiment includes a first detector that includes a plurality of zones. Each zone includes a plurality of detector devices, wherein each zone generates a zone trigger signal when an event is detected by a detector device in the zone. The embodiment further includes a first energy source coupled to the first detector, wherein when the first energy source is active, events occur that are detectable by the first detector. A calibration circuit is coupled to the first detector, to perform timing calibration of zone trigger signals of zones of the first detector with respect to timing of a reference zone trigger signal of the predetermined reference zone of the first detector, wherein the zone trigger signals and the reference zone trigger signal are generated when an event is detected.

Abstract: Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I−&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value.