Event-driven Patents (Class 703/17)
  • Patent number: 10241960
    Abstract: Described are methods, systems and computer readable media for simulated replay of data using a computer system.
    Type: Grant
    Filed: May 14, 2016
    Date of Patent: March 26, 2019
    Assignee: Deephaven Data Labs LLC
    Inventors: David R. Kent, IV, Ryan Caudy, Charles Wright, Oleg Vydrov, Radu Teodorescu
  • Patent number: 10241811
    Abstract: A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: March 26, 2019
    Assignee: Significs and Elements, LLC
    Inventors: Muthu M. Baskaran, Benoit J. Meister, Benoit Pradelle
  • Patent number: 10242315
    Abstract: Techniques for representing a finite state machine forming are described herein. The techniques include a method that identifies screens of a computing program. The method may include correlating the identified screens with states of a finite state machine. Events indicating transition between the identified screens may be determined as well as data flow associated with the events. The method may include forming a graph representing the screens, events, and data flow in the finite state machine.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Aharon Abadi, Moria Abadi, Idan Ben-Harrush
  • Patent number: 10175956
    Abstract: A solution providing for the dynamic design, use, and modification of models using a declarative software application meta-model that provides for self-modification of a collection of the models is provided. The solution can enable continuous real-time testing, simulation, deployment, and modification of the collection of the models. A model in the collection of the models can represent an entity or a function and can be included in a set of related models. Additionally, a set of related models can include a plurality of sets of related models. The collection of the models can represent, for example, one or more software applications, processes, and/or the like.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 8, 2019
    Assignee: EnterpriseWeb LLC
    Inventors: Dave M. Duggal, William J. Malyk
  • Patent number: 10169518
    Abstract: An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit design computing equipment may perform register moves within the circuit design, whereby registers are moved across one or more portions of the combinational logic. When moving the registers, counter values may be maintained for a group of non-justifiable elements within the combinational logic, across which the registers may move. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that may be used to generate an adjustment sequence. The adjustment sequence may be prepended to the original reset sequence to generate an adjusted reset sequence that properly resets registers within the integrated circuit after registers moves.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventor: Mahesh A. Iyer
  • Patent number: 10116623
    Abstract: Token-based firewall functionality. A request is received for access to a resource from a remote user device, the request received by an application firewall. A token is associated with the request. The token and associated information are stored in an event correlator coupled with the application firewall. The token is associated with one or more subsequent actions by the resource in response to receiving the request. A response to the request including the token is generated. The response with the token is transmitted to the remote user device via the application firewall. The application firewall analyzes the response and determines an action to be taken on the response based on the token and the associated information.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: October 30, 2018
    Assignee: salesforce.com, inc.
    Inventor: Yoel Gluck
  • Patent number: 10108761
    Abstract: A method of executing a simulation model while generating an associated structural model includes changing, by a computer-aided design (CAD) system, the structural model. The method further includes evaluating, by the CAD system, at least one trigger criterion to determine if the change to the structural model is a simulation trigger event. The method also includes executing, by the CAD system, the simulation model if the change to the structural model is determined to be the simulation trigger event.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: October 23, 2018
    Assignee: DASSAULT SYSTEMES SOLIDWORKS CORPORATION
    Inventors: Jonathan Wiening, Marlon Banta, Stephen Endersby
  • Patent number: 10032111
    Abstract: A system includes a machine learning engine. The machine learning engine is configured to receive training data including a plurality of first input conditions and a plurality of first response maneuvers associated with the first input conditions. The machine learning engine is configured to train a learning system using the training data to generate a second response maneuver based on a second input condition.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 24, 2018
    Assignee: ROCKWELL COLLINS, INC.
    Inventors: Joshua R. Bertram, Angus L. McLean
  • Patent number: 9996373
    Abstract: An approach for avoiding overloads of network adapters. The approach receives one or more requests from one or more virtual machines, wherein the one or more requests are directed to one or more network adapters. The approach determines whether a first network adapter of the one or more network adapters is saturated. Responsive to a determination that the first network adapter is saturated, the approach sends a first busy event to a first virtual machine of the one or more virtual machines.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kiran K. Anumalasetty, Venkata N. S. Anumula, Vinod Kumar Boddukuri, Sanket Rathi, Rajaboina Yadagiri
  • Patent number: 9954579
    Abstract: “Smart” connectors with embedded processors, measurement circuits and control circuits are disclosed for establishing a “contactless” radio frequency (RF) electromagnetic (EM) Extremely High Frequency (EHF) communications link between two electronic devices having host systems. The connectors are capable of monitoring, controlling, and directing (managing) link operation to dynamically adapt to conditions, as well as monitoring and altering (or modifying) data passing through the connector, and selecting a protocol suitable for a communications session. The connectors are capable of identifying the type of content being transferred, providing authentication and security services, and enabling application support for the host systems based on the type of connection or the type of content. The connectors may operate independently of the host systems, and may perform at least one of sensing proximity of a nearby object; detecting a shape of a nearby object; and detecting vibrations.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 24, 2018
    Assignee: KEYSSA, INC.
    Inventors: Gary D. McCormack, Ian A. Kyles, Roger D. Isaac
  • Patent number: 9934786
    Abstract: A system is disclosed for facilitating free form dictation, including directed dictation and constrained recognition and/or structured transcription among users having heterogeneous native (legacy) protocols for generating, transcribing, and exchanging recognized and transcribed speech. The system includes at least one system transaction manager having a “system protocol,” to receive a verified, streamed speech information request from at least one authorized user employing a first legacy user protocol. The speech information request which includes spoken text and system commands is generated using a user interface capable of bi-directional communication with the system transaction manager and supporting dictation applications, including prompts to direct user dictation in response to user system protocol commands and systems transaction manager commands.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 3, 2018
    Assignee: Advanced Voice Recognition Systems, Inc.
    Inventors: Joseph H. Miglietta, Michael K. Davis
  • Patent number: 9892050
    Abstract: A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i?1)-th translation stage, i?[1, . . . , N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Florian A. Auernhammer, Patricia M. Sagmeister
  • Patent number: 9894183
    Abstract: Controlling a remote procedure call from a client computer to a server computer, the client computer extracts a periodic remote procedure call from among a plurality of remote procedure calls from the client computer and extracts a non-periodic remote procedure call from among the plurality of remote procedure calls from the client computer. The client computer identifies a first information associated with the extracted periodic remote procedure call that is an item whose value is determined to represent data targeted by the periodic remote procedure call. The client computer identifies a second information associated with the extracted non-periodic remote procedure call that is a targeted data value of the item, and sets a priority level, used to select for execution the periodic procedure call, based on the first information and the second information.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Kurokawa, Takahisa Mizuno, Tomohiro Shioya, Sayaka Tamai
  • Patent number: 9888024
    Abstract: Techniques are disclosed for detecting security incidents based on low confidence security events. A security management server aggregates a collection of security events received from logs from one or more devices. The security management server evaluates the collection of security events based on a confidence score assigned to each distinct type of security event. Each confidence score indicates a likelihood that a security incident has occurred. The security management server determines, based on the confidence scores, at least one threshold for determining when to report an occurrence of a security incident from the collection of security events. Upon determining that at least one security event of the collection has crossed the at least one threshold, the security management server reports the occurrence of the security incident to an analyst.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 6, 2018
    Assignee: SYMANTEC CORPORATION
    Inventors: Kevin Roundy, Michael Spertus
  • Patent number: 9866592
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing, by a policy enforcement system, a plurality of policies and data associating a plurality of user credentials with the plurality of policies; receiving, from a client device, a request for data from a file system, the request further comprising user credentials; forwarding the request for data to a second node that stores the data from the file system; receiving, from the node, the data from the file system; selecting from the plurality of policies, based on the received user credentials and the data associating the plurality of user credentials with the plurality of policies, one or more policies that correspond to the received user credentials; filtering, by the policy enforcement system, the data from the file system based on the one or more policies; and sending the filtered data to the client device.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 9, 2018
    Assignee: BlueTalon, Inc.
    Inventors: Dilli Dorai Minnal Arumugam, Prasad Mujumdar
  • Patent number: 9858371
    Abstract: A method for generating a minimized combined scenario for use in simulation, from a post-silicon validation test that includes a combined scenario, may include obtaining a failed scenario loop of a scenario of the combined scenario that includes combined action scenarios that were executed in loops during a post-silicon validation test of a system on chip; and adding any loops of other scenarios of the combined scenario that were executed at least partially concurrently with the failed scenario loop, while discarding any loops of other scenarios of the combined scenario that were completed during the post-silicon validation test before the failed scenario loop or did not commence before the failed scenario loop was completed.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: January 2, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Meir Ovadia
  • Patent number: 9852048
    Abstract: Embodiments of the present invention provide methods and systems for simulating variable changes during runtime of a process. The method includes recording variable changes and process context, and filtering sensitive content from the variable changes and process context. The recorded variable changes are recorded into a timeline containing the change in values to the variable changes, which is executed in a simulation environment, in order to debug the process.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ling Lan, Xin Peng Liu, Shu Chao Wan, Liang Wang, Yue Wang, Jing Jing Wei, Yu Zhang, Dian Guo Zou
  • Patent number: 9817832
    Abstract: Providing a service in a storage system includes using a predicate that corresponds to a subset of storage objects in a set of storage objects stored in the storage system. The predicate is used to select or reject the objects to which the service is to be provided. The predicate is applied to the set of storage objects to obtain the subset of storage objects. The service is then invoked for the subset of storage objects selected according to the predicate. A trigger event causes invocation of the service. The trigger event may be periodic and/or may be a storage object lifecycle event, a storage object access related event, an event corresponding to a state change of the storage system, or an event that is external to the storage system. The trigger event may include the predicate being modified.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: November 14, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Boris V. Protopopov, Rossen Dimitrov, Arkady Kanevsky, Patrick Eaton, Jurgen Leschner, David Cohen
  • Patent number: 9799009
    Abstract: The present invention provides a system and method to dynamically identify, assemble, or otherwise simulate the availability of resources for an orchestrated service or application, thereby allowing for strategic changes in scheduling, purchasing, hiring, and the like to ensure that the resources needed to deliver the desired outcome during a particular time period are present. In particular, the system includes an orchestration module storing a plurality of resource parameters, correlating a predetermined criterion for one or more resources with an event, and simulating the event, where the simulation includes comparing the stored plurality of parameters with the predetermined criterion. The system further determines whether the stored plurality of parameters satisfy the predetermined criterion, and may store the determination for subsequent evaluation.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: October 24, 2017
    Assignee: Avaya Inc.
    Inventors: Christopher Hobbs, John Bell, Raymond B. Wallace, Laurence A. Beaulieu
  • Patent number: 9747142
    Abstract: A method for centralizing events for a multilevel hierarchical computer management system, the system including a plurality of source equipments generating events and a plurality of event collectors per level, the method including selecting by an upper level collector a lower level collector according to operational parameters and/or a link quality of service of the lower level collector; receiving by the collector the events from the selected lower level collector; periodically verifying if the selected collector is available and if not repeating the selection step; and comparing by the upper level collector its events with those from the unselected lower level collectors and receiving from one of these unselected lower level collectors the events that are different.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: August 29, 2017
    Assignee: CASSIDIAN SAS
    Inventors: Manuel Henry, Valérian Rossigneux
  • Patent number: 9720999
    Abstract: Techniques for meta-directory control and evaluation of events are provided. Disparate events from heterogeneous processing environments are collected as the events are produced by resources within the processing environments. The events are filtered and organized into taxonomies. Next the filtered and organized events are assigned to nodes of a Meta directory, each node defining a relationship between two or more of the resources and policy is applied. Finally, additional policy is evaluated in view of the events and their node assignments with other events, and one or more automated actions are then taken.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 1, 2017
    Assignee: Micro Focus Software Inc.
    Inventors: Stephen R Carter, Scott A. Isaacson
  • Patent number: 9652237
    Abstract: A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Roger Gramunt, Ramon Matas, Benjamin C. Chaffin, Neal S. Moyer, Rammohan Padmanabhan, Alexey P. Suprun, Matthew G. Smith
  • Patent number: 9563563
    Abstract: A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i?1)-th translation stage, i?[1, . . . , N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Florian A. Auernhammer, Patricia M. Sagmeister
  • Patent number: 9563471
    Abstract: A simulation apparatus that performs parallel execution of multiple logical processes obtained by modeling a plurality of components included in a system to be simulated. The apparatus includes: (i) a condition generating unit configured to generate, on the basis of communication delays between the multiple logical processes, constraint conditions to be satisfied by initial time shifts given to the multiple logical processes and look-ahead times each to be permitted by a message sent from a logical process serving as a communication source to a logical process serving as a communication destination to permit look-ahead; and (ii) a solver unit configured to solve an optimization problem that satisfies the constraint conditions and minimizes overhead in communication of messages between the multiple logical processes, and obtain the initial time shifts of the multiple logical processes and the look-ahead times between the multiple logical processes.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Tatsuya Ishikawa, Asim Munawar, Shuichi Shimizu
  • Patent number: 9564375
    Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 7, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Randy Mann, Sandeep Puri, Sonia Ghosh, Anuj Gupta, Xusheng Wu
  • Patent number: 9547568
    Abstract: A verification test is performed on a device containing master and slave units connected via a bus. In the verification test, a first signal is transferred between a first master unit and a first slave unit during a first transfer period while a second signal is transferred between a second master unit and a second slave unit during a second transfer period. The second transfer period overlaps at least a part of the first transfer period. When the first transfer period is longer than a third transfer period, first combination information indicating the combination of the first master unit and first slave unit is stored in a storage unit, in conjunction with second combination information indicating the combination of the second master unit and second slave unit.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: January 17, 2017
    Assignee: SOCIONEXT INC.
    Inventor: Taku Kawamura
  • Patent number: 9430311
    Abstract: Disclosed are methods and computer-readable instructions for capturing and reporting information for a failure mode effects analysis. One method includes populating and generating a cause and effect map via a graphical user interface, the cause and effect map having a plurality of events interconnected with one or more propagation lines and of the plurality of events being associated with one or more potential failures of a component or subsystem of a system, performing a failure mode effects analysis (FMEA) on the cause and effect map, graphically depicting the cause and effect map to reflect risk based on the FMEA, and visually distinguishing at least one of the plurality of events.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: August 30, 2016
    Assignee: Halliburton Energy Services, Inc.
    Inventor: Daniel Voon Leng Lee
  • Patent number: 9396445
    Abstract: A control system usable in a print shop where print jobs are processed with at least one print shop related resource is provided. The at least one print shop related resource is operated over multiple discrete time intervals such that production related data is generated for each one of the multiple discrete time intervals. The production related data generated during each one of the multiple discrete intervals is collected and stored in memory. The control system includes a controller and a program. The program operates with the controller to calculate at least one performance measure value from the stored production related data, and to determine, with the at least one calculated performance measure value, whether any further collection of production related data is required.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: July 19, 2016
    Assignee: Xeroz Corporation
    Inventor: Sudhendu Rai
  • Patent number: 9390386
    Abstract: Methods, systems, and apparatus for predicting the characteristics of a user are described. A model based on a conditional multivariate normal distribution and social relationship information between the selected user and each of one or more other users are obtained. One or more characteristics of the selected user are determined based on the model and the social relationship information. The user characteristics may be determined by adjusting the characteristics of a typical source user according to the model and the social relationship information of the selected user.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 12, 2016
    Assignee: Neustar IP Intelligence, Inc.
    Inventors: Armand Erik Prieditis, Wonhong Lee
  • Patent number: 9336100
    Abstract: Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the first memory location is dependent, with the set of backtrack locations being made up of at least one of: memory locations and register locations; and (iii) comparing respective simulation values and actual values for at least one of the backtrack locations to help determine a cause of the miscompare at the first memory location.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Vysakh Kolassery, Gunaranjan Kurucheti, Subrat K. Panda
  • Patent number: 9329970
    Abstract: First and second simulated processing of a stream-based computing application using respective first and second simulation conditions may be performed. The first and second simulation conditions may specify first and second operator graph configurations. Each simulated processing may include inputting a stream of test tuples to the stream-based computing application, which may operate on one or more compute nodes. Each compute node may have one or more computer processors and a memory to store one or more processing elements. Each simulated processing may be monitored to determine one or more performance metrics. The first and second simulated processings may be sorted based on a first performance metric to identify a simulated processing having a first rank. An operator graph configuration associated with the simulated processing having the first rank may be selected if the first performance metric for the simulated processing having the first rank is within a processing constraint.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Branson, John M. Santosuosso
  • Patent number: 9317331
    Abstract: In an embodiment, a method for interactively varying scheduling of a multi-threaded application executing on a symmetric multi-core processor provides an interface in a co-simulation design environment. The interface is associated with a multi-threaded application executing on a target processor that includes symmetric processor cores. The method also sets a scheduling attribute of the multi-threaded application using the interface. The setting occurs when the multi-threaded application is executing. The method further receives data associated with the executing of the multi-threaded application in the co-simulation design environment when the multi-threaded application is executing subsequent to the setting of the scheduling attribute.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 19, 2016
    Assignee: The MathWorks, Inc.
    Inventors: David Koh, Murat Belge
  • Patent number: 9304888
    Abstract: Embodiments are directed to executing a workflow using a virtualized clock and to ensuring idempotency and correctness among workflow processes. In one scenario, a computer system a computer system determines that a workflow session has been initialized. The workflow session runs as a set of episodes, where each episode includes one or more pulses of work that are performed when triggered by an event. Each workflow session is processed according to a virtualized clock that keeps a virtual session time for the workflow session. The computer system receives an event that includes an indication of the time the event was generated, and then accesses the received event to determine which pulses of work are to be performed as part of a workflow session episode. The computer system then executes the determined pulses of work according to the virtual session time indicated by the virtualized clock.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 5, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kenneth David Wolf, Justin David Brown, Edmund Samuel Victor Pinto, Nathan Christopher Talbert
  • Patent number: 9274919
    Abstract: A system and method for tracing individual transactions on method call granularity is disclosed. The system uses instrumentation based transaction tracing mechanisms to enhance thread call stack sampling mechanisms by a) only sampling threads executing monitored transactions while execution is ongoing b) tagging sampled call stacks with a transaction id for correlation of sampled call stacks with instrumentation bases tracing data. The combination of instrumentation based tracing with thread call stack sampling reduces sampling generated overhead by only sampling relevant thread, and reduces instrumentation generated overhead because it allows reducing instrumentation.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 1, 2016
    Assignee: dynaTrace software GmbH
    Inventors: Bernd Greifeneder, Christian Schwarzbauer, Stefan Chiettini, Jurgen Richtsfeld, Erich Georg Hochmuth
  • Patent number: 9248374
    Abstract: A client device platform may provide an emulator with game inputs to advance an emulated game from a first state to a second state. The emulator may record the game inputs. Once the emulation of the game is suspended, the client device platform may deliver a replay request to the emulator. Upon receiving the replay request, the emulator may re-emulate the game inputs that have been stored in the emulator's memory. The re-emulation will produce the replay which may be delivered back to the client device platform. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 2, 2016
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Brian Michael Christopher Watson, Victor Octav Suba Miura, Jacob P. Stine, Nicholas J. Cardell
  • Patent number: 9239898
    Abstract: In some embodiments, in a method, a netlist is received. The netlist comprises a subcircuit that comprises a device and a rule check module. The rule check module specifies a plurality of terminals of the device subject to an operating space, and at least one parameter that controls a non-rectangular boundary of the operating space. The netlist is simulated to obtain simulation data associated with the terminals of the device. The operating space that has the non-rectangular boundary is formed by using the at least one parameter. The simulation data is checked against the operating space. A situation in which the checked simulation data does not fall within the operating space is reflected.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: January 19, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Ming Chen, Yi-Ting Wang, Jian-Zhi Huang, Chia-Ying Lin, Chia-Chi Ho, Ya-Chin Liang, Ke-Wei Su, Chung-Shi Chiang
  • Patent number: 9223910
    Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 29, 2015
    Assignee: XILINX, INC.
    Inventors: Ishita Ghosh, Saikat Bandyopadhyay, Kumar Deepak, Hem C. Neema, David K. Liddell
  • Patent number: 9128748
    Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: September 8, 2015
    Assignee: ROCKETICK TECHNOLOGIES LTD.
    Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
  • Patent number: 9075939
    Abstract: A method for the co-simulation of two or more interacting mathematical models in which each model has at least one input port and one output port for inputting and outputting values of parameters in a predefined parameter protocol. The unit of measurement is identified for each parameter in the model and a scaling factor is then generated to equalize the units of measurement for each parameter in each model. The parameter protocol for each port is then determined and a virtual bus with unique locations is configured for each parameter in the models. The parameters from the models are then configured as a function of the parameter protocol so that the same parameters from different models are associated with the same location in the virtual bus.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: July 7, 2015
    Assignee: Hitachi, Ltd
    Inventors: Sujit Phatak, Donald J. McCune
  • Patent number: 9075666
    Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: July 7, 2015
    Assignee: Synopsys, Inc.
    Inventors: Jan M. J. Janssen, Thorsten H. Grötker, Christoph Schumacher, Rainer Leupers
  • Publication number: 20150127318
    Abstract: An operation of a processor with out-of-order execution is simulated by a computer configured to access a storage unit storing a specific internal state of the processor. A program executed by the processor is divided into a plurality of blocks. When a target block on which an operation simulation is to be performed is changed from a first block to a second block in the plurality of blocks, the computer determines whether the second block is a block that performs a process according to an exception that has occurred in the first block. When it is determined that the second block is a block that performs the process according to the exception, the computer performs the operation simulation of the second block after changing an internal state of the processor in the operation simulation to the specific internal state stored in the storage unit.
    Type: Application
    Filed: September 25, 2014
    Publication date: May 7, 2015
    Applicant: Fujitsu Limited
    Inventors: David Thach, Shinya Kuwamura, Atsushi Ike
  • Patent number: 9002899
    Abstract: A method of merging at least two state machines includes: mapping a first node from a first state machine to a second node of a second state machine to generate an input pair; performing a depth-first recursive analysis of transitions and nodes in the first state machine and the second state machine based on the input pair to construct an output node; and mapping the output node to a third state machine.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventor: Branimir Z. Lambov
  • Patent number: 8995288
    Abstract: A deployed configurable communication integrated circuit (IC) and/or chipset which may be integrated within a wireless communication and/or multi-media communication device may be operable to monitor its operating conditions, performance and/or utilization characteristics. It may send information via a wireless, optical and/or wired network to a remote analysis and/or development system and/or service, such as an engineering service, that may determine and return configuration parameters. The configuration parameters may be utilized to adjust antenna and/or MIMO, SIMO, MISO and beamforming configuration, power level, interference rejection, equalizer length, dynamic range, modulation, encoding and/or decoding, analog to digital conversion precision, error detection and/or correction parameters, MAC parameters such as timing thresholds, transmit window size and/or buffer space.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: March 31, 2015
    Assignee: Broadcom Corporation
    Inventor: Jeyhan Karaoguz
  • Patent number: 8990062
    Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Ryo Kawahara
  • Publication number: 20150081266
    Abstract: An information processing apparatus includes a simulator configured to simulate a process to be executed by an apparatus based on an operation procedure defined in first definition information, and one or more status changers each configured to detect arrival of a time specified in second definition information by monitoring an event generated based on the simulated process, and to change a status of the simulator to a status specified in the second definition information based on the detected time. In the information processing apparatus, the simulator simulates a process to be executed by the apparatus in accordance with a request from a program to cause the apparatus to execute the process in the status changed by the status changer.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 19, 2015
    Inventors: Satoshi TAKAHASHI, Kunihiro AKIYOSHI
  • Patent number: 8983632
    Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: March 17, 2015
    Assignee: Honeywell International Inc.
    Inventors: Paul Wacker, Ralph Collins Brindle, Shilpa Anand
  • Patent number: 8977532
    Abstract: Techniques for estimating time remaining for an operation are described. Examples operations include file operations, such as file move operations, file copy operations, and so on. A wide variety of different operations may be considered in accordance with the claimed embodiments, further examples of which are discussed below. In at least some embodiments, estimating a time remaining for an operation can be based on a state of the operation. A state of an operation, for example, can be based on events related to the operation itself, such as the operation being initiated, paused, resumed, and so on. A state of an operation can also be based on events related to other operations.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Francisco Alvarez Cavazos, Jordi Mola
  • Patent number: 8942969
    Abstract: Systems and methods for event simulation with energy analysis. A method includes receiving a plurality of environment objects, and receiving energy attributes corresponding to one or more of the environment objects. The method includes simulating the operation of the environment objects and, during the simulation, calculating values for the energy attributes reflecting the energy use for the respective energy attributes. The method includes displaying the calculated values for the energy attributes.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 27, 2015
    Assignee: Siemens Product Lifecycle Management Software Inc.
    Inventor: Matthias Heinicke
  • Publication number: 20150019195
    Abstract: Systems and methods for modeling a prospective systems migration between server systems are provided. Performance data associated with a plurality of applications in a first server system may be collected. A selection of a set of applications in the plurality of applications to migrate to a second server system may be processed. Combined performance data that estimates how the set of applications will perform on the second server system may be computed using at least some of the performance data. Based on the combined performance data, indications as to whether the set of applications should be migrated to the second server system may be provided.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 15, 2015
    Inventor: George Davis
  • Patent number: 8914678
    Abstract: A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Robert Daniel Brummayer