Abstract: In an embodiment, a method for interactively varying scheduling of a multi-threaded application executing on a symmetric multi-core processor provides an interface in a co-simulation design environment. The interface is associated with a multi-threaded application executing on a target processor that includes symmetric processor cores. The method also sets a scheduling attribute of the multi-threaded application using the interface. The setting occurs when the multi-threaded application is executing. The method further receives data associated with the executing of the multi-threaded application in the co-simulation design environment when the multi-threaded application is executing subsequent to the setting of the scheduling attribute.

Abstract: Embodiments are directed to executing a workflow using a virtualized clock and to ensuring idempotency and correctness among workflow processes. In one scenario, a computer system a computer system determines that a workflow session has been initialized. The workflow session runs as a set of episodes, where each episode includes one or more pulses of work that are performed when triggered by an event. Each workflow session is processed according to a virtualized clock that keeps a virtual session time for the workflow session. The computer system receives an event that includes an indication of the time the event was generated, and then accesses the received event to determine which pulses of work are to be performed as part of a workflow session episode. The computer system then executes the determined pulses of work according to the virtual session time indicated by the virtualized clock.

Abstract: A system and method for tracing individual transactions on method call granularity is disclosed. The system uses instrumentation based transaction tracing mechanisms to enhance thread call stack sampling mechanisms by a) only sampling threads executing monitored transactions while execution is ongoing b) tagging sampled call stacks with a transaction id for correlation of sampled call stacks with instrumentation bases tracing data. The combination of instrumentation based tracing with thread call stack sampling reduces sampling generated overhead by only sampling relevant thread, and reduces instrumentation generated overhead because it allows reducing instrumentation.

Abstract: A client device platform may provide an emulator with game inputs to advance an emulated game from a first state to a second state. The emulator may record the game inputs. Once the emulation of the game is suspended, the client device platform may deliver a replay request to the emulator. Upon receiving the replay request, the emulator may re-emulate the game inputs that have been stored in the emulator's memory. The re-emulation will produce the replay which may be delivered back to the client device platform. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: In some embodiments, in a method, a netlist is received. The netlist comprises a subcircuit that comprises a device and a rule check module. The rule check module specifies a plurality of terminals of the device subject to an operating space, and at least one parameter that controls a non-rectangular boundary of the operating space. The netlist is simulated to obtain simulation data associated with the terminals of the device. The operating space that has the non-rectangular boundary is formed by using the at least one parameter. The simulation data is checked against the operating space. A situation in which the checked simulation data does not fall within the operating space is reflected.

Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.

Abstract: Methods, systems, and machine readable medium for multi-thread safe system level modeling simulation (SLMS) of a target system on a host system. An example of a SLMS is a SYSTEMC simulation. During the SLMS, SLMS processes are executed in parallel via a plurality of threads. SLMS processes represent functional behaviors of components within the target system, such as functional behaviors of processor cores. Deferred execution may be used to defer execution of operations of SLMS processes that access a shared resource. Multi-thread safe direct memory interface (DMI) access may be used by a SLMS process to access a region of the memory in a multi-thread safe manner. Access to regions of the memory may also be guarded if they are at risk of being in a transient state when being accessed by more than one SLMS process.

Abstract: A method for the co-simulation of two or more interacting mathematical models in which each model has at least one input port and one output port for inputting and outputting values of parameters in a predefined parameter protocol. The unit of measurement is identified for each parameter in the model and a scaling factor is then generated to equalize the units of measurement for each parameter in each model. The parameter protocol for each port is then determined and a virtual bus with unique locations is configured for each parameter in the models. The parameters from the models are then configured as a function of the parameter protocol so that the same parameters from different models are associated with the same location in the virtual bus.

Abstract: An operation of a processor with out-of-order execution is simulated by a computer configured to access a storage unit storing a specific internal state of the processor. A program executed by the processor is divided into a plurality of blocks. When a target block on which an operation simulation is to be performed is changed from a first block to a second block in the plurality of blocks, the computer determines whether the second block is a block that performs a process according to an exception that has occurred in the first block. When it is determined that the second block is a block that performs the process according to the exception, the computer performs the operation simulation of the second block after changing an internal state of the processor in the operation simulation to the specific internal state stored in the storage unit.

Abstract: A method of merging at least two state machines includes: mapping a first node from a first state machine to a second node of a second state machine to generate an input pair; performing a depth-first recursive analysis of transitions and nodes in the first state machine and the second state machine based on the input pair to construct an output node; and mapping the output node to a third state machine.

Abstract: A deployed configurable communication integrated circuit (IC) and/or chipset which may be integrated within a wireless communication and/or multi-media communication device may be operable to monitor its operating conditions, performance and/or utilization characteristics. It may send information via a wireless, optical and/or wired network to a remote analysis and/or development system and/or service, such as an engineering service, that may determine and return configuration parameters. The configuration parameters may be utilized to adjust antenna and/or MIMO, SIMO, MISO and beamforming configuration, power level, interference rejection, equalizer length, dynamic range, modulation, encoding and/or decoding, analog to digital conversion precision, error detection and/or correction parameters, MAC parameters such as timing thresholds, transmit window size and/or buffer space.

Abstract: The present invention is achieved as software which operates on a computer system and which performs calculation by receiving various data as inputs, and which outputs values. The present invention is applicable to a coarse-grained system architecture model including the foregoing event-driven simulation and receives, as inputs, execution time T and the number of memory accesses, N, in the simulation step of the model. Thus, various estimates at the occurrence of memory access conflict are obtained at a simulation speed sufficient for evaluating the effect of the memory access conflict and comparing it with many alternative architectures without information on the correct timing of memory accesses in consideration of memory synchronous accesses and arbitration. The results of this simulation are estimated simulation-step execution time T? under memory access conflict and memory-bandwidth utilization factors {U?i} in individual simulation steps under memory access conflict.

Abstract: An information processing apparatus includes a simulator configured to simulate a process to be executed by an apparatus based on an operation procedure defined in first definition information, and one or more status changers each configured to detect arrival of a time specified in second definition information by monitoring an event generated based on the simulated process, and to change a status of the simulator to a status specified in the second definition information based on the detected time. In the information processing apparatus, the simulator simulates a process to be executed by the apparatus in accordance with a request from a program to cause the apparatus to execute the process in the status changed by the status changer.

Abstract: A system having a function block execution framework. Function blocks may be for use in a control system design. These blocks may be selected from a library of a function block engine. Selected function blocks may be executed for operational purposes. They may be continuously executed by a processor to maintain operational status. However, since a function block engine and a resulting system of function blocks may be operated with battery power, executions of function blocks may be reduced by scheduling the executions of function blocks to times only when they are needed. That means that the processor would not necessarily have to operate continuously to maintain continual execution of the function blocks and thus could significantly reduce consumption of battery power.

Abstract: Techniques for estimating time remaining for an operation are described. Examples operations include file operations, such as file move operations, file copy operations, and so on. A wide variety of different operations may be considered in accordance with the claimed embodiments, further examples of which are discussed below. In at least some embodiments, estimating a time remaining for an operation can be based on a state of the operation. A state of an operation, for example, can be based on events related to the operation itself, such as the operation being initiated, paused, resumed, and so on. A state of an operation can also be based on events related to other operations.

Abstract: Systems and methods for event simulation with energy analysis. A method includes receiving a plurality of environment objects, and receiving energy attributes corresponding to one or more of the environment objects. The method includes simulating the operation of the environment objects and, during the simulation, calculating values for the energy attributes reflecting the energy use for the respective energy attributes. The method includes displaying the calculated values for the energy attributes.

Abstract: Systems and methods for modeling a prospective systems migration between server systems are provided. Performance data associated with a plurality of applications in a first server system may be collected. A selection of a set of applications in the plurality of applications to migrate to a second server system may be processed. Combined performance data that estimates how the set of applications will perform on the second server system may be computed using at least some of the performance data. Based on the combined performance data, indications as to whether the set of applications should be migrated to the second server system may be provided.

Abstract: A system for simplifying message sequences is disclosed. The system includes a shrink component and a message simplification component. The shrink component is configured to receive a failure inducing message sequence and to provide a shrunk sequence based on the failure inducing message sequence. The shrunk sequence has less or equal number of messages than the failure inducing message sequence. The message simplification component is configured to receive the shrunk sequence and to simplify messages within the shrunk sequence to generate a simplified message sequence including debugging hints.

Abstract: Techniques to simulate production events are described. Some embodiments are particularly directed to techniques to simulate production events based on randomization across a distribution of production events. In one embodiment, for example, an apparatus may comprise a simulation application operative to simulate one or more commands in a simulated environment using a task hierarchy, the simulation application comprising a configuration component, a command generation component, and an execution component, wherein simulating the one or more commands comprises executing one or more task commands.

Abstract: A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity setting, a group of consecutive transactions is grouped into a super transaction, and the statistical values representing the super transaction are recorded to represent the group of transactions. The super transactions are visualized in a visualization tool for analyzing the performance of the model.

Abstract: A processor for use in simulating operation of a portion of an electrical circuit is provided. The processor is configured to receive at least one input indicative of electrical circuit data related to the electrical circuit being simulated, generate a model of the electrical circuit based on the at least one input, receive a user input that indicates the portion of the electrical circuit to be simulated, generate, based on the user input and the electrical circuit model, a partial circuit snapshot that corresponds to the portion of the electrical circuit, and apply at least one event to the partial circuit snapshot to simulate operation of the corresponding portion of the electrical circuit.

Abstract: A method for use with a computer simulation includes providing an ability to run a simulation in which a plurality of client devices communicate over a network to interact with the simulation, providing an ability to generate a first user interface on each of the plurality of client devices for allowing users associated with the client devices to interact with the simulation, providing an ability to allow users associated with a subset of the plurality of client devices to interact with information that includes a representation of at least a portion of an environment of the simulation without allowing access thereto by the other client devices, and providing an ability for the simulation to generate an event in response to interactions with the information. A system for use in running a computer simulation and a storage medium storing a computer program executable by a processor based system are also disclosed.

Abstract: A simulation apparatus has a type setting section that sets a type of mode of electric power consumption of equipment, and an output section that simulates an amount of the electric power consumption of the equipment in accordance with the type set by the type setting section and outputting the amount of electric power consumption thus simulated.

Abstract: In a computer-implemented process modeling and simulating environment, an analyzer receives a process model with parameters in combination with data from previous or planned process performances. An analyzer receives a simulation target from a user, calculates evaluation results that represent the influence of the parameters in view of the simulation target, and presents the evaluation results as indicators to the user. Upon receiving modifications to the performance data, the process is simulated with modified performance data. Alternatively, the evaluation results are converted to computer instructions to automatically modify the process parameters.

Abstract: In one embodiment, a plurality of kernels are provided. Each kernel may simulate a partition of a design under test. A plurality of event regions are provided. The regions may be in an ordered priority. Events for the device under test may be determined for event regions in each of the kernels. An event region to execute events in is then determined and all kernels may execute events in the same event region. Kernels then execute events for the determined event region. When finished executing events in an event queue, data synchronization may occur. In this case, information may be synced among kernels, such as status and state values for shared objected are synchronized.

Abstract: An illumination system is provided, including a light emitting device and a control device, wherein the control device is coupled to the light emitting device so as to capture a situation data in a remote end and generate a situation signal correspondingly. The light emitting device receives the situation signal and generates a simulating situation.

Abstract: A pavement condition analysis system and method models a state of a roadway by processing at least traffic and weather data to simulate the impact of traffic and weather conditions on a particular section of a transportation infrastructure. Traffic data is ingested from a plurality of different external sources to incorporate various approaches estimating traffic characteristics such as speed, flow, and incidents, into a road condition model to analyze traffic conditions on the roadway in order to improve road condition assessments and/or prediction.

Abstract: A spiral resonator is analyzed by modeling a set of loops of the spiral resonator with a model of a circuit including a set of units, wherein each unit includes a resistor and an inductor to model one loop of the spiral resonator. Values of the resistor and the inductor of each unit are based on properties of a corresponding loop. Electrical connection of the loops is modeled by electrically connecting the units in a corresponding order of the loops. A capacitive coupling in the spiral resonator is modeled by connecting adjacent units with at least one capacitor having a value based on the capacitive coupling between two corresponding adjacent loops. An inductive coupling in the spiral resonator is modeled based on inductive coupling between pairs of loops. The operation of the spiral resonator is simulated with the model of the circuit.

Abstract: An energy-saving optimizing program works closely with conventional process simulation programs by applying energy saving paradigms embodied in script files that may review data inherent in the simulation program to identify possible energy-saving opportunities. When the script files identify a possible energy savings, they may interact with the simulation program to evaluate the savings potential and present the same to a user. In this way opportunistic energy savings may be provided even for processes that resist close form global optimization.

Abstract: A system and method of operating an integrated circuit (IC) having a fixed layout of one or more blocks having one or more current sources therein that draw electrical current from a power source. The method includes dynamically issuing to a block configured to perform operations responsive to an instruction received at the block, a reserve amount of tokens; determining for each issuance of instruction to the block whether that block's reserve token amount exceeds zero; and one of: issuing the instruction to the block if the token reserve for that block is greater than one, and decrementing, after issuance of the instruction, by one token the block's reserve token amount, or, preventing issuance of an instruction to the block. In the method, each block may be initialized to have: a reserve token amount of zero, a token expiration period; a token generation cycle and a token generation amount.

Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

Abstract: A method for calculating a primary time constant of a power grid. It comprises the steps of: establishing an electromechanical transient model of the power grid using the widely used power system analysis software package (PSASP) according to the actual power grid parameters and network topology; establishing an electromagnetic transient model under PASAP using the actual power grid parameters for a site which requires the calculation of the primary time constant of the power grid, and setting a ground short circuit fault at the site; obtaining a transient short circuit current of the short circuit point of the power grid using a hybrid simulation method of the electromechanical and electromagnetic transient models; filtering out a periodic component in the transient short circuit current to obtain a non-periodic component attenuated with time, and finding the attenuation time constant of the non-periodic component which is the primary time constant of the power grid.

Abstract: A system with a dynamic temporal dimension for monitoring and control of contact centers, comprising: a scalable simulation service configured with a virtual environment that replicates and is maintained in synchrony with a production contact center environment; an analysis manager; a persistent query service; and a visualizer. The persistent query service receives data from contact center systems and updates virtual tables based on the updates; the analysis manager, sends real-time updates to the visualizer, and the visualizer updates a visualization provided to a user by displaying the real-time updates as a set of past states; and the scalable simulation service performs a time-warped simulation to compute at least a future state of one of the virtual environments and sends a second plurality of updates to the visualizer, and the visualizer updates the visualization provided to the user by displaying the second plurality of real-time updates as a projected future state.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: An algorithm and architecture are disclosed for performing multi-argument associative operations. The algorithm and architecture can be used to schedule operations on multiple facilities for computations or can be used in the development of a model in a modeling environment. The algorithm and architecture resulting from the algorithm use the latency of the components that are used to process the associative operations. The algorithm minimizes the number of components necessary to produce an output of multi-argument associative operations and also can minimize the number of inputs each component receives.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.

Abstract: A method for inserting characteristic extractor is provided. The method includes parsing a transaction level model (TLM) of an electronic device of a target system to find out at least one target point of an operation status of the electronic device; and inserting at least one characteristic extractor into the at least one target point.

Abstract: A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values.

Abstract: Related communication signals between a simulator and an emulator are organized into logical channels. The signals in each channel are then be transmitted only as needed, reducing the use of the communication pathways between the simulator and the emulator. Further, the circuit components that will receive the communication signals to be shared on a channel are be physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to receive the signals sent by the simulator. Similarly, emulator components that send communication signals to be shared on a channel are physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to send these signals to the simulator.

Abstract: The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S2). The voltage fluctuation analysis step at the gate level is executed on an entire chip TP. Next, a step of obtaining waveforms of power supply voltage and ground voltage (Vss) according to the voltage fluctuation analysis step is executed (step S4). Subsequently, a signal analysis step at a transistor level is performed (step S6). The signal analysis step at the transistor level is performed in an area narrower than the entire chip TP, for example, on one or more functional modules. After that, a step of obtaining a signal analysis result according to the signal analysis step is executed (step S8).

Abstract: A method for a discrete event simulation model of a system utilizing a just-in-time compilation for one or more code blocks associated with an event in one or more discrete event simulation models is disclosed. The method comprises the steps of determining the event in a discrete event simulation model according to a kind of event, retrieving the code block associated with the event, compiling the code block into an object file using a compiler, linking the object file with a predetermined function in a simulation library, compiling the object file and the predetermined function into a customized dynamic link library, loading the customized dynamic link library (DLL) within a discrete event simulation program execution and linking the customized DLL to a simulation program. The method allows user entered logic to be executed in high speed by integrating a just-in-time compiler embedded into the simulation model to allow dynamic generation of high speed code blocks within one or more simulations.

Abstract: Methods, apparatuses, and computer readable media for utilizing a single model of event-based energies at multiple hierarchical levels of a design. The event-based energy model contains multiple interfaces that access or reference lower level power data, such as pin-based power data. The power of a transaction level definition of a design is estimated using the event-based energy model. The transaction-level definition of the design uses indirect references to access the event-based energy model. Other abstraction levels of the design may have their power estimated using the same low-level event-based energy model. Overall, a consistent power estimation of a design is performed using the same event-based energy model at different levels of abstraction of the design flow.

Abstract: A method and apparatus for developing microcomputer-based systems. A controller model having at least one parameter is simulated and, similarly, a plant model having at least one parameter and controlled by the controller model is simulated. A user interface then has access to the parameters of the controller model and plant model and optionally suspends the execution of the controller model and plant model in response to a trigger event. The user interface determines the status of the controller model parameters and/or plant model parameters at the time of the trigger without altering the controller model parameters or plant model parameters or the program code of the controller model.

Abstract: A performance evaluation device includes: a control timing model unit for outputting a timing for inputting a control signal input/output between plural function blocks contained in a simulation model corresponding to a hardware; a control signal transfer period calculation unit for calculating a transfer period of the control signal between the plural function blocks in accordance with the timing for inputting the control signal; a data timing model unit for outputting a timing for inputting a data signal corresponding to the control signal, which is input/output between the plural function blocks; and a data signal transfer period calculation unit for calculating a transfer period of the data signal between the plural function blocks in accordance with the timing for inputting the data signal.

Abstract: A method for predicting electrical power distribution interruptions based on common, immediate weather conditions. Daily, hourly, and bi-hourly weather data are used to predict the number of interruptions. Common weather conditions include, but are not limited to, rain, wind, temperature, lightning, humidity, barometric pressure, snow, and ice. The method includes compiling common weather data including a plurality of weather variables and the number of historical interruptions for a historical period, establishing model equations for the average value of the weather variables, combining the model equations for each of the weather variables into a composite model, and performing a regression analysis using the composite model to establish interruption prediction values. A computer program product for enabling said method and a computer system adapted to carry out said method are also included.

Abstract: In a normal operation, a physical unit simulator is allowed to speculatively perform high-speed continuous execution. Only when an actual input comes in, a speculative input and the actual input are compared with each other. Thereafter, in response to inconsistency between the inputs, the physical unit simulator is returned to a point closest to the point of the actual input and is allowed to execute a variable step module to reach the point of the actual input. Upon arrival at the point of the actual input, the simulator is shifted back to the high-speed continuous execution from there. Thus, a processing speed of the simulator can be significantly improved.

Abstract: An apparatus and method for determining an optimal global quantum value for use in event-driven simulations of a device are disclosed herein. The device is simulated using information representative of a device design corresponding to the device, the simulation of the device comprising an event-driven simulation using a provisional global quantum value. Events included in a sequence chart corresponding to the simulation using the provisional global quantum value are compared against expected events. Based on the comparison detecting at least one of the expected events being absent in the sequence chart, providing the optimal global quantum value as being smaller than the provisional global quantum value. Based on the comparison detecting no difference between the events in the sequence chart and the expected events, providing the optimal global quantum value as being larger than the provisional global quantum value.

Abstract: Methods and systems for simulating a system model are provided. The method includes loading into a computing system the system model that includes a plurality of event generating device models and non-event generating device models, scheduling a next event for each of the event generating device models independent of the next event of each other of the device models, advancing time to an earliest of the scheduled next events that is scheduled at a host device, committing the earliest of the scheduled next events, and replacing the earliest of the scheduled next events with a new next event for the host device.