Abstract: A method for digital circuit design. The first step of the process is the step of providing a circuit design in the form of a hardware definition language. Then, the process produces a binary simulation of the design by setting out for each unit of time during execution of the hardware design the a control state and a program state of the design and assigns a symbol to each signal of the design. The process proceeds by executing a symbolic simulation of the design, concluding with identifying and capturing the combinational logic expression of the simulation output and the next state functions of the simulation.

Abstract: Methods and systems for simulating acoustic field resulted from particular excitations by performing vibro-acoustic analysis of a structure are disclosed. According to one aspect of the present invention, vibro-acoustic analysis of a structure is performed in two stages. First, steady state dynamic (SSD) responses are obtained using a finite element analysis model of a structure subject to harmonic excitations (e.g., external nodal loads, pressures, or enforced motions (e.g., ground motions), etc.). The steady state responses are the results (e.g., nodal velocities at desired locations of the structure) obtained in a finite element analysis in frequency-domain. Second, an acoustic analysis is conducted according to Helmholtz equation using the nodal velocities obtained at desired locations on the structure as a boundary condition. The acoustic analysis can be performed in a number of procedures (e.g., boundary element method, Rayleigh approximation method, etc.).

Abstract: In one embodiment, we describe a method that generates seasonality rules for anomaly detection for a hierarchical/tree based data structure. A new algorithm for processing nodes in hierarchy, as well as business rules for nodes, is described. Variations and examples are given to describe different scopes and embodiments of the invention. Exclusion criteria and children nodes are used as some examples for the implementations, with flow charts to describe the methods of application, as examples.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A simulation system is provided. A simulator is configured to execute simulation of a simulation object at a processing speed. A user interface module is configured to generate at least one of a first operation screen for inputting simulation conditions on the simulation executed by the simulator and an output screen for representing a result of the simulation executed by the simulator, and to display the at least one of the first operation screen and the output screen on a display unit. An adjustor is configured to adjust an updating speed of the at least one of the first operation screen and the output screen which are displayed on the display unit by the user interface module to be different from the processing speed.

Abstract: A method and apparatus automatically determines equilibrium operating conditions of a system model. The automated method enables users of block diagram models of dynamic systems to utilize simulation to define operating conditions for linearization. The automated method further allows users to generate operating conditions during simulation instead of explicitly specifying them by hand or using trim analysis. In accordance with one example, the method of generating a linear time invariant model includes providing a system model. A user specifies at least one event at which a linearization analysis should be performed. A simulation of the system model is executed. The electronic device automatically performs the linearization analysis upon occurrence of the at least one event as the simulation is running. Output results are generated of the linearization analysis to form the linear time invariant model.

Abstract: Disclosed is a simulation test system and method for testing a vehicle electronic component capable of easily testing performance of the electronic component anytime regardless of location without repeating the same driving test.

Abstract: Systems, methods, apparatus, computer program code and means for gathering, organizing and presenting on a real time basis information pertinent to Risks associated with subjects related to the Construction Industry. Risks associated with the Construction Industry can be managed by gathering data relevant to the Construction Industry from multiple sources and aggregating the gathered data according to one or more Risk variables. An inquiry relating to a Risk subject can be received and portions of the aggregated data can be associated with the Risk subject. The associated portions of the aggregated data can be transmitted to an entity placing the inquiry or other designated destination.

Abstract: A method, and apparatus for software and resource management with a model-based architecture.

Abstract: As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown.

Abstract: A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: An emulation system includes a first circuit for emulating a first logical part of a device, a second circuit for emulating a second logical part of the device that is different from the first logical part, wherein the first circuit is separate from the second circuit, and a third circuit connecting the first circuit and the second circuit to communicate signals between the first circuit and the second circuit.

Abstract: A method is provided for sequential discrete event simulation for a distributed system having a set of nodes. A priority queue is constructed that includes events to be executed by a processor at a given node in the set. A first subset of nodes is identified. Each node in the first subset is associated with a respective subset of events and includes a highest priority event whose priority must be unconditionally re-evaluated during a next time step. A second subset of nodes is identified. Each node in the second subset is associated with a respective other subset of events and includes a highest priority event whose priority must be re-evaluated when a re-evaluation condition depending upon an external state is satisfied. A next one of the plurality of events in the priority queue is selected to be executed by the processor using the first and second subsets of nodes.

Abstract: Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a subset of those waveforms with system elements along the signal path is disclosed. By deriving a generic, re-useable, parameterized Fourier series, time-domain clock and pseudo-random data signals are generated from a subset of their true harmonic components. Time-domain signal parameters including high, low, and common-mode voltage levels, transition slew-rates, transition timing, period and/or frequency, may be designated by the user, and the computer calculates the harmonic components that will combine through the inverse Fourier transform to provide the required time-domain characteristics. By computing the frequency content of the signal directly it is possible to simulate the interaction of the signal with various system blocks while remaining in the frequency domain, thereby reducing simulation time and memory requirements.

Abstract: Methods are provided for performing depth-first searches of concrete models of systems using control flow information of the system for improved reachability analysis. The concrete model's control structure and dependencies are extracted and an over-approximated (conservative) abstract control model is created. The abstract control model simulates the concrete model during model checking. Model checking the abstract control model produces execution traces based on the control paths of the concrete model. These execution traces may be used to guide a state space search on the concrete model during invariant checking to determine satisability of one or more selected invariants of the system.

Abstract: A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for emulating a mass storage device and a file system of a mass storage device. In a first aspect, a human-portable data processing device that includes one or more data processors that perform operations in accordance with machine-readable instructions, an incoming message classifier configured to classify an incoming read command according to an address of the data requested by the incoming read command, and an emulation data generation component connected to respond to the classification of the incoming read command by the incoming message classifier to generate emulation data emulating that which would have been read by the incoming read command were the human-portable data processing device a mass storage device; and a bus controller configured to respond to the incoming read command with the emulation data generated by the emulation data generation component.

Abstract: A mechanism to dynamically vary the amount of delay for an event-generated function call is discussed. The event causing the generation of the function call may be a signal-based event, function call event or some other type of event. A function call generating delay component is inserted into a DES model and dynamically adjusts the amount of delay to apply prior to generating and transmitting the function call to an intended target component. The function call generating component reads a value from an input port in determining the amount of delay. The identified value at the input port may be a signal value or an attribute associated with an event entity received at the port.

Abstract: A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.

Abstract: A method for building a magnetic bead mathematical model includes defining component elements of the model of the magnetic bead, building the model of the magnetic bead, obtaining a characteristic curve of an impedance of a magnetic bead in a standard magnetic bead specification of the magnetic bead, ascertaining parameters of the component elements, simulating the model of the magnetic bead, and comparing the characteristic curve with the characteristic curve in the standard magnetic bead specification, to further optimize the mode of the magnetic bead.

Abstract: Disclosed are various embodiments for systems and methods facilitating simulation of metering devices in an advanced metering infrastructure (AMI) deployment. Meter simulators are executed in a simulation application, and a user can initiate a simulation based upon various operational scenario the user desires to simulate.

Abstract: A method and system for correlating out interactions, which occur due to one or a set of specific events, of an application, which is deployed in multiple adjacent tiers in an actual environment is described. First, a simulation environment corresponding to the actual environment is created. Then, specific events are led to the actual environment and the simulation environment. A pattern(s) of interactions, which are related with the specific events, between adjacent tiers in the simulation environment and a large number of interactions between adjacent tiers in the actual environment are obtained. Afterwards, interactions, which are related with the specific events, between adjacent tiers among the obtained interactions between adjacent tiers in the actual environment are correlated using a template of the obtained pattern(s) of interactions, which are related with the specific events, between adjacent tiers in the simulation environment as a template.

Abstract: Embodiments include methods, apparatus, and systems for monitoring windows on computers. In one embodiment, movement of a mouse or cursor in a focused window of the computer is analyzed to determine whether an application is properly executing in the computer.

Abstract: An acoustic modeling system and an acoustic modeling method use beam tracing techniques that accelerate computation of significant acoustic reverberation paths in a distributed virtual environment. The acoustic modeling system and method perform a priority-driven beam tracing to construct a beam tree data structure representing “early” reverberation paths between avatar locations by performing a best-first traversal of a cell adjacency graph that represents the virtual environment. To further accelerate reverberation path computations, the acoustic modeling system and method according to one embodiment perform a bi-directional beam tracing algorithm that combines sets of beams traced from pairs of avatar locations to efficiently find viable acoustic reverberation paths.

Abstract: A method for simulating behaviour of first and second interrelated components within a system. The method comprises modelling behaviour of said first and second components using first and second functional specifications; simulating behaviour of said first and second components in predetermined circumstances by instantiating at least one first entity within a hierarchy of interrelated entities; and instantiating at least one further entity in response to the or each instantiated first entity. The or each further entity is selected by a simulation system on the basis of its hierarchical relationship with the at least one first entity.

Abstract: In an embodiment, a graphical model may include a functional portion and a architectural portion. The architectural portion may describe a multiprocessor system. Inter-process communication blocks may be defined that describe the connectivity of functional blocks in the deployed version of the model. The IPC blocks may describe the connectivity of the blocks independent of the communication channel(s) that connect the processor nodes in the multiprocessor system.

Abstract: A method for designing a transformer using three secondary winding phase shift angles and a minimized core cross-sections. The method includes receiving an indication of an acceptable level of total harmonic distortion (THD) for the transformer, identifying a desired number of secondary windings per output phase of the transformer, simulating performance of various models for the transformer various potential phase shift angles, wherein each of the various models includes a set of phase shift angles for the secondary windings of the transformer. The method further includes identifying, based on the simulation, a transformer model that both has no more than three unique phase shift angles in the set and exhibits a primary side THD that is within the acceptable level, identifying an optimized core cross-sections, and reporting the identified transformer model having the three unique phase shift angle and the optimized core cross-sections.

Abstract: Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is performed in a piece-wise fashion, in a sequence of transient time points. At one or more user-specified time points (“tpunch” points) within the transient interval, the state of the circuit in the transient response at that time point is applied to the model as if it were a DC operating point, and the small-signal stability of the circuit under those conditions is analyzed. Transient instability of the circuit is thus discovered by way of simulation, allowing the designer to determine the cause and cure of that instability.

Abstract: Provided is a computer system (1) including a storage (2) for storing a netlist (31), and a contents generator (12) for generating a program (32) containing a statement to execute a plurality of operations of an operation portion contained in the netlist (31). The operation portion includes an operation performing logic operations of multiple stages and having a plurality of inputs, and an operation of a previous stage for a plurality of input sources.

Abstract: A user interface to a network simulator facilitates the use of application layer parameters and application layer logic. The user interface is configured to allow the user to define the input in a graphic form, or a text/programming form, or a combination of both. Preferably, the user interface provides common graphic forms for both inputting the data to the simulator as well as for displaying the resultant data from the simulator, thereby easing the progression from the analysis of output from one simulation to the generation of new input for a subsequent simulation.

Abstract: A systems power distribution tool integrates the design of the power source and distribution network to provide a robust interconnect topology and power source. This is accomplished with a machine of one or more computing devices configured as a systems power distribution tool. The tool “pulls” load current from the source through interconnects to the loads. This allows the interconnects to be designed to satisfy derating conditions for worst case voltage and current conditions and the power source to be designed to source the loads under actual conditions without margin stacking.

Abstract: The embodiments described herein generally relate to a discrete event simulation (DES) tool which combines the process-driven model and the event-driven model. This integrated process (which uses entities) and event simulation framework according to the various embodiments provides a platform that is appropriate for all combinations of simulation model requirements and at the same time provides higher level of model abstraction. The DES tool instantiates a new paradigm that permits flow of entities at the event-driven model layer that is analogous to their treatment at the process-driven model layer.

Abstract: A method for modeling performance of an information technology system having one or more servers for serving a number of types of transactions includes modeling a service time of each transaction type at each server and a processor overhead at each server as one of a polynomial, exponential, or logarithmic function of the average arrival rate of each transaction type at the corresponding server to generate service time and processor overhead functions and inferring optimal values of coefficients in the service time and processor overhead functions to generate a performance model of the information technology system.

Abstract: Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.

Abstract: A method for automatic fault detection with data representing a fault in an on-board system, the method including: determining, with a processor, at least two physical variables represented by said data, said at least two physical variables including at least one time-dependent variable representative of a persistence of an event in time, and at least one instantaneous variable; representing, with the processor, said data by points of a space whose coordinates are values of said at least two physical variables; an detecting, with the processor, a fault by employing a frontier defining a subspace of said space in which representation of a datum is associated with the detection of a fault.

Abstract: Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power state switchable between a power-on state and a power-off state. The logic design is traversed to analyze driver and load logic of each of the primary inputs to the switchable power domain to identify any pure pass-through nets each of which has no driver and no load logic in the switchable power domain.

Abstract: A computer system for converting a computer aided design drawing file of an electrical power system into one or more component objects for power analytic analysis and simulation, is disclosed. The computer system can include a processor, a memory, a display device, and an input device. The memory device can be coupled to the processor and configured to maintain a component classification database, an import engine, computer aided design drawing parser, and a symbol classification engine. The display device can be coupled to the processor and configured for displaying the computer aided design drawing file of the electrical power system.

Abstract: A computing device simulates a test system by defining parameter values to be used to populate certain modeling formulas defining the test system. The defined parameter values correspond to one of the many points defining a domain in which the test system is to be simulated. The simulation iteratively solves the modeling formulas for each unit of the test system model space for each point in the domain in which the test system is simulated. Results for the subjects of interest are calculated at each iteration using the populated modeling formulas. A variance of the subjects of interest is also calculated at each iteration using a correlation coefficient obtained for the subjects of interest. The iterations of defining the parameter values and calculating the value and variance of the subjects of interest in the test system model space continues until all points in the domain have been simulated.

Abstract: A mechanism to dynamically vary the amount of delay for an event-generated function call is discussed. The event causing the generation of the function call may be a signal-based event, function call event or some other type of event. A function call generating delay component is inserted into a DES model and dynamically adjusts the amount of delay to apply prior to generating and transmitting the function call to an intended target component. The function call generating component reads a value from an input port in determining the amount of delay. The identified value at the input port may be a signal value or an attribute associated with an event entity received at the port.

Abstract: Described herein is a method for optimizing a prediction of resource usage of an application running in a virtual environment, comprising: providing a predetermined set of benchmarks, wherein the predetermined set of benchmarks; executing the predetermined set of benchmarks in a native hardware system in which the application natively resides; executing the predetermined set of benchmarks in the virtual environment; collecting first traces of first resource utilization metrics in the native hardware system based on the execution of the predetermined set of benchmarks in the native hardware system; collecting second traces of second resource utilization metrics in the virtual environment based on the execution of the predetermined set of benchmarks in the virtual environment; generating a first prediction model and a second prediction model; generating a third prediction model that maps all of the first traces of the selected first metric to the second traces of resource utilization metrics; comparing the firs

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: This invention is directed to a circuit simulation using multi-rate harmonic balancing. Specifically, this invention enables effective reduction of analysis dimensions, e.g. frequency or time. The methodology converts N-dimensional problems to local (N-x)-dimensional problems. The method enables simultaneous solving of all local problems, each of these problems having a dimension less than or equal to N, thus approximating the original system to be solved. In practical situations, N could be the number of independent frequencies in an N-tone harmonic balance analysis.

Abstract: Nodes interconnected by a network have their substantially parallel execution simulated. Substantially parallel execution of the nodes during a current quantum of simulation time having a quantum length is simulated. Simulation of execution can result in simulation of inter-node data packets being transmitted over the network. When the current quantum of simulation time has elapsed, simulation of execution of the nodes is synchronized. If no inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is increased. If one or more inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is decreased. This process is then repeated for a next quantum of simulation time having the quantum length as has been increased or decreased.

Abstract: Provided is a method for modeling an ESD breakdown current. According to one variation, a first proportional constant is based on a circumference of the ESD protection device and a second proportional constant based on an area of the ESD protection device. A dual first order equation is derived by sampling circumferences and areas of two ESD protection devices. According to another variation, an equation is defined in which a third value (an ESD breakdown current) is a sum of a first value and a second value, the first value being obtained by multiplying a circumference of an ESD protection device by a first proportional constant, the second value being obtained by multiplying an area of the ESD protection device by a second proportional constant. Then, circumferences and areas of first and second ESD protection samples are calculated. Next, first and second equations are derived by reflecting the first and second circumferences and areas to the equation.

Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

Abstract: A network system can have a plurality of distributed software agents configured to collect events from network devices. In one embodiment, the agents are configured to aggregate the events. In one embodiment of the present invention, an agent includes a device interface to receive an event from a network device, a plurality of aggregation profiles, and an agent aggregate module to select one of the plurality of aggregation profiles, and increment an event count of an aggregate event representing the received event using the selected aggregation profile.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. In particular, the techniques and systems relate to design instrumentation circuitry that facilitates the analysis, diagnosis and debugging of the hardware designs. A HDL design instrumentation circuitry embedded within an electronic system comprises one or more probe circuits to allow storage of signal values of the electronic system upon predetermined events, one or more breakpoint registers to specify the predetermined events, and one or more trigger processing units to control the storage of signal values upon the detection of the predetermined events by the breaking registers. The present design instrumentation circuitry permits monitoring the electronic system at speed, facilitating the analysis diagnosis and debugging by giving detailed and accurate information about the operation of the electronic system.

Abstract: A packet delay variation simulation system has a packet generator, a packet delay variation generator, and a packet delay analyzer to analyze delayed packets. The packet delay variation generator has multiple delay distribution modules that use both a deterministic delay process and a statistical delay process packet for determining a packet's delay. The packet delay variation generator may utilize different probability density functions to describe various portions of measured packet data. That is, measured packet delay information is analyzed and information from this analysis is used to construct a total delay model for a network. The delay may include a pre-determined deterministic delay offset as well as one or more variable statistical delay offsets.

Abstract: In one embodiment, a system model models characteristics of a real-world system. The system model includes a plurality of sub-portions that each correspond to a component of the real-world system. A plurality of test vectors are applied to the system model and coverage achieved by the test vectors on the sub-portions of the system model is measured. In response to a failure of the real world system, a suspected failed component of the real-world system is matched to a particular sub-portion of the system model. A test vector to be applied to the real-world system to test the suspected failed component is selected in response to coverage achieved on the particular sub-portion of the system model.