Event-driven Patents (Class 703/17)
  • Patent number: 6775809
    Abstract: A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: August 10, 2004
    Assignee: Rambus Inc.
    Inventors: Frank Lambrecht, Ching-Chao Huang, Michael Fox
  • Patent number: 6766311
    Abstract: An interactive computer-based training (ICBT) system operable over a computer network for training users. The ICBT system is provided with inter-dependent, state-machine-based hardware and software simulators for emulating hardware and software functionality associated with a piece of equipment on which the users are to receive interactive training. The state transition method effectuated in a computer-readable memory system includes the steps of: identifying a current state of the state machine wherein a transition is to be effectuated; determining if there is a state immediately prior to the current state, and if so, determining whether there is a dependency of the current state on the immediately prior state, the dependency being characterized as a first order dependency; inferring a reference value associated with the current state based on the first order dependency; and determining a future state of the state machine based on the inferred reference value.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: July 20, 2004
    Assignee: WorldCom, Inc.
    Inventors: Robert S. Wall, Donald R. Warner, Jackie R. Closson, Patrick J. Doggett
  • Publication number: 20040133535
    Abstract: Event positioning and detection system and methods which can determine an event epicenter based on tangential relationships between a plurality of sensors and the waveform created by the event as it occurs and is detected in a medium.
    Type: Application
    Filed: August 1, 2003
    Publication date: July 8, 2004
    Applicant: Tangent Research Corporation
    Inventors: Peter Hans Scharler, Jason Thomas Winters
  • Publication number: 20040117170
    Abstract: A simulator running on a single computer may be configured to appear as one or more users simultaneously initiating Internet requests from separate user environments using a plurality of different authentication methods. An engine of the simulator may communicate with a browser to appear as one or more users each having access to a local defined user account and initiating Internet requests using the plurality of different authentication methods. The simulator may be configured to maintain different user profile data for each user appearing to operate within a separate user environment. The simulator may be configured to appear as one or more separate users initiating Internet requests using a plurality of different authentication methods from multiple, different user environments.
    Type: Application
    Filed: December 13, 2002
    Publication date: June 17, 2004
    Inventors: Robert E. Walsh, Michael P. Shea
  • Patent number: 6751583
    Abstract: A co-simulation design system to simulate on a host an electronic system that includes target digital circuitry and a target processor with an accompanying user program. The system includes a processor simulator to simulate execution of the user program by executing host software that includes an analyzed version of the user program. The system further includes a hardware simulator to simulate the target digital circuitry and an interface mechanism that couples the hardware simulator with the processor simulator. The user program is provided in binary form. Determining the analyzed version of the user program includes decomposing the user program into linear blocks, translating each linear block of the user program into host code that simulate the operations of the linear block, storing the host code of each linear block in a host code buffer for the linear block, and adding timing information into the code in the host code buffer on the time it would take for the target processor to execute the user program.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: June 15, 2004
    Assignee: VaST Systems Technology Corporation
    Inventors: Neville A. Clarke, James R. Torossian
  • Publication number: 20040098240
    Abstract: To handle non-determinism in a state machine model, different non-deterministic outcomes are represented in a system by ‘worlds’. A world represents the state, history and variable values result of event processing for every permutation occasioned by non-determinism. The system clones a world (233) so as to represent a sequence uniquely. When any two resultant worlds are identical, one is deleted (235). When plural worlds exist, the system accepts an event for processing and processes the event in all of the extant worlds (232, 234). The embodied system causes the generation and processing of a set of transition sequences based on fork and race-condition non-determinism for each extant world. The system allows permutation of set-transit actions, and generates additional worlds for each permutation. The system also allows for mid-transition-flight firing of additional events, which results in additional worlds in which the remainder of the transition algorithm is processed.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 20, 2004
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Graham G. Thomason
  • Patent number: 6738955
    Abstract: A method for characterizing average performance in a data processing system is provided. This method consists of adding meta-tool level variables to a verification tool. These meta-tool variables keep track, at once, of all concurrent streams of execution that the tool is considering in its reachability analysis. The image of an initial state variable is found and then divided into a frontier of new states and a set of previously reached states. The previously reached states are ignored and the image of the frontier is found. This process continues until the frontier is empty and all possible states have been reached. In one embodiment of the present invention, the probabilities of the paths can be considered by sampling and holding input data using SMV (a model checking tool) variables.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Flemming Andersen, Jason Raymond Baumgartner, Steven Leonard Roberts
  • Patent number: 6738737
    Abstract: An event sequencer for a functional mechanism contains a list of signatures and corresponding priority designations, and an event list containing event information from race condition events that are to be re-ordered. A method for sequencing race condition events, includes storing signatures for identifying predetermined events, storing priority designations corresponding to the signatures to enable identification of relative priorities between identified events, detecting at least first and second events and information about each event, storing only upon signature match the events and event information associated with each event, sorting the events, and sending the sorted events to a functional mechanism. Events are compared with stored signatures, and signature matches are determined. The arrival of events is detected, events are compared with stored signatures, and matches between events and signatures are established.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: May 18, 2004
    Assignee: Cirrus Logic, Inc.
    Inventor: Hamilton B. Carter
  • Publication number: 20040061595
    Abstract: A decision aid for use in the defense of a combat ground vehicle which includes a track fusion element, a threat typing element, threat prioritization element, and a countermeasures (CM) selection element.
    Type: Application
    Filed: January 6, 2003
    Publication date: April 1, 2004
    Inventors: Ronald M. Yannone, Howard B. Partin
  • Patent number: 6708328
    Abstract: A first system for analysis of a portion of a partial state space includes a representation component and an analysis component. The portion of the partial state space is related to a part of a second system. The representation component of the first system employs a value in the portion of the partial state space to represent that information for the part of the second system is unknown. The analysis component of the first system employs the value in the portion of the partial state space to analyze, in response to an analysis question that is related to the part of the second system, the portion of the partial state space.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: March 16, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Glenn R. Bruns, Patrice Ismael Godefroid
  • Publication number: 20040044513
    Abstract: A distributed simulation system of this invention performs simulation by use of a common facility where event-driven application programs loaded into a plurality of computers with a display unit connected to one another via a network assure information transfer between a plurality of objects existing in a distributed environment. The distributed simulation system comprises an user interface unit configured to receive an operation corresponding to the user's will, and an event notifying unit configured to notify the application programs of the user's operation given via the user interface unit as an event.
    Type: Application
    Filed: July 31, 2003
    Publication date: March 4, 2004
    Inventor: Noriaki Kitahara
  • Patent number: 6698004
    Abstract: The present invention provides a solution for converting a boundary scan description language (BSDL) file to a hardware verification language (HVL) test program file. The BSDL file is scanned for header information and the header information is stored in a header object. The BSDL file is then scanned for pin information, the pin information corresponding to at least one pin in the BSDL file having a pin location, and stored in a pin object. At least one variable for the HVL test program file is created and bound to one of the pin locations resulting in a binding relationship for each variable. The binding relationships are then stored in a bind object. The present invention is designed to overcome the disadvantages of the prior art.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: February 24, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Keshava I. Satish, Neil Korpusik
  • Patent number: 6694290
    Abstract: A method of using a computer to analyze an extended finite state machine model of a system includes receiving at least one requirement expression, determining at least one path of states and transitions through the model, evaluating at least one of the requirement expressions based on at least one of the determined paths through the model to determine whether the path satisfies the requirement expression, and generating a report based on the evaluating.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: February 17, 2004
    Assignee: Empirix Inc.
    Inventors: Larry Apfelbaum, Peter L. Savage, Katrin Bell
  • Patent number: 6691080
    Abstract: An average cache hit ratio and execution time not considering any interrupt are obtained by processes (1001-1011). A section hit ratio simulation (2006a) is done using the obtained information, interrupt generation probability information (2005), and cache scheme/cache size information (2004). A stall penalty (2008) is added to the obtained trace information (D) to attain the number of execution clocks, and the cache hit ratio and execution time are estimated. An average cache hit ratio and execution time considering an interrupt can be obtained.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayoshi Tachibana
  • Publication number: 20040024578
    Abstract: Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performances on the Closed Queuing Network (CQN) simulation are compared with each other. Lookback can be used to reduce the rollback frequency in optimistic simulations. The relation between lookahead and lookback is also discussed in detail. Finally, it is shown that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.
    Type: Application
    Filed: May 13, 2003
    Publication date: February 5, 2004
    Inventors: Boleslaw K. Szymanski, Gang Chen
  • Patent number: 6681264
    Abstract: A system and method for determining whether a set of message sequence charts (MSCs) is realizable or safely realizable in an implementation is provided. The determination is made by analyzing the set of MSCs for the existence of unspecified, implied MSCs. If the set of MSCs can be realized in a deadlock-free automaton, then the set of MSCs is safely realizable. If the set of MSCs is realizable (no implied MSCs exist), a state machine can be synthesized from the set of MSCs. If the set of MSCs is not realizable, then implied, unspecified (partial) MSCs are produced. Also, given an undesirable MSC, the system determines whether the set of required MSCs implies the given undesired MSC.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: January 20, 2004
    Assignee: Lucent Technologies Inc.
    Inventors: Rajeev Alur, Kousha Etessami, Mihalis Yannakakis
  • Patent number: 6678643
    Abstract: A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: January 13, 2004
    Assignee: Advantest Corp.
    Inventors: James Alan Turnquist, Shigeru Sugamori, Hiroaki Yamoto
  • Patent number: 6678645
    Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: January 13, 2004
    Assignee: Advantest Corp.
    Inventors: Rochit Rajsuman, Hiroaki Yamoto
  • Patent number: 6675139
    Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Mark W. Jetton, Richard A. Laubhan, Richard T. Schultz
  • Patent number: 6668337
    Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Miwaka Takahashi, Akira Motohara, Osamu Ogawa
  • Patent number: 6668203
    Abstract: A state machine model analyzes sensor data from dynamic processes at a facility to identify the actual processes that were performed at the facility during a period of interest for the purpose of remote facility inspection. An inspector can further input the expected operations into the state machine model and compare the expected, or declared, processes to the actual processes to identify undeclared processes at the facility. The state machine analysis enables the generation of knowledge about the state of the facility at all levels, from location of physical objects to complex operational concepts. Therefore, the state machine method and apparatus may benefit any agency or business with sensored facilities that stores or manipulates expensive, dangerous, or controlled materials or information.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: December 23, 2003
    Assignee: Sandia Corporation
    Inventors: William R. Cook, John M. Brabson, Sharon M. Deland
  • Patent number: 6665848
    Abstract: A method for checking a model includes computing a succession of sets of the states of the system, beginning with an initial set of one or more initial states, such that the states in each of the sets are reachable by a successive cycle of a transition relation of the system from the states in a preceding set. One or more of the sets in the succession are selected to be saved in a memory, while the sets not selected are discarded. When an intersection is found between one of the sets in the succession and a target set, a trace is computed from one of the target states in the intersection through the states in the sets in the succession, including the discarded sets, to one of the initial states, using the sets saved in the memory to reconstruct the discarded sets.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: December 16, 2003
    Assignee: International Business Machines Corporation
    Inventors: Shoham Ben-David, Leonid Glukhovsky
  • Patent number: 6665632
    Abstract: First, the assembly population of the probability distribution of the mounting state of each part (within the initial setting range of assembly tolerance) is generated using the Monte-Carlo method. Then, an individual group that meets the design specification designated by a user is detected and the initial setting of the assembly tolerance is modified using the individual group. In this case, sensitivity indicating the modification of the assembly tolerance of which part is the most efficient can also be calculated/presented. Furthermore, how much the modification amount should be can also be calculated/presented.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: December 16, 2003
    Assignee: Fujitsu Limited
    Inventors: Yuichi Sato, Masayoshi Hashima
  • Publication number: 20030225561
    Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.
    Type: Application
    Filed: March 12, 2003
    Publication date: December 4, 2003
    Applicant: Broadcom Corporation
    Inventors: Luis Garcia, Russell E. Vreeland, Christopher B. Novak, Gabriel G. Marasigan, Christopher A. Roussel
  • Publication number: 20030225560
    Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.
    Type: Application
    Filed: March 12, 2003
    Publication date: December 4, 2003
    Applicant: Broadcom Corporation
    Inventors: Luis Garcia, Russell E. Vreeland, Christopher B. Novak, Gabriel G. Marasigan, Christopher A. Roussel
  • Patent number: 6658633
    Abstract: Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Devins, James R. Robinson
  • Patent number: 6654934
    Abstract: A device for executing an event thread. The device has programmable logic for storing data to define a number of states in an event thread to be executed in the event engine. The device also has execution logic coupled to the programmable logic. The execution logic is configurable to execute the current state and re-configurable to execute the next state, in response to data from the programmable logic. In this fashion, the next state may be executed by re-configuring the execution logic. The device also has transition logic coupled to the programmable logic. The transition logic causes the next state in the event thread to be entered by loading new data from the programmable logic. Therefore, the execution logic is re-configurable during execution of the event thread.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 25, 2003
    Assignee: Cyrpess Semiconductor Corporation
    Inventors: Craig Nemecek, Steve Roe
  • Publication number: 20030208349
    Abstract: A method for minimizing event scheduling overhead in VHDL simulation were proposed, and the speed-up of the VHDL simulation time can be obtained. It consists of the two ideas. The first idea excludes any events that do not have any effects on VHDL simulation. The second idea is grouping multiple homogeneous events, and treating them as a single event to reduce the burden of scheduling in the simulation. These idea were applied separately as well as in a combined way.
    Type: Application
    Filed: May 3, 2002
    Publication date: November 6, 2003
    Applicants: ACAD, Corp.
    Inventor: Andy Huang
  • Publication number: 20030200072
    Abstract: A technique for distributed processing a partitioned model is provided based on tight functional coupling of multiple submodels of the model. The technique includes, in one embodiment, providing each submodel with a generic coupler to enable processing of the submodel on any simulator instance of any simulator. Submodels coupled with the generic couplers can be processed on the same or different computing units. The generic couplers facilitate communication between submodels through a common communication directory (CCD) by using functions of a generic coupler shared library. The generic couplers further use functions of the shared library to ensure integrity of data transmitted between submodels.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Applicant: International Business Machines Corporation
    Inventors: William K. Mellors, Marvin J. Rich
  • Publication number: 20030200073
    Abstract: A model is partitioned into a plurality of partitions to be processed by a selected number of processors. Since the partitions are substantially independent of one another, the policy employed in the mapping of the partitions to the processors is flexible. Further, in the case in which the model is a chip, at least a portion of the clock and maintenance logic of the chip is also partitioned and mapped to the selected number of processors.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Applicant: International Business Machines Corporation
    Inventors: Marvin J. Rich, William K. Mellors, Soon I. Joe
  • Patent number: 6634010
    Abstract: An improved ASIC design support system is described. In accordance with the ASIC design support system, it is possible to easily download the latest versions of a necessary library (or libraries) and a necessary simulator. The ASIC design support system includes a web server which receives a request of the customer including the specification of the ASIC he wants to design. The web server serves to generate and transfer to the customer a library (or libraries) or a simulator required for designing said ASIC and performing simulation thereof.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Ishigami, Takao Aoyagi, Hideki Taguchi
  • Publication number: 20030191869
    Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 9, 2003
    Applicant: International Business Machines Corp.
    Inventors: Derek Edward Williams, Carol Ivash Gabele, Wolfgang Roesner
  • Publication number: 20030191620
    Abstract: A method and system for tracking instances of a testcase execution event within a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a design entity list is generated within the HDL model, wherein the design entity list identifies all design entities instantiated within the HDL model. One or more instrumentation code modules are dynamically loaded into the simulation control program, wherein the instrumentation code modules generate and process testcase execution events associated with at least one of the identified design entities.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 9, 2003
    Applicant: International Business Machines Corp.
    Inventors: Derek Edward Williams, Carol Ivash Gabele, Wolfgang Roesner
  • Publication number: 20030191621
    Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include at least first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs.
    Type: Application
    Filed: January 30, 2003
    Publication date: October 9, 2003
    Applicant: International Business Machines Corporation
    Inventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
  • Publication number: 20030158720
    Abstract: Models in compositional state systems are reduced by defining a set of events of interest and defining a transitive effect machine for components in the model relative to the events of interest. A transitive effect machine for a given component is defined by determining the transitive effects of events in the given component on other components in the model. Transitive effect machines are defined relative to reduced versions of other components in the model. The transitive effect machines are defined by successive assumptions of the reduced versions of the other components in the model and successively defined approximations to the transitive effect machine.
    Type: Application
    Filed: August 24, 2001
    Publication date: August 21, 2003
    Applicant: Wayne Biao Liu
    Inventor: Wayne Biao Liu
  • Patent number: 6609229
    Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: August 19, 2003
    Assignee: O-In Design Automation, Inc.
    Inventors: Tai An Ly, Jean-Charles Giomi, Kalyana C. Mulam, Paul Andrew Wilcox, David Lansing Dill, Paul Estrada, II, Chian-Min Richard Ho, Jing Chyuarn Lin, Robert Kristianto Mardjuki, Lawrence Curtis Widdoes, Jr., Ping Fai Yeung
  • Patent number: 6584436
    Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: June 24, 2003
    Assignee: Vast Systems Technology, Inc.
    Inventors: Graham R. Hellestrand, Ricky L. K. Chan, Ming Chi Kam, James R. Torossian
  • Patent number: 6574665
    Abstract: A hierarchial vector clock (HVC) providing a logical time system to a collection of distributed systems. HVC is not restricted to any fixed number of hierarchy levels and scals naturally when the number of levels increases. Unlike constant-size clocks, its storage and processing requirements grow gracefully at approximately a logarithmic rate with the number of distributed sites within the distributed system. HVC is well suited for modern, message-passing distributed systems which make use of highly hierarchical communication networks.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: June 3, 2003
    Assignee: Lucent Technologies Inc.
    Inventor: Denis Andreyevich Khotimsky
  • Publication number: 20030101040
    Abstract: A hardware simulation and validation system is provided using a plurality of signal interface controllers to exchange stimulus and response signals with a hardware simulation. The action of the signal interface controllers is coordinated by a test scenario manager which exchanges test scenario controlling messages with the signal interface controllers. The test scenario controlling messages specify simulation actions to be performed and when those simulation actions are to be performed.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 29, 2003
    Inventor: Andrew Mark Nightingale
  • Patent number: 6571112
    Abstract: A method and apparatus for processing embedded messages at a mobile station including a subscriber identity module (SIM) identifying the subscriber, for example, a GSM or a non-GSM wireless telephone. The process includes receiving a message having a protocol identifier, transferring at least a portion of the message to the subscriber identity module if the protocol identifier satisfied a condition, extracting information from the at least portion to of the message at the subscriber identity module if a protocol identified by the protocol identifier is supported by the subscriber identity module.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: May 27, 2003
    Assignee: Motorola, Inc.
    Inventor: Satyanarayanan Ramaswamy
  • Patent number: 6564178
    Abstract: The present invention provides a method and apparatus for testing architectural compliance of processors wherein various types of cases requiring some structure can be simulated and a degree of randomness can be added to the case without destroying the structure of the case. The apparatus comprises a computer capable of being configured to execute a testing program. When the computer is executing the testing program, the computer generates instructions and simulates execution of the instructions in a processor. During simulation, the computer detects when simulation of an instruction has caused an event to occur in the processor. The computer identifies the event that has occurred and generates a list of atoms and stores the list in a memory device in communication with the computer. Each of the atoms in the list corresponds to a description of a particular event handler task to be performed by the processor in response to the occurrence of the event.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: May 13, 2003
    Assignee: Hewlett-Packard Company
    Inventor: Karl P Brummel
  • Patent number: 6560571
    Abstract: The present invention provides a method and apparatus for evaluating nodes in an integrated circuit to determine whether or not networks containing the nodes meet certain design criteria. The method and apparatus of the present invention are embodied in a rules checking system which evaluates the nodes in the integrated circuit to determine whether or not the networks in the integrated circuit comply with the design rules. Compliance with any particular rule is verified by performing one or more checks on the particular node being evaluated. Some checks require less time to perform than others. In some cases, the result of a single check can provide a determination as to whether or not the network containing the node being evaluated complies with the rule associated with the particular check. Furthermore, some checks are less expensive in terms of the amount of time required to perform them than other checks.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: May 6, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: John G McBride
  • Patent number: 6560572
    Abstract: A mixed-mode simulator for simulating a circuit containing an event-driven device with a plurality of pins. The mixed-mode simulator has a circuit simulator for simulating at least an analog portion of the circuit. The circuit simulator has a user-defined device modeling feature. The mixed-mode simulator has an event-driven device simulator and an interface between the circuit simulator and the event-driven device simulator. The interface has a parameter passing portion for receiving values from and returning values to the circuit simulator through the user-defined device modeling feature. The interface has a timing portion for instructing the event-driven simulator to run a simulation of the device based on the values for a given time period. The interface has a response reading portion for reading values of the pins at the end of the time period. Values are returned to the circuit simulator through the parameter passing portion and the user-defined modeling feature.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: May 6, 2003
    Assignee: Interactive Image Technologies, Ltd.
    Inventors: Anil P. Balaram, Rich Helms
  • Patent number: 6557149
    Abstract: A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: April 29, 2003
    Assignee: Intel Corporation
    Inventors: Matthew C. Morrise, Kenneth S. Stevens
  • Patent number: 6549882
    Abstract: Provided are test systems, methods, and media which allow a user to script any type of test or model scenario based on a particular type of network traffic (e.g., protocol interaction). In preferred embodiments, the script provides for the generation of packets (stimuli) which are used to provoke responses in order to model or test proper operation of one or more network protocols. The invention includes a scripting language, also referred to as a stimulus/response engine, which includes commands specifying a state change of a network device, and provides for the establishment of packet filters based on expected network traffic, receiving and matching arriving packets with packet filters, and, where there is a match, conducting actions specified by the user in the script. A stimulus/response engine (SRE) in accordance with the present invention is dynamic it that it accommodates patterns (packet filters) which are modified during test runs.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: April 15, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Huei-Ping Chen, Ting Chuan Tan
  • Patent number: 6513143
    Abstract: A computer implemented apparatus and method that automates the entry, modification, analysis, and generation of test benches from electrical circuits, both of which are specified as hardware description language (HDL) files. The computer implemented-method and apparatus also provides a unique mechanism that blends entry and display of timing requirements that must be met by the electric circuit.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: January 28, 2003
    Assignee: Xilinx, Inc.
    Inventors: Andrew Maurice Bloom, Rodrigo Jose Escoto
  • Patent number: 6510405
    Abstract: A method and apparatus for selectively displaying signal values generated by a logic simulator. Preferably, only those signal values that are relevant to a particular problem or event are displayed. The logic simulator itself may identify and display the selected signals, or a post-processor may read the list or trace window data provided by the simulator and identify and display the appropriate signals. In either case, the present invention may reduce the need to sift through large output listing and/or trace window data to identify the signal values that are relevant to a particular problem or event.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: January 21, 2003
    Assignee: Unisys Corporation
    Inventor: Roger Lee Gilbertson
  • Patent number: 6507809
    Abstract: A high-speed performance simulation method and system for simulating the performance of a large-scaled system such as a parallel computer. In implementation, the large-scaled system is divided into subsystems or partial units and the divided subsystems are simulated in parallel. Even when a particular partial unit occupies a shared resource, high-speed, well-coordinated performance simulation is achieved. A performance simulation system includes a plurality of performance simulators and an overall control section connected to these performance simulators. The plurality of performance simulators individually simulate the performances of partial units into which a simulant is divided. The overall control section causes the performance simulators to conduct the simulation processes alternately every AT cycle.
    Type: Grant
    Filed: April 8, 1999
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Taisei Yoshino, Isao Watanabe, Yoshiko Tamaki
  • Patent number: 6507807
    Abstract: The present invention provides a method and apparatus for determining the RC delays associated with branches of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. When the rules checker algorithm is executed, the algorithm analyzes information relating to the network and determines the total effective RC delays between the output of a driver gate of the network and the inputs of one or more receiver gates of the network.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: January 14, 2003
    Assignee: Hewlett-Packard Company
    Inventor: John G McBride
  • Patent number: 6496792
    Abstract: A method and apparatus for a transaction checking for system architecture validation are provided. Tracking data is received from trackers in the system. The tracking data is parsed to construct queues. These queues are compared with each other. For one embodiment, the queues are further compared with predicted behavior of the element that was tested. Discrepancies between the queues and the queue and predicted behavior are flagged.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: December 17, 2002
    Assignee: Intel Corporation
    Inventor: Eric J. Magnusson