Abstract: Methods and systems disclosed efficiently detect potential interactions between features in a telecommunications network. The methods and systems specify AIN (Advanced Intelligent Network) and switch-based features and detect their interactions when present within a feature package provided to a single subscriber. The methodology supports the assumption that each feature is created without the knowledge of other features, and that each feature is specified as a “black box,” i.e., nothing is known about its internal logic except its input/output behaviors. The invention models a call environment, models two or more features, and combines the call variable usage for each feature. Methods then compare the combined call variable usages to detect potential feature interactions.

Abstract: A verification of the protocol between the various communicating elements of a concurrent system may be performed directly using the actual code that implements the element when it is actually operating. This is achieved by combining stateless search techniques with partial order methods, namely, persistent set and sleep set methods. In particular, the code of each element of a system is exercised by a scheduler in such a way that global states of the system are visited according to a stateless search, which is a search that does not use an explicit representation of the global states. A global state is a state in which the next operation to be executed by every element of the system is a visible operation. The set of visible operations includes at least those operations related to communication between the elements.

Abstract: A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior.

Abstract: A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simulation results are identified and recorded along with the identified errors. Recorded error-specific data and transaction-specific data are then utilized to graphically display the simulation results such that individual transactions identified within the simulation results are graphically distinct and such that errors occurring during a transaction are visually identified with the transaction. Recording and displaying error information and raising the level of abstraction of simulation results from cycles and signals to transactions enables easier simulation analysis and debugging.

Abstract: A distributed discrete-event simulation system operable for processing time-stamped events in chronological order for simulating a multinode communications network, the simulation system comprising a plurality of subsystem platforms (SPs) operable for transmitting message packets to other SPs for simulating node to node communications; and a system controller coupled via a communication link to the plurality of SPs for controlling synchronization and message packet processing associated with the plurality of SPs; wherein when a time-stamped event is received by one of the SPs, the receiving SP responsive to the time-stamped event triggers execution of tasks associated with the time-stamped event in the other SPs via the message packets to provide parallel task processing for the particular time-stamped event among the plurality of SPs.

Abstract: A computer implemented method for simulating a resistive circuit, including a plurality of macro circuits that are arranged hierarchically. The method includes the steps of reading a netlist description of the resistive circuit and recursively traversing the resistive circuit starting from terminal nodes of a macro circuit at a highest level of hierarchy using precharacterizations of each of the plurality of macro circuits to determine node voltages and branch currents of the resistive circuit.

Abstract: A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred.

Abstract: A method and a system for generating a behavioral model for a device having a plurality of driver pins and receiver pins. The method and system includes connecting the plurality of driver and receiver pins to a test apparatus including an input stimulation means, a voltage measurement means, and a current measurement means, stimulating a first set of the plurality of receiver pins using the input stimulation means, performing voltage measurements at selected ones of the plurality of driver pins using the voltage measurement means, stimulating a second set of the plurality of receiver pins using the input stimulation means, performing current measurements at selected ones of the plurality of driver pins using the current measurement means, and creating the behavioral model using the voltage measurements and the current measurements.

Abstract: A method and apparatus for efficiently determining whether a set of constraints input to a verification tool are mutually contradictory or overconstraining. A set of constraints are mutually contradictory or overconstraining when they define values for system-model variables and/or inputs that are inconsistent with each other at a given state or group of states of a system-model state machine. It has been found that when a set of constraints assign inconsistent values at a given state or group of states of the system-model state space, the verification tool will treat the given state or group of states as a so-called non-returnable state. That is, the verification tool will not recognize any paths from the given state or group of states to a set of reset states.

Abstract: An arrangement for designing a testing modeling system provides a testing hierarchy, where non-standard device elements having internal memory and logic structures are modeled by partitioning the device element into a recognizable memory model and a recognizable logic model separate from the memory model. The segregated models are then verified for accuracy using existing design and simulation tool and with comparison to existing hardware implementations. Once the revised models have been verified, the new models can be stored in a model library for future use.

Abstract: In a circuit simulation method, circuit information of an electronic circuit to be simulated is inputted, and whether or not a linear circuit element circuit included in the electronic circuit is passive, is discriminated. For this discrimination, an inductance matrix of the electronic circuit is prepared, and, before a circuit analysis by a circuit simulator, whether or not the inductance matrix is a positive definite is discriminated by obtaining and checking the value of minor determinants of the matrix, and by determining that the circuit is passive if the values of the diagonal items in the matrix are positive definites, and that the circuit is not passive if at least one of the values of the diagonal items in the matrix is not a positive definite. In the latter case, from information of the minor determinants, additional information indicating a cause for non-passivity is derived and outputted.