Event-driven Patents (Class 703/17)
  • Patent number: 7266490
    Abstract: A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 4, 2007
    Inventor: Robert Marc Zeidman
  • Patent number: 7263478
    Abstract: An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 28, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takehiko Tsuchiya
  • Patent number: 7260794
    Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: August 21, 2007
    Assignee: Quickturn Design Systems, Inc.
    Inventor: Michael R. Butts
  • Patent number: 7257526
    Abstract: An efficient parallel event simulation method is implemented by simulating blocks of M edge events, where M is approximately equal to e logeN, and N being the number of interconnected processing elements. Following a simulation iteration, each processing element shares information with adjacent processing elements that relates to events that the processing elements simulated which may affect the simulation of events at the neighbor processing elements. When the communication reveals that the information that is shared by a neighbor processing elements is different from the information that the processing element assumed, then the arriving information is kept and the simulation process is repeated. In executing the repeated simulations of a block, the same random variable values are employed. When all of the processing elements find that the arriving shared information is the same as the information already known to the receiving processing element, simulation of the block ends.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: August 14, 2007
    Assignee: Lucent Technologies Inc.
    Inventors: Boris Dmitrievich Lubachevsky, Alan Weiss
  • Patent number: 7257524
    Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: August 14, 2007
    Assignee: Quickturn Design Systems, Inc.
    Inventors: William John Schilp, Pramodini Arramreddy, Krishna Babu Bangera, Makarand Yashwant Joshi
  • Patent number: 7246053
    Abstract: A method for transforming a behavioral specification involves converting the behavioral specification into a diagram representation, converting a delay from the diagram representation if the behavioral specification comprises a delay, generating a compliant cycle diagram from the diagram representation, and deriving a cycle equivalent behavioral specification from the compliant cycle diagram.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: July 17, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Mohamed Soufi, William K. Lam, Victor A. Chang
  • Patent number: 7246052
    Abstract: The system simulator comprises master simulators 1f, 1s, 2f and 2s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially actuating the master simulator and the slave simulator by using a function call and a thread manager S for actuating the master simulator by using a thread switching. When the master simulator activated by using the function call from the function manager accesses the slave simulator and an access blocking is caused, the master simulator controls the thread manager such that the master simulator is activated by using the thread switching carried out by the thread manager. Thus, it is possible to carry out the simulation at a high speed without getting into a dead lock state caused by the access blocking and without changing the simulator for simulating a conventional bus master.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: July 17, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Eiji Shamoto, Masahiro Fukuda
  • Patent number: 7246054
    Abstract: Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performances on the Closed Queuing Network (CQN) simulation are compared with each other. Lookback can be used to reduce the rollback frequency in optimistic simulations. The relation between lookahead and lookback is also discussed in detail. Finally, it is shown that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 17, 2007
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Boleslaw K. Szymanski, Gang Chen
  • Patent number: 7239993
    Abstract: A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7239995
    Abstract: A method includes simulating a token through a production process, the production process having a plurality of stages, determining whether the token may proceed from a first stage to a second stage in the production process, detecting event information as the token proceeds through the plurality of stages, and determining a root cause of a detected stall event based on the event information.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 3, 2007
    Assignee: Intel Corporation
    Inventors: Anat Shemer, Alex Reicher
  • Patent number: 7236918
    Abstract: In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instrumentation entities monitor logical operation of one or more of the plurality of design entities during simulation for occurrence of events of interest. In response to the indication, the compiler determines by reference to a bill-of-materials of a previously compiled file whether or not the previously compiled file was compiled with instrumentation entities compatible with the desired set of instrumentation entities. In response to determining that the previously compiled file was compiled with compatible instrumentation entities, the compiler compiles the simulation model of the digital design utilizing the previously compiled file in accordance with the indication.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7236919
    Abstract: A method for modeling a circuit layout to determine behavior responsive to a radiation event is set forth. The method includes identifying a first portion of the circuit layout that includes at least one body region of a MOS transistor in the circuit layout, the at least one region having a width substantially equal to that of the MOS transistor. A first model corresponding to the first portion of the circuit layout is selected. A second portion of the circuit layout that includes at least a first region within a drain of the MOS transistor in the circuit layout is identified and an appropriate second model corresponding to the second portion of the circuit layout is selected, wherein the at least one second model includes at least one parasitic bipolar transistor.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: June 26, 2007
    Assignee: Honeywell International Inc.
    Inventor: David E. Fulkerson
  • Patent number: 7231338
    Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: June 12, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Carl Cavanagh, Steven A. Sivier, Carl B. Frankel, James P. Freyensee
  • Patent number: 7228262
    Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: June 5, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Anzou, Chikako Tokunaga, Takashi Matsumoto
  • Patent number: 7224689
    Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: May 29, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Jay R. Freeman
  • Patent number: 7219047
    Abstract: A sub-system is provided to a discrete event simulator (DES) to expedite simulation execution by first detecting a non-quiescent steady-state condition in the simulated system, and when the steady-state condition is detected, the simulator determines a state, and subsequently simulates the system at a skip-ahead time using this determined state, or a predicted state based on the determined state. Convergence analysis is used to determine whether the system is at, or approaching, a steady-state condition. This convergence skip-ahead process achieves faster analysis by avoiding the computation that would conventionally be required to simulate the system behavior during the time interval that is skipped.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 15, 2007
    Assignee: OPNET Technologies, Inc.
    Inventors: Alain Cohen, Pradeep K. Singh, Arun Pasupathy, Stefan Znam
  • Patent number: 7206732
    Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 17, 2007
    Assignee: International Business Machines Corporation
    Inventors: Derek Edward Williams, Carol Ivash Gabele, Wolfgang Roesner
  • Patent number: 7203631
    Abstract: Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, e.g., VLSI designs, of processors, circuits and logical systems. Embodiments of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: Ranan Fraer, Osnat Weissberg, Amitai Irron, Gila Kamhi, Marcelo Glusman, Sela Mador-Haim, Moshe Y. Vardi
  • Patent number: 7203632
    Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: April 10, 2007
    Assignee: Xilinx, Inc.
    Inventors: Roger B. Milne, L. James Hwang, Jeffrey D. Stroomer, Nabeel Shirazi, Haibing Ma, Jonathan B. Ballagh
  • Patent number: 7194400
    Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: March 20, 2007
    Assignee: International Business Machines Corporation
    Inventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7191111
    Abstract: Dynamic cosimulation is implemented using a cosimulation bridge for data exchange between a primary simulator and a secondary simulator, and a plurality of user selected optimization control signals defined over the cosimulation bridge. At least one user selected optimization control signal is identified for disabling the cosimulation bridge. The primary simulator and secondary simulator are dynamically disengaged for ending data exchange responsive to disabling the cosimulation bridge. Responsive to optimization control signal going inactive, the primary simulator and secondary simulator are dynamically re-engaged for data exchange. The optimization control signals include a single sided disable; a two independent disable; a functional OR disable; a functional AND disable, and suspend signals. The single sided disable and the two independent disable enable disabling one side of the cosimulation bridge and not the other side.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventor: Raymond Walter Manfred Schuppe
  • Patent number: 7181383
    Abstract: A system for simulating a circuit having hierarchical data structure includes a simulator module having one or more computer programs for 1) creating a static database in accordance with a netlist description of the circuit, where the static database contains topology information of the circuit; 2) selecting a group circuit for simulation, where the group circuit contains one or more leaf circuits selected from the first branch and the second branch; 3) creating a dynamic database for representing the group circuit, where the dynamic database includes references to the static database for fetching topology information dynamically during simulation; and 4) simulating the group circuit in accordance with the dynamic database. Since the system duplicates and reproduces only the relevant dynamic information when necessary, the disclosed circuit simulator uses less memory and produces better performance.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 20, 2007
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bruce W. McGaughy, Prashant Karhade, Jaideep Muhkerjee, Jun Kong
  • Patent number: 7167821
    Abstract: A performance prediction simulator gives effect to the resource contention among multiple resources in a simulated system by adjusting event durations appropriately. A resource topology tree defining the resource configuration of the system is input to the simulator. The simulator includes an evaluation engine that determines the amount of resource used during each simulation interval of the simulation and records the resource usage in a resource contention timeline, which can be displayed to a user. The amount of resource used during a simulation is also used to adjust the event duration calculations of the hardware models associated with each event.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 23, 2007
    Assignee: Microsoft Corporation
    Inventors: Jonathan C. Hardwick, Efstathios Papaefstathiou
  • Patent number: 7162404
    Abstract: A configuration database associated with a digital design stores at least one data structure defining a Dial instance and a mapping between each possible input value of the Dial instance and a respective output value. The output value controls which of a number of different possible latch values is placed in a configuration latch to configure a functional portion of a simulation model of the digital design. The configuration database further indicates an association between the Dial instance and the configuration latch. In response to a request specifying an input value for the Dial instance, the data structure in the configuration database is accessed to determine an output value for the Dial instance based upon the mapping. In addition, a latch value for the configuration latch is obtained based upon the output value and the association indicated by the configuration database. The latch value is then utilized to set the configuration latch in the simulation model.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: January 9, 2007
    Assignee: International Business Machines Corporation
    Inventors: Bryan Ronald Hunt, Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7162405
    Abstract: A method includes creating a network model that includes a plurality of objects that represent assets in a real world system at real world times. The network model is displayable by a geographic information system. A first object is entered in the network model. The first object is associated with a first creation date and a first expiration date at first and second real world times, respectively. A second object is entered in the network model. The second object is associated with a second creation data and a second expiration date at third and fourth real world times, respectively. A system clock in the network model is set to a fifth real world time that is between the first and third real world times. Displaying the first object and any additional objects in the network model that represent assets present in the real world system at the fifth real world time.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: January 9, 2007
    Assignee: CertaLogic, Inc.
    Inventors: Alejandro Javier Spiritoso Mc Cabe, Sebastián César Maruffo
  • Patent number: 7158924
    Abstract: A method and system for tracking instances of a testcase execution event within a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a design entity list is generated within the HDL model, wherein the design entity list identifies all design entities instantiated within the HDL model. One or more instrumentation code modules are dynamically loaded into the simulation control program, wherein the instrumentation code modules generate and process testcase execution events associated with at least one of the identified design entities.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: January 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Derek Edward Williams, Carol Ivash Gabele, Wolfgang Roesner
  • Patent number: 7158925
    Abstract: Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the network on latch boundaries. Thus, management aspects of the simulation, such as management associated with the global simulation time, are simplified.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: January 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Marvin J. Rich, William K. Mellors
  • Patent number: 7155379
    Abstract: A component, system and method for simulation of a PCI device's memory-mapped I/O register(s) are provided. The PCI simulation component has an initialization component, a configuration space simulator and a memory-mapped I/O space simulator. The initialization component can claim an amount of memory by modifying the amount of memory that an operating system has available to it. The initialization component further identifies to the operating system that at least some of the claimed memory resides on a PCI bus. The configuration space simulator causes the operating system to accept that the simulated PCI device is present in the system. The memory-mapped I/O space simulator simulates device and can comprise can comprise a thread that monitors the simulated memory-mapped I/O registers for a change in order to simulate behavior of the simulated PCI device.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 26, 2006
    Assignee: Microsoft Corporation
    Inventors: Jacob Oshins, Brandon Allsop
  • Patent number: 7152025
    Abstract: A method is provided to automatically identify noise events in a channel of a communication system comprising the steps of: receiving an input signal from the channel; determining the mean energy of the input signal; determining the recent energy of the input signal; identifying a beginning of the noise event when the recent energy is greater than the product of the mean energy and a predefined first threshold; identifying an end of a noise event when the recent energy is less that the product of the mean energy and a predefined second threshold; and providing for output the beginning of the noise event and the end of the noise event. Other systems and methods are disclosed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: December 19, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Itay Lusky, Daniel Wajcer, Yosef Bendel, Yigal Bitran, Naftali Sommer, Ofir Shalvi, Zvi Reznic, Ariel Yagil, Eli Haim
  • Patent number: 7149675
    Abstract: A method for automatically mapping state elements between a first circuit and a second circuit is described. The method proceeds by comparing, in a structural phase, structural features of state elements in the first circuit to structural features of state elements in the second circuit for equivalence. Mappings between state elements of the first circuit and the second circuit are determined based on the comparison of structural features. “Don't care” input conditions are then accounted for prior to determination of functional features. During an inversion detection phase, the polarity of the mappings found in the prior structural phase are determined. A functional phase follows in which the functionality of state elements in the first circuit are compared to the functionality of state elements in the second circuit for equivalence using a three-valued random simulation and further mappings are determined based upon the functional comparison.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Yatin V. Hoskote, Kiran B. Doreswamy
  • Patent number: 7149676
    Abstract: The performance of a system is simulated in a method comprising: performing simulation in a first simulation mode for at least a first portion of code that models at least a portion of the system; and performing simulation in a second simulation mode for at least a second portion of code that models at least a portion of the system.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: December 12, 2006
    Assignee: Renesas Technology Corporation
    Inventor: Sivaram Krishnan
  • Patent number: 7146296
    Abstract: An acoustic modeling system and an acoustic modeling method use beam tracing techniques that accelerate computation of significant acoustic reverberation paths in a distributed virtual environment. The acoustic modeling system and method perform a priority-driven beam tracing to construct a beam tree data structure representing “early” reverberation paths between avatar locations by performing a best-first traversal of a cell adjacency graph that represents the virtual environment. To further accelerate reverberation path computations, the acoustic modeling system and method according to one embodiment perform a bi-directional beam tracing algorithm that combines sets of beams traced from pairs of avatar locations to efficiently find viable acoustic reverberation paths.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: December 5, 2006
    Assignee: Agere Systems Inc.
    Inventors: Ingrid B. Carlbom, Thomas A. Funkhouser
  • Patent number: 7143018
    Abstract: A method and system for minimizing redundancy in collected harvest event testcases from a batch simulation farm which includes a harvest testcase server that collects simulation data for a simulation model from at least one simulation client. In accordance with the method of the present invention, a testcase is executed on the simulation model within a simulation client. Responsive to the testcase triggering a harvest event, the harvest event is compared with a list of harvest events that have previously been triggered within the simulation model. In response to determining that the harvest event has not been previously triggered within the simulation model, the testcase is delivered to the harvest testcase server.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 28, 2006
    Assignee: International Business Machines Corporation
    Inventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7143023
    Abstract: A method and system and computer program product for automatically creating computer simulations or analyses of signal transfers of a circuit or system design are disclosed. A description of a physical design of a circuit or system is provided. The physical design has physical components and at least one of the physical components may transfer a signal to at least one other physical component. The physical design description includes an identification of the physical components and information descriptive of physical inter-connectivity among the physical components. A signal transfer description is provided for at least one signal transfer. The signal transfer description includes a set of source nodes and a set of receiver nodes. The set of source nodes provide the signal to be transferred and the receiver nodes receive the signal transferred from the corresponding set of source nodes. Each node is described by information associated with physical components.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: November 28, 2006
    Assignee: Signal Integrity Software, Inc.
    Inventors: Barry S. Katz, Walter M. Katz
  • Patent number: 7136796
    Abstract: An exemplary method and system for generating integrated circuit (IC) simulation information regarding the effect of design and fabrication process decisionn includes creating and using a data store of profile-based information comprising metrology signal, structure profile data, process control parameters, and IC simulation attributes. An exemplary method and system for generating a simulation data store using signals off test gratings that model the effect of an IC design and/or fabrication process includes creating and using a simulation data store generated using test gratings that model the geometries of the IC interconnects. The interconnect simulation data store may be used in-line for monitoring electrical and thermal properties of an IC device during fabrication. Other embodiments include utilizing a metrology simulator and various combinations of a fabrication process simulator, a device simulator, and/or circuit simulator.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: November 14, 2006
    Assignee: Timbre Technologies, Inc.
    Inventors: Nickhil Jakatdar, Xinhui Niu, Junwei Bao
  • Patent number: 7133818
    Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: November 7, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Keith H. Bierman, David R. Emberson, Liang T. Chen
  • Patent number: 7130785
    Abstract: A system and method for detecting accesses to non-existing hardware entities using a simulator environment. When an application running on a simulated target platform issues a transaction that involves accessing a hardware address, wherein the address is within a range of addresses allocated to a simulated hardware block, a set of instructions provided with the simulator are operable to determine if there exists a backing that corresponds to the transaction's address. If there is no backing (i.e., a control status register) associated with the address, an appropriate notification or warning is provided as a response.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: October 31, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Richard Shortz
  • Patent number: 7120569
    Abstract: The invention is a sequential machine for solving boolean satisfiability (SAT) problems for functions of n variables and m clauses in linear time with complexity O(m), independent of the number of variables in the function. With current hardware technology, a value of n=32 variables can be achieved. The machine can serve as a basic building block to develop faster SAT solvers.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: October 10, 2006
    Inventor: Javier Armando Arroyo-Figueroa
  • Patent number: 7117133
    Abstract: A system and method for designing photonic band gap structures. The system and method provide a user with the capability to produce a model of a two-dimensional array of conductors corresponding to a unit cell. The model involves a linear equation. Boundary conditions representative of conditions at the boundary of the unit cell are applied to a solution of the Helmholtz equation defined for the unit cell. The linear equation can be approximated by a Hermitian matrix. An eigenvalue of the Helmholtz equation is calculated. One computation approach involves calculating finite differences. The model can include a symmetry element, such as a center of inversion, a rotation axis, and a mirror plane. A graphical user interface is provided for the user's convenience. A display is provided to display to a user the calculated eigenvalue, corresponding to a photonic energy level in the Brilloin zone of the unit cell.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: October 3, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Chiping Chen, Michael A. Shapiro, Evgenya I. Smirnova, Richard J. Temkin, Jagadishwar R. Sirigiri
  • Patent number: 7111010
    Abstract: The present invention provides techniques for managing and analyzing business information. Specific embodiments provide persons with business or other non-technical fields with the capability to create, edit, and work with data models, profiles, and reports for business and other information. Specific embodiments can enable business and other non-technical users with enhanced understanding of information, and greater capabilities to manipulate relationships between various data entities in databases, for example.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: September 19, 2006
    Assignee: Hon Hai Precision Industry, Ltd.
    Inventor: Li-Wen Chen
  • Patent number: 7110934
    Abstract: The present invention provides a system and method for controlling a simulator to run a software simulation of a data processing system in order to generate simulated timing data indicative of performance of an unmodelled portion of the data processing system not modelled by the software simulation. The software simulation provides a timing accurate model of those parts of the data processing system other than the unmodelled portion. The method of the invention comprises inputting to a controller of the simulator real trace data obtained from execution of a program by the data processing system, the real trace data identifying the sequence of instructions executed by the data processing system, and associated timing data.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: September 19, 2006
    Assignee: ARM Limited.
    Inventors: Anthony Neil Berent, Paul Frederick D'Souza
  • Patent number: 7107202
    Abstract: A method apparatus for hardware and software co-simulation in ASIC development includes developing hardware and software concurrently and co-simulating the hardware and software therebetween via a network while the hardware and software are being developed. The method and apparatus for hardware and software co-simulation allows the software development and testing of hardware and software to start with the design of hardware so as to reduce an overall system development cycle involving ASICs.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Gopal Hegde, Surendra Rathaur, Miguel Guerrero, Anoop Hegde, Ilango Ganga, Amamath Mutt, Simon Sabato
  • Patent number: 7100132
    Abstract: A translator tool for translating simulation test data generated to test clock recovery circuitry of a device from an event-based format to a cycle-based format readable by integrated circuit testers is presented. The simulation test data includes test timing irregularities intentionally injected into a serial data signal that will be processed by the clock recovery circuitry of the device under test. The translator tool includes a normalization function that extracts the intentionally injected timing irregularities from the event-based test data and generates corresponding normalized event-based test data without the extracted timing irregularities. The translator tool includes a cyclization engine that cyclizes the normalized event-based test data to generate corresponding cycle-based test data without the timing irregularities.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: August 29, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Andrew S. Hildebrant, David Dowding
  • Patent number: 7099812
    Abstract: The disclosed invention is a grid that monitors a design simulation to support design verification coverage analysis. The disclosed invention includes n ordered axis declarations 72 that each correspond to a functional attribute and list at least two valid functional states, logic expressions 78 that test for the functional states and set axis variables, and a grid declaration 80 that converts the axis variables to a unique linear index value corresponding to the cross-product of the achieved functional states and records hits. The linear index is calculated by multiplying the integer value of each axis variable (except the nth axis variable) by the product of the sizes of each higher-order axis than the axis to which said axis variable corresponds, summing the results, and adding the integer value of the nth said axis variable.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: August 29, 2006
    Assignee: Intrinsity, Inc.
    Inventor: Fritz A. Boehm
  • Patent number: 7092868
    Abstract: A method and system for resolving testcase collection inconsistencies between a testcase list which includes testcases that have triggered harvest events within a simulation model, and a harvest hit table which records harvest events that have been triggered during simulation of the simulation model. First, the harvest hit table is updated from a simulation client to include a harvest event triggered by a testcase during simulation of the simulation model. The testcase is then collected within the testcase list. Finally, testcases identified within the testcase list are compared to testcases identified within the harvest hit table to determine inconsistencies therebetween.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7092866
    Abstract: A technique for applying time compression to simulate long-term execution of a software application in the short time frames includes providing simulated events to a software application under test and selectively advancing the system clock. The subject system utilizes two utility modules to interact with a software application under testing. The first module, the Event Simulation module, generates a range of predefine events which simulate the nature and frequency of events to which the software application would react. The second module, the Clock Modification module, intercepts the time signal generated by the operating system under which the software application is executing and modifies the clock signal, typically by advancing the time at a rate which is faster than one second per second, i.e., normal time rate. With the subject system, the behavior of an application over a simulated period may be observed in just a fraction of the simulated period duration, e.g.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventor: Vaughn T. Rokosz
  • Patent number: 7089517
    Abstract: A method for design validation of complex IC with use of a combination of electronic design automation (EDA) tools and a design test station at high speed and low cost. The EDA tools and device simulator are linked to the event based test system to execute the original design simulation vectors and testbench and make modifications in the testbench and event based test vectors until satisfactory results are obtained. The event based test vectors are test vectors in an event format in which an event is any change in a signal which is described by its timing and the event based test system is a test system for testing an IC by utilizing the event based test vectors. Because EDA tools are linked with the event based test system, these modifications are captured to generate a final testbench that provides satisfactory results.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: August 8, 2006
    Assignee: Advantest Corp.
    Inventors: Hiroaki Yamoto, Rochit Rajsuman
  • Patent number: 7085703
    Abstract: A method and system for providing centralized access to instrumentation count event information generated by simulation testing of a hardware simulation model, in which simulation testing is performed within a batch simulation farm by multiple simulation clients communicating with an instrumentation server. An entitylist that includes an identifier for each design entity within said hardware simulation model that has at least one instantiated instrumentation count event is generated within a simulation client. The entitylist is delivered from the simulation client to the instrumentation server. Within the instrumentation server, the entitylist is associated with an identifier for the hardware simulation model such that instrumentation count event information is accessible from said instrumentation server by individual design entity information.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Carol Ivash Gabele, Wolfgang Roesner, Derek Edward Williams
  • Patent number: 7085700
    Abstract: An improved method for debugging of analog and mixed signal behavioral models during simulation using Newton-Raphson iteration replay. The method according to the invention has substantially modified the prior art solution by limiting the interactive debugging steps in a replay of the last iteration of the accepted timepoints. Using this method, the user only interacts with the simulation during the iteration replay, and only for the accepted solution points. If the user is single stepping through this simulation, the simulator enters interactive mode at each statement during the replay. Similarly, if not single stepping, but a breakpoint has been triggered, the simulator enters the interactive mode at the appropriate statement to honor the breakpoint. While the iteration replay is performed, the system of equations does not need to be solved again. Instead, the solution vector is reinstated from the known solution of the last iteration.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: August 1, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donald J. O'Riordan, Richard Trihy
  • Patent number: 7076418
    Abstract: A method for system simulation, which is distinguished by a first sequence of steps for simulating a microcontroller/microprocessor and peripheral modules using predetermined signal patterns and by a second sequence of steps for interrogating and evaluating system states that are brought about by the simulation. In order to carry out the second sequence, the first sequence is interrupted as dictated by markers that have been inserted into the first sequence, and the second sequence is executed in an accelerated operational mode that has been adapted to the evaluation.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: July 11, 2006
    Assignee: Infineon Technologies AG
    Inventor: Albrecht Mayer