Abstract: A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of simulation results. A transaction is defined as a specific sequence of transitions on a selection or grouping of signals over a period of time where the signal activity has some higher level operational meaning. Simulation results are recorded on a transaction basis by storing standard simulation results information along with transaction-specific data elements, including the name of the transaction, the start time of the transaction, the end time of the transaction, and the interface on which the transaction takes place. Additional transaction-specific data elements may include parent and child relationships and predecessor and successor relationships between transactions.

Abstract: Exceptions allow a circuit designer, working with a circuit synthesis system, to specify certain paths through the circuit to be synthesized as being subject to non-default timing constraints. The additional information provided by the exceptions can allow the synthesis system to produce a more optimal circuit. A tag-based timing analysis tool is presented, which implements exceptions, and can be used in a synthesis system. A circuit is analyzed in “sections,” which comprise a set of “launch” flip flops, non-cyclic combinational circuitry and a set of “capture” flip flops. The tag-based static timing analysis of the present invention is performed in four main steps: preprocessing, pin-labeling, RF timing table propagation and relative constraint analysis. Preprocessing converts the exceptions written by the circuit designer into a certain standard form in which paths through the circuit to be synthesized are expressed in terms of circuit “pins.

Abstract: A transient analysis device in which a simulation executing unit uses a first net list produced by a net list producing unit to measure a settling time of an analog/digital mixed circuit to be analyzed, after a dummy pulse parameter setting unit sets a parameter of a dummy pulse based on the measurement result, the net list producing unit converts, into a net list, a transfer function of a new circuit obtained as a result of the addition of a dummy pulse generation circuit for generating a dummy pulse whose parameter has been set to the analog/digital mixed circuit, and the simulation executing unit executes transient analysis processing by using a second net list produced with respect to the new circuit.

Abstract: A simulator includes a timing simulation section executing timing simulation for a logic circuit of an electronic component, a time management section extracting logical operation time at an output terminal of the electronic component from a result of the simulation, a transmission line simulation section executing simulation of a transmission line connected to the output terminal from the logical operation time extracted by the time management section, and a simulation result processing section combining the result of the simulation by the timing simulation section and a result of the transmission line simulation by the transmission line simulation section.

Abstract: A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design.

Abstract: Delay-independent cycle-based logic simulation of synchronous digital circuits with levelized compiled code simulation has substantially increased speed. Sweep, eliminate, and factor reduce the number of literals. The use of cofactoring, a register allocation and spill scheme, an inverter minimization scheme, and retiming further reduce the simulation time for two and four valued simulation. A shift minimization scheme reduces time in four-valued simulation. The faster simulation is embodied in a method, a computer system, and a computer program product.

Abstract: A computer-aided logic circuit designing apparatus in which data on a plurality of circuits is stored in a database, the data on a plurality of circuits is read out therefrom and combined by a net list-RTL description combining section, a clock system portion is analyzed based on the logic circuit obtained by combining the data by a clock system analyzing section, and a result of the analysis is displayed by an analysis result display section correlating each type of clock system to a corresponding clock input element.

Abstract: A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components. The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circuit model. The hybrid circuit model is constructed by creating and integrating analog and behavioral models from the plurality of electrical components. The timing and noise effects remain accurate even at high printed circuit board/multi-chip module clock speeds, thereby ensuring that a user is able to construct an optimal design for any one of the plurality of electrical components.

Abstract: A time-frequency method and apparatus are disclosed for simulating the initial transient response of quartz oscillators. An original system of differential algebraic equations that characterize a quartz oscillator are reformulated using a system of well-defined partial differential equations (PDEs). The quartz oscillator is initially represented by a system of ordinary differential algebraic equations that are then reformulated using an artificial system of partial differential algebraic equations. The artificial system represents the behavior of the quartz oscillator with two artificial time axes, t1 and t2, at least one of which has periodic boundary conditions. The artificial system is solved numerically using an integration technique along a strip of the artificial system, defined by [0, T(t2)[×[0, ∞[. Thereafter, the time behavior of the signal is calculated from the numerical solution of the artificial system.

Abstract: A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system (600) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execution of the Static timing analysis, the predictability of clock signals is recognized and denoted in a timing model (616-622). Furthermore, an actual logical function of the clock circuit is determined during execution of the static timing analysis to provide more precise knowledge of the rise and fall times of the signals provided to the clock circuit.

Abstract: A system and method for generating design constraints for a logic synthesized block from timing analysis of the block. A timing analysis of logic described in software is performed for each of various operating modes of a circuit in which the logic is used. Timing data is extracted from the timing analysis and used as design constraints in the synthesis of the logic for the block.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: The invention provides an apparatus and a method for accurately and rapidly estimating a performance of an integrated circuit in the design at a register transfer level. A parsing member converts an HDL description of the integrated circuit at the register transfer level into a representation by using parse trees, and a parse tree allocation member allocates elements of the integrated circuit to respective nodes of the parse trees. A trade-off estimation member predicts a minimum area which can satisfy a timing constraint by applying estimation models stored in an estimation library to the respective elements of the integrated circuit represented by using connections between the elements, and by appropriately changing application of driver models stored in a driver library.

Abstract: Methods and apparatus are described for generating circuit parameters for a plurality of interconnect line circuit models. The plurality of circuit models represent a plurality of interconnect lines in a programmable logic device (PLD). Design description data corresponding to the PLD are generated at least in part from spreadsheet representations of the plurality of interconnect lines. A device model for the PLD is generated using estimated circuit parameters and a plurality of mathematical equations representing the plurality of interconnect line circuit models. Operation of the PLD is simulated using the device model and the design description data thereby generating modeled delay data corresponding to the estimated circuit parameters. The modeled delay data are compared with measured delay data corresponding to the plurality of interconnect lines.

Abstract: A simulation model for a digital system comprises a number of functional units, interconnected by a number of interface units for transmitting messages between the functional units. Each interface unit includes a mechanism for automatically composing and decomposing messages into higher and lower levels of design. The interface thus provides a general mechanism which allows units at any level to communicate with units at any other level, for mixed-level modelling.

Abstract: A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation

Abstract: The present invention relates to a method and system for identifying tested path-delay faults in integrated circuits. A path status graph is generated to represent the detected status of simulated path-delay faults. The path status graph includes vertices representing primary inputs, primary outputs and elements of the circuit. Detected status path-delay faults can be dynamically distributed to edges of the path status graph. Tested path-delay faults can be identified from traversal of the edges of the path status graph.

Abstract: In the present invention, a method is provided for analyzing signal noise caused by cross-coupling between an attacker signal line, upon which an attacker signal resides, and a victim signal line, upon which a victim signal resides. This method comprises selecting the victim signal, selecting the attacker signal, performing cross-talk attacker filtering on a plurality of signal lines to identify a first set of potential attacker signals on a first set of potential attacker signal lines that cause signal noise upon said victim signal, performing safety window filtering on a plurality of signals signal lines to identify a second set of potential attacker signals on a second set of potential attacker signal lines that cause signal noise upon the victim signal line, and reducing the effects of the signal noise on at least one of the victim signal lines.

Abstract: When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

Abstract: Operation cycles to be subjected to an IDDQ test are selected from among operation cycles defined by a test pattern for a functional test of a CMOS integrated circuit so that a sufficient and necessary number of operation cycles are accurately and rapidly selected. A combination of sets of m-bit data are selected so that the combination includes sets of m-bit data each bit of which is changed from one of the values "0" and "1" to the other at least once. The operation cycles corresponding to the sets of m-bit data included in the combination are rendered to be the IDDQ test cycles to be subjected to the IDDQ test.

Abstract: In laying out the wiring of an LSI, PWB or the like, based on the logical connection information, layout result information, delay analyzing information or the like, the delay time margins for the entire path is evaluated by means of a delay analyzing means to detect a worst case path having the worst delay time margin from among the delay time margins for each path by means of a worst case path detecting means. A difference between the delay time margin of a secondary worst case path having the worst delay time margin among the next stage paths of this worst case path and the delay time margin of the preceding worst case path is evaluated by means of a clock skew adjusting time extracting means. Within the range of this clock skew adjusting time, an optimum delay time to be added is calculated by means of an additional delay time calculating means.

Abstract: A method and system for predicting the sensitivity of the integrated circuit logic cell timing performance to variations in voltage and temperature. Rather than using the prior art approach of multiplicative derating factors to model voltage and temperature effects on timing performance, adders are used to model the change in performance due to variations in operating conditions (i.e., voltage and temperature). The adders are treated as functions of input transition time (Tx) and output load capacitance (Cload). The change in performance as measured in time forms a plane over the Tx-Cload operating range for variations in either voltage or temperature. The adders, using a plane equation as a function of Tx and Cload, greatly improve the absolute accuracy in predicting the effects of variations in voltage and temperature, as compared to using the prior art methods involving multiplicative derating factors.

Abstract: A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.

Abstract: One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip.

Abstract: Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).

Abstract: In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

Abstract: In a circuit simulation method, circuit information of an electronic circuit to be simulated is inputted, and whether or not a linear circuit element circuit included in the electronic circuit is passive, is discriminated. For this discrimination, an inductance matrix of the electronic circuit is prepared, and, before a circuit analysis by a circuit simulator, whether or not the inductance matrix is a positive definite is discriminated by obtaining and checking the value of minor determinants of the matrix, and by determining that the circuit is passive if the values of the diagonal items in the matrix are positive definites, and that the circuit is not passive if at least one of the values of the diagonal items in the matrix is not a positive definite. In the latter case, from information of the minor determinants, additional information indicating a cause for non-passivity is derived and outputted.

Abstract: A processor performance evaluation system and method provides a method of model decomposition and trace attribution by first decomposing a full pipelined model of the entire system into a main model and one or more additional sub-models, such that it is possible to build fast trace-driven non-pipelined simulation models for the sub-models to compute specific metrics or values, which would be required during full-model, pipeline simulation. The main model is a fully pipelined model of the entire system; however, the simulation work required for the sub-units characterized by the sub-models is not coded into the simulation engine. Instead, the necessary values are provided from encoded fields within the input trace.

Abstract: A clock signal distribution circuit has a clock tree configuration. In the layout of the clock tree, a standard clock tree is prepared having a route buffer, a plurality of intermediate stage buffer cells and a plurality of last stage buffer cells connected in a hierarchical configuration. All of the clock lines have an equal length. If there are no set of flip-flops ina target integrated circuit corresponding to a set of last stage buffer cells, the set of last stage buffer cells are removed as a whole provided there is not other last stage buffer cells connected to a flip-flop.

Abstract: A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device. The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycles on a simulated hardware component. The system further includes a simulator library for modeling and verifying hardware components of a desired electronic device. The simulator library includes built-in models and routines for simulating multiple internal hardware components. The simulator library is used with the cycle-accurate simulator. The system also includes a simulation Application Program Interface ("API") for allowing user-customized model and routines of internal and external hardware components to be used with the cycle-accurate simulator. The system can be used to design, verify and develop on-chip and off-chip components for a system-on-a-chip used in a desired electrical device.