Timing Patents (Class 703/19)
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Publication number: 20080072197Abstract: A system and method for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.Type: ApplicationFiled: September 18, 2006Publication date: March 20, 2008Inventors: Yee Ja, Bradley S. Nelson
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Patent number: 7346481Abstract: Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.Type: GrantFiled: August 31, 2004Date of Patent: March 18, 2008Assignee: Xilinx, Inc.Inventors: Jonathan B. Ballagh, Roger B. Milne, Nabeel Shirazi, Jeffrey D. Stroomer
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Patent number: 7346483Abstract: To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.Type: GrantFiled: October 10, 2003Date of Patent: March 18, 2008Assignee: Synopsys, Inc.Inventors: Horia Toma, Thorsten Heiner Groetker, Srinivas Bongoni, Andrea Kroll
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Patent number: 7346861Abstract: Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.Type: GrantFiled: December 2, 2004Date of Patent: March 18, 2008Assignee: Altera CorporationInventor: Andy L Lee
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Publication number: 20080052651Abstract: There is provided a set of methods for generating state space models of general VLSI interconnect and transmission lines, trees and nets by closed forms with exact accuracy and low computation complexity. The state space model is built by three types of models: the branch model, the connection model and the non-connection model, that are block matrices in closed forms, arranged with topology. The main features are the topology structure, simplicity and accuracy of the closed forms of the state space models {A,B,C,D} or {A,B,C}, computation complexity of O(N) in sense of scalar multiplication times, where N is the total system order, practice of the modeling, ELO model simplification, and their optimization. For evenly distributed interconnect and transmission lines, trees and nets, the closed forms of state space model have the computation complexity of O(1), i.e., only a fixed constant of scalar multiplication times.Type: ApplicationFiled: August 8, 2006Publication date: February 28, 2008Inventor: Sheng-Guo Wang
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Patent number: 7325153Abstract: A method to obtain configuration data for a data processing apparatus by calculating (110) a time interval between the commencement of a mode (104) and a subsequent event (108). The calculated time interval is then compared (112) with one or more reference values (114). The result of the comparison is used to derive configuration data (116). The method may be further refined by including a calibration stage to reduce the error in the calculated time interval, thereby allowing comparison with a larger set of reference values (114), which in turn permits more configuration data to be derived from the calculated time interval.Type: GrantFiled: July 16, 2003Date of Patent: January 29, 2008Assignee: NXP B.V.Inventor: Alan J. Terry
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Patent number: 7324932Abstract: A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment in which the electronic device is to be tested. A virtual calibration of the virtual test environment may be performed, to more closely emulate the actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal that is applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated.Type: GrantFiled: June 28, 2005Date of Patent: January 29, 2008Assignee: Intel CorporationInventors: Sunil K. Jain, Gregory P. Chema
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Patent number: 7318016Abstract: A system and method for optimizing placement of network equipment and information load in a network over a period of time. A demand input structure having a plurality of demands organized by their time points is provided as an input to a model generator and an optimization processor associated therewith. Starting with the earliest demand set to be serviced by the network, a directed graph network model is obtained by using appropriate transformation techniques. A cost function associated with the network model is constructed using a flow cost term and an equipment cost term. Appropriate constraints are imposed on the cost function for optimization. A solution set comprising network placement information and demand routing information is obtained for a current time point. When the next demand set is taken up for optimization, the network model and associated cost function are recursively updated by using the solution set obtained for the demand set at a prior time point.Type: GrantFiled: February 17, 2004Date of Patent: January 8, 2008Assignee: Verizon Business Global LLCInventors: Kristen L. Watkins, Nandagopal Venugopal
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Patent number: 7315806Abstract: A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there are negative constraints in logic elements. In one example embodiment, the technique adjusts negative timing constraints by grouping the timing constraints based on associated output terminals in a digital logic circuit. The NCC is then applied to each grouped constraint to correct for path delays and resulting timing inaccuracy during an event driven simulation.Type: GrantFiled: May 20, 2004Date of Patent: January 1, 2008Assignee: Texas Instruments IncorporatedInventors: Abdul MJ Muthalif, Raghavendra N Rao, Javaji Sunil Babu
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Patent number: 7315805Abstract: A discrete event simulation (DES) and method of model development provide affordable, accurate, pre-validated, reusable and portable models and simulations that capture the complexity, interdependencies and stochastic nature of the operations and support (O&S) of weapons systems. A model of the O&S problem is created based on a service use profile (SUP) that describes a logical structure of delivery, maintenance, deployment, testing policy, infrastructure and logistics constraints. That model is translated into a DES, preferably using a “toolkit” including common attributes for the weapons and pre-validated common blocks and sub-models that define higher level functionality. The DES calculates a time-based prediction of weapons availability, maintenance activities, and spare parts stock over a life cycle of the weapons system.Type: GrantFiled: February 5, 2004Date of Patent: January 1, 2008Assignee: Raytheon CompanyInventor: Robert D Slater
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Patent number: 7313511Abstract: Virtual Real Time (VRT) provides high fidelity timing for software simulator environment running in a workstation. VRT is scalable and controllable. VRT provides flight and simulation software synchronization mechanism. This feature guarantees that the causality effect between flight software when interacting with simulated devices is the same as running flight software in a real test-bed environment. VRT provides high-resolution timing, which facilitates monitoring and detection of timing related faults while running the simulation software system on a workstation. VRT is modularized, such that the switchover from virtual clock to real clock is a trivial task. Running the system on a workstation using VRT behaves exactly like a real system, with the added benefits of user controllable features such as start, stop, monitor and time-scale. Performance of systems running with VRT is generally very good, equal to or better than the hardware, as the software runs natively on a faster workstation.Type: GrantFiled: August 6, 2003Date of Patent: December 25, 2007Assignee: California Institute of TechnologyInventors: Mohammad Shahabuddin, William K. Reinholtz
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Patent number: 7302378Abstract: An ESD protection device modeling method of modeling an electrical characteristic of an electrostatic discharge (ESD) protection device for simulating a circuit that include the ESD protection device, comprising the steps of (114) setting a parameter of at least one specific element that affects the electrical characteristic of the ESD protection device; and (116) modeling the electrical characteristic of the ESD protection device with the parameter of the specific element.Type: GrantFiled: September 3, 2004Date of Patent: November 27, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Hirokazu Hayashi
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Patent number: 7299438Abstract: A timing verification apparatus calculates a pulse width variation coefficient based on a pulse width of an input clock signal, a delay value of the clock signal, and an operation frequency. The apparatus then calculates the pulse width for a delayed clock signal provided to a clock input terminal of a flip flop (FF) using the pulse width variation coefficient. Further, the apparatus compares the calculated pulse width with a standard value. The timing verification apparatus calculates the pulse width of the delayed clock signal provided to the clock input terminal of the FF using the pulse width of the clock signal, and a rise delay and a fall delay of the path. The apparatus considers on-chip variations and accurately executes timing verification for signals.Type: GrantFiled: March 16, 2005Date of Patent: November 20, 2007Assignee: Fujitsu LimitedInventor: Toshikatsu Hosono
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Patent number: 7299437Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.Type: GrantFiled: February 24, 2005Date of Patent: November 20, 2007Assignee: Fujitsu LimitedInventor: Hiroyuki Higuchi
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Publication number: 20070244686Abstract: A calibration method of a mixed mode simulation calibrates standard delay times in a standard delay format and includes obtaining a digital output circuit from a digital circuit, obtaining an analog output circuit from an analog circuit, performing a simulation on the digital output circuit connected to the analog output circuit to obtain an ideal output, obtaining a first delay time according to the standard delay times of the digital output circuit, performing a calibrative analog-to-digital mixed mode simulation using the first delay time to obtain an analog-to-digital mixed output, comparing the ideal output and the analog-to-digital mixed output to calibrate the first delay time, and calibrating the standard delay times of the digital output circuit according to the calibrated first delay time.Type: ApplicationFiled: July 7, 2006Publication date: October 18, 2007Inventors: Yaong-Jar Chang, Yung-Chieh Lin, Jung-Chi Ho, Pei-Wen Luo
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Patent number: 7283942Abstract: The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called simulation paths. Each simulation path is simulated separately to determine its contribution to the overall delay in the path. According to another embodiment of the present invention, linear and non-linear loads are modeled using linear circuit models to further increase the speed of the simulator. According to another embodiment, driver circuits are simulated using non-linear circuit models. Before a simulation is performed, sample input and output values for the non-linear models are computed and stored in memory. When a circuit design is simulated, the input and output values are accessed from the memory. Intermediate values are determined by interpolating from the values stored memory.Type: GrantFiled: November 26, 2002Date of Patent: October 16, 2007Assignee: Altera CorporationInventor: David Lewis
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Patent number: 7266488Abstract: A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.Type: GrantFiled: March 5, 2003Date of Patent: September 4, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Douglas E. Wallace, Jr., Jonathan P. Dowling
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Patent number: 7260515Abstract: A method and apparatus for cycle-based simulation of a transparent latch includes classifying a phase of the transparent latch, classifying a phase of an input to the transparent latch, and classifying a phase of a simulation cycle. The transparent latch is simulated as a cycle-based simulation element based on the phase of the transparent latch, the phase of the input to the transparent latch, and the phase of the simulation cycle.Type: GrantFiled: March 28, 2002Date of Patent: August 21, 2007Assignee: Sun Microsystems, Inc.Inventor: Liang T. Chen
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Publication number: 20070192079Abstract: Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.Type: ApplicationFiled: February 16, 2007Publication date: August 16, 2007Inventors: Karl Van Rompaey, Andreas Wieferink
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Patent number: 7254794Abstract: Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.Type: GrantFiled: June 3, 2005Date of Patent: August 7, 2007Assignee: Xilinx, Inc.Inventor: Richard P. Burnley
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Patent number: 7246054Abstract: Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performances on the Closed Queuing Network (CQN) simulation are compared with each other. Lookback can be used to reduce the rollback frequency in optimistic simulations. The relation between lookahead and lookback is also discussed in detail. Finally, it is shown that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.Type: GrantFiled: May 13, 2003Date of Patent: July 17, 2007Assignee: Rensselaer Polytechnic InstituteInventors: Boleslaw K. Szymanski, Gang Chen
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Patent number: 7239997Abstract: A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.Type: GrantFiled: January 14, 2004Date of Patent: July 3, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7239996Abstract: Printed circuit board, ASIC, transistor group, or other circuit timing can be analyzed by symbolically modeling the circuit, simulating the behavior of the circuit, analyzing the behavior to catch timing violations. Routing constraints for critical traces can be made by using the analysis results as the input to a trace circuit router. Further timing verification of the printed circuit board, ASIC, transistor group, or other circuit layout may be accomplished by analyzing and modeling the interconnect delays of the traces, simulating the symbolic circuit model with the interconnect delay model, and analyzing the behavior of the circuit for timing violations.Type: GrantFiled: May 28, 2003Date of Patent: July 3, 2007Inventors: Arthur J. Boland, Richard M. Pier, William Matthew Hogan
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Patent number: 7231336Abstract: In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.Type: GrantFiled: December 5, 2003Date of Patent: June 12, 2007Assignee: Legend Design Technology, Inc.Inventors: You-Pang Wei, Yuhung Liao, Mingchi Liu, YuJiao Ping
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Patent number: 7228262Abstract: An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.Type: GrantFiled: July 1, 2004Date of Patent: June 5, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Anzou, Chikako Tokunaga, Takashi Matsumoto
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Patent number: 7224689Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.Type: GrantFiled: July 17, 2002Date of Patent: May 29, 2007Assignee: Sun Microsystems, Inc.Inventor: Jay R. Freeman
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Patent number: 7222319Abstract: A timing analysis apparatus reads a net list including connection information and the like of circuit cells of an LSI, delay data for previously storing delay information of the circuit cells, stage count-derating factor dependency and components P, V and T of a derating factor; detects the number of stages of each signal path by a signal path cell counting section; determines a derating factor corresponding to the extent of averaging of random variation of each signal path in accordance with the number of stages of the signal path; and performs timing analysis on the basis of the determined derating factor. Therefore, more realistic and highly accurate timing design can be performed on a large-scale circuit.Type: GrantFiled: April 8, 2005Date of Patent: May 22, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7219320Abstract: OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.Type: GrantFiled: March 24, 2004Date of Patent: May 15, 2007Assignee: Fujitsu LimitedInventors: Tetsuo Kawano, Satoru Yoshikawa, Toshikatsu Hosono, Shigenori Ichinose, Takashi Yoneda
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Patent number: 7219048Abstract: Aspects of the present invention include a methodology for the general timing-driven iterative refinement-based approach, a timing-driven optimization (TDO) method that optimizes the circuit depth after the area oriented logic optimization, and a layout-driven synthesis flow that integrates performance-driven technology mapping and clustering with TDO to account for the effect of mapping and clustering during the timing optimization procedure of TDO. The delay reduction process recursively reduces the delay of critical fanins of a selected. Furthermore, in one embodiment, the fanins of the selected node are sorted according to their slack values.Type: GrantFiled: January 2, 2001Date of Patent: May 15, 2007Assignee: Magma Design Automation, Inc.Inventor: Songjie Xu
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Patent number: 7216315Abstract: For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.Type: GrantFiled: January 6, 2004Date of Patent: May 8, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takaki Yoshida
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Patent number: 7216320Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.Type: GrantFiled: November 8, 2004Date of Patent: May 8, 2007Assignee: Clear Shape Technologies, Inc.Inventors: Li-Fu Chang, Yao-Ting Wang, Fang-Cheng Chang
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Patent number: 7213223Abstract: A method and computer readable storage medium for estimating total path delay in an integrated circuit design include of receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design. A sum of the stage delays, a worst case sum of the stage delay variations, and a root-sum-square of the stage delay variations are calculated. A a value of a weighting function is calculated as a function of the number of stage delays. A a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations is calculated from the weighting function. The weighted sum is generated as output to estimate total path delay.Type: GrantFiled: November 19, 2004Date of Patent: May 1, 2007Assignee: LSI Logic CorporationInventor: Alexander Tetelbaum
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Patent number: 7206958Abstract: Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.Type: GrantFiled: October 21, 2003Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Jeannette N. Sutherland, Robert E. Mains, Matthew J. Amatangelo
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Patent number: 7203632Abstract: Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.Type: GrantFiled: March 14, 2003Date of Patent: April 10, 2007Assignee: Xilinx, Inc.Inventors: Roger B. Milne, L. James Hwang, Jeffrey D. Stroomer, Nabeel Shirazi, Haibing Ma, Jonathan B. Ballagh
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Patent number: 7200544Abstract: There is disclosed an IC simulation system operable to (i) store a plurality of HDL modules, each of which is representative of a circuit element, (ii) receive a HDL description of a desired circuit, and (iii) synthesize a circuit netlist as a function of the received HDL circuit description and ones of the plurality of HDL modules, the circuit netlist is responsible for defining behavioral relationships among associated ones of the HDL modules, and associate a timing-violation controller with the circuit netlist to ignore selected timing violations sensed as a function of various ones of the behavioral relationships during simulation of the desired circuit.Type: GrantFiled: October 26, 2001Date of Patent: April 3, 2007Assignee: National Semiconductor CorporationInventor: Hal C. McCown
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Patent number: 7197445Abstract: A method (900) of modeling transactions and performing inertial rejection can include representing a plurality of scalar signals as one or more transaction objects, wherein each transaction object comprises a start index, an end index, values for each constituent scalar signal which correspond to an index within a range specified by the start index and end index inclusive, and a time at which the values are transacted. (400) The method further can include constructing and adding a new transaction object for the plurality of scalar signals (920) and comparing the new transaction object with at least one existing transaction object (925) wherein the at least one existing transaction object occurs earlier in time than the new transaction object and is within a rejection window. At least one of a start index and an end index of the at least one existing transaction object can be manipulated (975).Type: GrantFiled: March 14, 2003Date of Patent: March 27, 2007Assignee: Xilinx, Inc.Inventors: Kumar Deepak, Jimmy Zhenming Wang, Wei Lin
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Patent number: 7197629Abstract: A method of computing overhead associated with executing instructions on an out-of-order processor which includes determining when a first instruction retires, determining when a second instruction retires, and calculating an overhead based upon subtracting when the first instruction retired from when the second instruction retired.Type: GrantFiled: November 22, 2002Date of Patent: March 27, 2007Assignee: Sun Microsystems, Inc.Inventor: Dominic Paulraj
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Patent number: 7188146Abstract: In a navigation system in which the page data loaded from a server are displayed in a terminal, the server receiving the request for data loading from the terminal transmits the requested data if the data generation has ended, but, if not, estimates the end time and transmits the estimated end time together with display information indicating that the data generation is in progress. The terminal, issuing the request for data loading, displays the display data received in response to the request, and, if the estimated end time of data generation is received together with the display data, issues the request for data loading again when the estimated end time is reached. Thus efficient processing can be realized without wasted waiting time or wasted request for data loading in the terminal, in case the data generation requires a long time.Type: GrantFiled: December 7, 1999Date of Patent: March 6, 2007Assignee: Canon Kabushiki KaishaInventor: Tsunehiro Tsukada
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Patent number: 7184346Abstract: Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.Type: GrantFiled: January 4, 2005Date of Patent: February 27, 2007Assignee: Virage Logic CorporationInventors: Jaroslav Raszka, Vipin Kumar Tiwari
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Patent number: 7177789Abstract: A simulator fitted with at least one microprocessor sends input simulation signals to a unit under test, and receives therefrom output signals in reaction thereto. The method consists in processing some of the output signals from the unit as they are issued by means of a programmable logic circuit, in storing parameter values corresponding to said processed signals, and in giving the microprocessor access to the stored parameter values at a frequency which is compatible with its own operating speed. The apparatus enables the method to be implemented. The simulator comprises at least one programmable logic circuit, e.g. of the FPGA type, that is suitable for receiving at least some of the signals output by the electronic unit.Type: GrantFiled: August 30, 2000Date of Patent: February 13, 2007Assignee: AlstomInventor: Denis Miglianico
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Patent number: 7167821Abstract: A performance prediction simulator gives effect to the resource contention among multiple resources in a simulated system by adjusting event durations appropriately. A resource topology tree defining the resource configuration of the system is input to the simulator. The simulator includes an evaluation engine that determines the amount of resource used during each simulation interval of the simulation and records the resource usage in a resource contention timeline, which can be displayed to a user. The amount of resource used during a simulation is also used to adjust the event duration calculations of the hardware models associated with each event.Type: GrantFiled: January 18, 2002Date of Patent: January 23, 2007Assignee: Microsoft CorporationInventors: Jonathan C. Hardwick, Efstathios Papaefstathiou
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Patent number: 7162411Abstract: Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.Type: GrantFiled: November 22, 2002Date of Patent: January 9, 2007Assignee: Texas Instruments IncorporatedInventors: Manisha Agarwala, Maria B. H. Gill, John M. Johnsen
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Patent number: 7162389Abstract: An evaluation device, for evaluating a control unit (ECU) to which another control unit (ECU) is connected through a communication line and communicating with it, which can simulate even an unstable state such as when the other control unit does not start up right after power is turned on. The evaluation device is provided with a communication behavior simulating unit for simulating communication behavior of that other control unit and a switching unit for switching the communication behavior simulating means so as not to simulate the communication behavior. The communication behavior simulating unit is provided with an acknowledgement signal generating unit, and the switching unit disables the operation of the acknowledgement signal generating unit.Type: GrantFiled: November 30, 2004Date of Patent: January 9, 2007Assignee: Fujitsu-Ten LimitedInventors: Harunaga Uozumi, Kenichi Kinoshita
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Patent number: 7159160Abstract: A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.Type: GrantFiled: June 21, 2004Date of Patent: January 2, 2007Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Gilbert Yoh, Manuel Salcido, Stan Perino
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Patent number: 7155691Abstract: A system for analyzing an electronic circuit includes a computer. The computer obtains a description of the electronic circuit. The computer further analyzes the electronic circuit by using compiled static timing analysis (CSTA). Specifically, in one embodiment, the computer is configured to compile a timing model for the circuit responsive to the description of the circuit. The timing model comprises a description of a timing path and a description of an algorithm to evaluate the timing path. The computer is further configured to analyze a design that includes the circuit, wherein the analyzing comprises evaluating the timing model, and wherein evaluating the timing model comprises performing the algorithm to evaluate the timing path.Type: GrantFiled: June 4, 2004Date of Patent: December 26, 2006Assignee: Nascentric, Inc.Inventor: Curtis Ratzlaff
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Patent number: 7149676Abstract: The performance of a system is simulated in a method comprising: performing simulation in a first simulation mode for at least a first portion of code that models at least a portion of the system; and performing simulation in a second simulation mode for at least a second portion of code that models at least a portion of the system.Type: GrantFiled: June 21, 2001Date of Patent: December 12, 2006Assignee: Renesas Technology CorporationInventor: Sivaram Krishnan
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Patent number: 7139691Abstract: Ground bounce noise in a digital system is evaluated using a weighted average simultaneous switching output (“WASSO”) on an I/O bank of a digital switching device, such as a field programmable gate array (“FPGA”). The WASSO allows a designer to normalize output drivers having different characteristics on a single I/O bank. In a further embodiment, a simultaneous switching output allowance (“SSO allowance”) is calculated using scaling factors derived from values assumed in the creation of published SSO information and predicted actual values of the device in a digital system that are not represented in tables of published SSO guidelines. The SSO allowance is used in conjunction with WASSO values of adjacent I/O banks to evaluate ground bounce for adjacent I/O banks.Type: GrantFiled: October 21, 2003Date of Patent: November 21, 2006Assignee: Xilinx, Inc.Inventor: Anthony T. Duong
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Patent number: 7133821Abstract: A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.Type: GrantFiled: November 22, 2002Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Manisha Agarwala, Maria B. H. Gill
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Patent number: 7133817Abstract: A method of verifying a digital hardware design simulated in a hardware design language (HDL). States to be verified are defined, including signal values for each component within the hardware design. A test is applied to the hardware design, such that traces of internal signals within the hardware design are recorded. Each trace includes signal data, time data and at least the internal signals associated with the components. The traces are processed to ascertain whether the plurality of components simultaneously had the signal values associated with the state, thereby to ascertain whether the state was achieved.Type: GrantFiled: February 12, 2002Date of Patent: November 7, 2006Assignee: STMicroelectronics LimitedInventor: Nicholas Pavey
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Patent number: 7133819Abstract: Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.Type: GrantFiled: February 13, 2001Date of Patent: November 7, 2006Assignee: Altera CorporationInventor: Michael D. Hutton