Abstract: A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

Abstract: A method and apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution. The method includes partitioning the complete clock net into a global clock net and a plurality of local clock nets, simulating a load for each of the local clock nets, simulating the global clock net, and combining the simulations to form the complete clock net. The method may further include evaluating the combination to determine whether the results converge and storing the simulation results in a Clock Data Model. When the results do not converge, the method re-simulates at least one of the local clock nets and re-simulates the global clock net. The Clock Data Model collects, manages, retrieves, and queries all of the simulation information. The method may further analyze the complete clock net to predict the clock skew for a given data transfer path for potential redesign.

Abstract: A method and apparatus for simulating an electronic circuit having a plurality of ports uses a digital processor to identify signal transmission characteristics associated with each of the ports. A plurality of test frequencies are selected with which to measure frequency response of the electronic circuit at each of the ports. For each of the test frequencies, a signal characteristic is identified at each of the ports in response to a sequential application of each of said test frequencies to each port. Scattering parameters corresponding to each port are extracted for each frequency based on the signal characteristics. These scattering parameters are then transformed into a time domain representation of the electronic circuit.

Abstract: The present invention provides a method and apparatus for amortizing critical path computation. According to an embodiment of the present invention, a digital circuit design is simulated using cycle based simulation techniques. The digital circuit design is represented by a data flow graph. In the data flow graph are one or more critical paths and one or more shortest paths. The data flow graph representing the digital circuit design is unrolled into a plurality of simulation cycles. Thereafter, the multiple cycle graph is scheduled to a plurality of processing units, thereby simulating several cycles at once. In one embodiment, communication latency is relaxed by delaying the arrival times of external inputs within the unrolled cycles. In another embodiment, the unrolled circuit allows for scheduling compaction. The present invention provides for improved simulation speed by better balancing the workload among multiple processing units in the system.

Abstract: There is disclosed a logical simulation method, comprising the steps of: executing simulation of 1 cycle; and proceeding to the execution of simulation for a next cycle without displaying a waveform indicating the simulation result of a cycle if the cycle is one for turning OFF a waveform display.

Abstract: A method and apparatus for simulating a source system having a plurality of source clocks to trigger a plurality of logic elements is provided. The plurality of source clocks are modeled with a global clock. At least one of the plurality of source clocks is modeled with a clock mask and a clock state. At least one of the plurality of logic elements is evaluated when the global clock generates a global clock pulse and updated based on the clock mask and the clock state.

Abstract: In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.

Abstract: A timing model is constructed using a timing view of a functional component of a circuit under consideration. This timing view uses one or more timing elements to replace timing determinant blocks of the actual circuitry for the purposes of timing analysis. These timing elements represent signal delays from point to point in the circuit and relative timing between signals in the circuit, and thus represent the important timing characteristics of the actual circuitry. After creating the timing view of the circuit, a cross-section of the circuit comprising the functional component is simulated to produce values for delays and relative timing between signals in the circuit. These values from the circuit simulation are then attached to the various timing elements in the timing view to create the timing model for the portion of the circuit represented by the timing view.

Abstract: A method for verifying a source-synchronous communication interface of a processor is disclosed. A software model of a first device having a source-synchronous communication interface and a software model of a second device capable of communicating with the first device via the source-synchronous communication interface are provided. The source-synchronous communication interface includes an applied clock line, an address line, an echo clock line, and a data line. A simulation of a data request from the first device model to the second device model via an applied clock signal along with an address on the applied clock line and the address line is initially performed. The requested data is then received by the first device model from the second device model via the data line after various delays between the applied clock signal and an echo clock signal on the applied clock line and the echo clock line, respectively. Finally, the requested data received by the first device model is verified as to its veracity.

Abstract: There is provided a delay time calculating method for use in a hierarchical design, capable of accurately calculating the delay amount at a boundary between different level layers in a hierarchical structure. A whole chain (T$01 to T$13) is divided into a first partial chain (T$04 to T$10) and a second partial chain (T$01 to T$03, T$11 to T$13). A first delay amount (TD(4-10)) of the first partial chain (T$04 to T$10) is calculated. A third partial chain (T$01 to T$05, T$09 to T$13) consisting of the second partial chain (T$01 to T$03, T$11 to T$13) and a plurality of chain elements (T$04 to T$05, T$09 to T$10) included in an end region of the first partial chain (T$04 to T$10), is generated, and a second delay amount (TD(1-5), TD(9-13)) of the third partial chain (T$01 to T$05, T$09 to T$13) is calculated.

Abstract: A gate delay calculation apparatus includes an Rs parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continues time function, an Rs determination portion for selectively extracting the parameter prestored in the Rs parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by Rs determination portion and the output load model.

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

Abstract: A circuit-characterization system includes a computer that uses a degradation option to degrade a characteristic of the circuit in order to calculate a degraded characteristic of the circuit. The computer uses a model of an operation of the circuit to characterize a constraint of the circuit and select a value for the constraint. The selected value of the constraint depends, at least in part, on the degraded characteristic of the circuit. Another circuit-characterization system includes a computer that characterizes first and second dependent constraints of an electronic circuit. The computer characterizes the first dependent constraint according to a model of an operation of the circuit to select a value for the first dependent constraint at a prescribed initial value of the second dependent constraint of the electronic circuit. The computer characterizes the second dependent constraint according to the model of the operation of the circuit to select a value for the second dependent constraint.

Abstract: A logical simulation system includes delay information operating part which receives a dispersion rule file in which information on dispersion in a chip having electrical and physical characteristics which influence the operation of an integrated circuit to be analyzed is described and which receives design information of the integrated circuit to prepare a delay information file in consideration of each influence of the information on the dispersion on the basis of the dispersion rule file and the design information; and logical simulation part which receives the design information and the delay information file to carry out a logical simulation of the integrated circuit.

Abstract: A method of and computer program product for modeling a logic circuit having combinational logic and latches, in which the latches are clocked by one of a first clock phase, a second clock phase or a pulse derived from the second clock phase, a subset of latches being scannable, comprises, for each latch in the logic circuit, associating the latch with one of the first and second clock phase; and when latch is associated with the first clock phase, modeling the latch as a buffer connected between the data input and output of latch; and when the latch is associated with the second clock phase, modeling the latch as an edge-triggered flip-flop having the same data input, data output and clock input as the latch.

Abstract: In generation of communication data, continuous data capable of being acquired by a data logger is set as original data and the original data is sampled every a timing period t inputted. Since the original data and timing of sampling are displayed on the same screen, it can visually be checked which portion of the original is sampled and sent. In the timing of sampling, an initial point can be shifted. Assuming urgent time such as abnormal occurrence, a sending point for sampling the original data and generating and sending the communication data can be inputted and set at the time other than the sampling period t.

Abstract: A time simulation technique for determining the service availability (or unavailability) of end-to-end network connections (or paths) between source and sink nodes is disclosed. The failure could be either a single failure mode or a multiple failure mode. The time simulation apparatus includes a network representation having pluralities of nodes, links and connections; each plurality having various attributes such as relating to failure, recovery and repair mechanisms. The apparatus further includes a mechanism for selecting one instance from each of the pluralities of nodes, links and connections based on the attributes; a failure/repair module for performing a simulated failure and repair on the selected instances as appropriate; a mechanism for selecting a connection between source and sink nodes; and an arithmetic mechanism for calculating availability of the selected connection.

Abstract: A method for reducing the computation time and improving the productivity in designing high-performance microprocessor chips that have no failures—due to crosstalk noise. The technique allows a very fast calculation of tables of frequency-dependent circuit parameters needed for accurate crosstalk prediction on lossy on-chip interconnections. These tables of parameters are the basis for CAD tools that perform crosstalk checking on >10K critical nets on typical microprocessor chips. A fast table generation allows for rapid incorporation of design or processing changes and transition to more advanced technologies.

Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Abstract: A circuit simulation method and system are provided, which can execute a highly precise delay analysis by generating a wiring structure which includes a target wiring conductor and a circumjacent wiring conductor in the circumferences of the target wiring conductor and which is generated in consideration of variation conditions, and by calculating a wiring capacitance on the basis of the wiring structure, thereby to highly precisely extracting a wiring capacitance in consideration of variation in fabricating process.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: A computer-implemented modeling, or planning, system provides a graphical user interface including a timeframe. Under user control, instances of component objects representing modeling entities can be displayed with respect to the timeframe for the input of time-related properties for the component objects. The component objects provide calculations in response to the time-related properties on properties of the component object for deriving an output comprising a time-series of output values. A resulting report can be generated based on the time-series of output values. The displayed instances of the component objects can be directly manipulated by the user in order to define the time-related properties. The direct graphical representation facilitates planning operations and enables accurate, rapid and easily understandable development of plans. Multiple scenarios can easily be generated using the system. A revision mechanism facilitates the return to a scenario modeled earlier.

Abstract: A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.

Abstract: Parameter values of an emulation parameter that is indicative of a data processing operation performed by a data processor are exported from the data processor. In response to detection of a condition wherein a first portion of a first parameter value is identical to a corresponding portion of a second parameter value, the second parameter value and only a remainder portion of the first parameter value other than the first portion are output from the data processor.

Abstract: A process for synthesis and rough placement of an IC design. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Each of the wires of the netlist is initially assigned a unit weight. Thereupon, a cell separation process assigns (x,y) locations to each of the cells based on the weights. The wires are then examined to determine their respective performance characteristics. The wires are iteratively re-weighted, and the cells moved according to the new weightings. Next, the cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of each of the gates can be either scaled up or down accordingly. Again, the nets are iteratively examined and their weights are adjusted appropriately. The cells are spaced apart according to the new weights.

Abstract: Behavioral synthesis allows a circuit design to be specified in a high-level hardware description language (HLHDL) that is more oriented towards expressing the desired behavior than the underlying hardware mechanisms by which such behavior will be accomplished. The present invention permits behavioral synthesis to be accomplished with control chaining information, but with the control chaining information determined by a basic data-flow based pretiming. Control chaining is useful because it permits advanced scheduling techniques in which the computation of a conditional functional unit can be considered for scheduling in the same clock cycle as the functional units that depend on the evaluation of that conditional functional unit. The present invention speeds up the step of pretiming, responsible for determining control chaining information, by eliminating additional processing, beyond data-flow chaining, for determining control chaining ready times.

Abstract: A computer-implemented method, system, and program product for application response time prediction provides an estimate of application performance in a second network given performance characteristics of the application in a first network. The invention avoids unnecessary simulation of an entire network, and is able to take into account the effect of network performance characteristics on both simple and non-simple applications, including those having relationships among threads.

Abstract: A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.

Abstract: A modeling method to incorporate transparency into black box models using setup time in a circuit timing model. The circuit timing model, comprising a plurality of latches initially represented using black box models, is generated. For each of the plurality of latches, an arrival time is calculated from the latch clock pin to an interface data output pin of the timing model, and the maximum arrival time is determined. For each of the plurality of latches, a setup time is calculated. A setup time is also calculated using the delay time from the interface data input pin to the interface data output pin and the maximum arrival time. The worst-case set up time is selected from these setup times and imposed at the interface data input pin. Satisfaction of the worst-case setup time causes the maximum arrival time to also be satisfied.

Abstract: The present invention simulates the behavior of a storage component by first determining whether a timing violation has occurred for the storage component. If one or more timing violations is detected, then an x (indicating uncertainty) is reflected at the output of the storage component. This x is maintained at the output of the storage component for a predetermined number of timing units. After the predetermined number of timing units has expired, the output of the storage component is changed from x to a certain value, such as a logical 1 or a logical 0. By changing the output to a certain value, the present invention prevents the x at the output of the storage component from indefinitely propagating to other components in the circuit. This in turn prevents large numbers of x's from appearing in the simulation results provided to the designer. Instead, values that are certain will appear in the results.

Abstract: A delay model of a macro is prepared in advance, and a delay of a top level is calculated using the delay model, to thereby reduce the clock skews between the respective macros to which clocks are supplied, within a functional block being designed.

Abstract: Hardware and software of a system is co-verified with synchronization events generated in the respective hardware and software verifications being accumulated and provided to the other verification on a periodic basis. The faster verification is halted to allow the slower verification to catch up, upon expiration of a synchronization window. Once caught up, the accumulated synchronization events are provided to the respective other verification. The transferred synchronization events are then in turn injected into the other verification at the same offset time into a synchronization period the synchronization events occurred in the previous synchronization period.

Abstract: Determining a switching factor is useful for optimizing integrated circuit (IC) design. One aspect of the invention is a method for determining the switching factor. The method includes applying a voltage to each interconnect of a pair of interconnects, each voltage having a waveform and a slew time. The method includes dividing the voltage waveform into time regions, and analyzing a behavior of a capacitor in each of the time regions by determining the value of an effective capacitance as seen from one of the interconnects. The method includes determining a total effective capacitance by time averaging the effective capacitance values and determining the switching factor from the total effective capacitance. The switching factor is a function of a ratio between the slew times, wherein a time-averaged effective value of the switching factor corresponds total effective capacitance.

Abstract: A highly reliable automatic evaluation is realized by constructing a mechanism which causes a simulator to monitor a regular cycle in which a result of a simulation becomes definite and a screen is renewed, and notifies this to an automatic evaluation unit.

Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Abstract: A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints.

Abstract: The disclosed devices are several forms of a timing insensitive glitch-free (TIGF) logic device. The TIGF logic device can take the form of any latch or edge-triggered flip-flop. In one embodiment, a trigger signal is provided to update the TIGF logic device. The trigger signal is provided during a short trigger period that occurs at adjacent times from the evaluation period. In latch form, the TIGF latch includes a flip-flop that holds the current state of the TIGF latch until a trigger signal is received. A multiplexer is also provided to receive the new input value and the old stored value. The enable signal functions as the selector signal for the multiplexer. Because the trigger signal controls the updating of the TIGF latch, the data at D input to the TIGF latch and the control data at the enable input can arrive in any order without suffering from hold time violations.

Abstract: A method for power net analysis of integrated circuits is provided. A circuit simulator determines current values for integrated circuit devices at specified supply voltages. A power net simulator uses the current values to calculate characteristics of the power net. The characteristics include voltage drop, current density and ground bounce. A layout representation of the power net is shown on a computer display along with the user-specified characteristics.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: In accordance with a timing verifying method of the present invention, the step of calculating a variation delay time composed of a wire delay time and a cell delay time in consideration of a process varying condition is performed independently of the step of performing logic simulation of a semiconductor integrated circuit based on the calculated variation delay time.

Abstract: An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design.

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator.

Abstract: The present invention is generally directed to a system and method for evaluating a netlist of a schematic to detect the output of a clock driver. In accordance with one embodiment of the invention, a method is provided for determining whether a circuit node is an output node of a clock driver circuit. The method includes the steps of ensuring that the node is a clock node, ensuring that the node is a node within an inverter loop, identifying every FET that is channel connected to the node, and, for every identified FET, ensuring that a signal that drives a gate node of the FET also drives a gate node of a different type FET. With these primary tests satisfied, the method determines the node under consideration to be an output node of a clock driver circuit. In accordance with another aspect of the invention, a method determines whether a circuit node is an output node of a clock driver circuit by ensuring that the node is a node within an inverter loop, and ensuring that a gate node of every FET (i.e.

Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: An integrated circuit device is layoutted on a semiconductor chip, and signal lines are routed between circuit blocks to be integrated on the semiconductor chip, wherein a conductive line is branched from another conductive line passing over one of certain circuit blocks expected to be identical in circuit characteristics with one another in order to pass over the other of the certain circuit blocks, thereby equalizing electric influence of a signal passing through the conductive line on the certain circuit blocks.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via an interface mechanism. The execution of a user program on a target processor that includes a cache is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator. The analysis also adds hooks to the user program such that executing the analyzed user program on the host computer system invokes a cache simulator that simulates operation of the cache.

Abstract: An simulator particularly suited for simulating the hardware/software behavior of embedded systems. The architecture of the simulator permits the hardware and software systems to be modeled as modules with well characterized behaviors. A concise module definition syntax is used to describe module behaviors, and a translator operates upon the module to abstract operations of module behaviors at a level which does not require cycle-based, direct interaction of each module with the underlying simulation engine.