Of Peripheral Device Patents (Class 703/24)
  • Patent number: 11175984
    Abstract: This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error (EC) information, which is linearly combined with similar information from other drives to create “superparity.” If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are use, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 16, 2021
    Assignee: Radian Memory Systems, Inc.
    Inventors: Robert Lercari, Craig Robertson, Mike Jadon
  • Patent number: 11175840
    Abstract: An apparatus in one embodiment comprises a host device comprising a processor coupled to memory. The host device is configured to communicate over a network with at least one storage system. The host device is further configured to generate a user space block device and to generate a kernel space block device corresponding to the user space block device. The host device is further configured to receive an input-output operation at the kernel space block device from an application executing on the host device and to transfer the input-output operation from the kernel space block device to the corresponding user space block device. The host device is further configured to submit the input-output operation to the at least one storage system based at least in part on the user space block device.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Md Haris Iqbal, Kundan Kumar
  • Patent number: 11157625
    Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 26, 2021
    Assignee: Dell Products, L.P.
    Inventor: Craig Lawrence Chaiken
  • Patent number: 11113091
    Abstract: An apparatus, method and computer program are described, the apparatus comprising processing circuitry configured to execute software, and an interface configured to receive, from the processing circuitry, a configuration request from first software requesting configuration of a virtualised device. In response to the configuration request, the interface is configured to forward a mediated request to the processing circuitry, and the mediated request comprises a request that second software having a higher privilege level than the first software determines a response to the configuration request received from the first software.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 7, 2021
    Assignee: Arm Limited
    Inventors: Alexandre Romana, Mario Torrecillas Rodriguez, Eric Biscondi
  • Patent number: 11095709
    Abstract: A hybrid cloud computing system having a private data center and a public cloud computing system is discussed. The private data center is managed by a first organization. The public cloud computing system is managed by a second organization, and the first organization is a tenant in the public cloud computing system. The hybrid cloud computing system is configured to generate a mapping that contextualizes virtual objects migrated between the private data center and the public cloud computing system based on the objects' location. Such a mapping is maintained to expose the true hybridity of the hybrid cloud rather than present two distinct views of a private data center (or private cloud) and a public cloud.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 17, 2021
    Assignee: VMware, Inc.
    Inventors: Sachin Thakkar, Debashis Basak, Serge Maskalik, Mark Bryan Whipple, Aarti Kumar Gupta
  • Patent number: 11029867
    Abstract: A memory system may include: a nonvolatile memory device including a plurality of memory blocks; and a controller for reading data stored in a physical address in response to a read command from a host, the read command including a first logical address, a first physical address corresponding to the first logical address, and a first read count associated with the first physical address, the controller may read first data from a first block corresponding to the first physical address and sends a response to the read command to the host, the response including the first data and updated information relating to the first read count.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Hwan Lee
  • Patent number: 11029934
    Abstract: A method includes analyzing operational code to determine identifiers used within the operational code. The method further includes grouping like identifiers based a relational aspect of the identifiers. The method further includes, for one or more identifier groups, determining potential feature(s) of the identifier group(s). The method further includes testing the potential feature(s) based on a corresponding feature test suite to produce feedback regarding meaningfulness of the potential feature(s). The method further comprises, when the meaningfulness is above a threshold, adding the potential feature(s) to a feature set. The method further includes, when the meaningfulness is at or below the threshold, adjusting analysis parameter(s), grouping parameter(s), feature parameter(s), and/or testing parameter(s).
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 8, 2021
    Assignee: UniqueSoft, LLC
    Inventor: Thomas J. Weigert
  • Patent number: 10996967
    Abstract: First and second virtual storage controllers represent first and second physical storage controllers that provide access to different physical storage devices that back first and second virtual disks. One or more computing nodes host a virtual storage array that includes paired virtual storage directors. Each virtual storage director has access to both the first and second virtual storage controllers. Thus, the virtual disks may be presented to the storage directors as dual-ported disks even if the physical storage devices are single-ported. The virtual storage directors and virtual storage controllers may each be hosted by a separate virtual machine or instantiated in a separate container.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 4, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jonathan Krasner, Chakib Ouarraoui, Steven McClure
  • Patent number: 10996975
    Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anton Korzh, Vijay S. Ramesh, Richard C. Murphy
  • Patent number: 10992543
    Abstract: Collectors are provided to network devices of an existing computer network. A reference network type associated with the existing computer network is determined. Based at least in part on telemetry and configuration information received from the collectors and the reference network type, an intent-based network model of the existing computer network is generated. The existing computer network is validated using the generated intent-based network model.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 27, 2021
    Assignee: Apstra, Inc.
    Inventors: Raghavendra Rachamadugu, Aleksandar Luka Ratkovic
  • Patent number: 10972540
    Abstract: Provided are a method, system and program for requesting storage performance models for a configuration pattern of storage resources to deploy at a client computing environment. A determination is made of a new configuration pattern of storage resources to deploy. A request is sent to a service provider with information on the new configuration pattern. A result set is received from the service provider having at least one provided configuration pattern having a degree of similarity to the new configuration pattern and a storage performance model for each of the provided configuration patterns. Each of the storage performance models indicate workload and performance characteristics for one of the provided configuration patterns. One of the provided configuration patterns is selected from the result set and the storage performance model for the selected configuration pattern is used to model performance at the client.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rakesh Jain, Ramani R. Routray, Sumant Padbidri, Yang Song
  • Patent number: 10949134
    Abstract: A first screen associated with printer queues is displayed in response to a user operation, and an output process of a document is executed using a printer queue selected on the first screen by a user operation.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 16, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Daisuke Yamazaki
  • Patent number: 10853280
    Abstract: A storage system includes a storage engine having a first compute node, a second compute node, a first fabric adapter, and a second fabric adapter, the first compute node having a first memory and the second compute node having a second memory. The first compute node is connected to both the first and second fabric adapters, and the second compute node is connected to both the second and first fabric adapters. Both fabric adapters are configured to perform atomic operations on a memory of its respective compute node, and each fabric adapter contains a multi-initiating module configured to enable both the first compute node and the second compute node to initiate memory access operations on its respective memory.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: James Guyer, Jason Duquette, Alesia Tringale, Julie Zhivich
  • Patent number: 10831489
    Abstract: Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak K. Singh
  • Patent number: 10817204
    Abstract: Facilitating migration of versioned data in a reverse chronological order is provided herein. A system can comprise a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can comprise initiating a migration of information from a source storage device to a target storage device. The information can comprise a current object version of data and previous object versions of the data. The current object version of data can comprise portions of the previous object versions of the data. The operations can also comprise facilitating a first migration of the current object version prior to the migration of the previous object versions. Further, the operations can comprise facilitating a second migration of the previous object versions in a reverse migration order.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: October 27, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Mikhail Borisov
  • Patent number: 10789001
    Abstract: Methods, systems, and apparatus, including a managed device comprising memory storage, one or more control registers, and circuitry to perform operations of receiving, from a control system, one or more posted write operations directed to the one or more control registers; based on the one or more posted write operations, storing in the one or more control registers, data specifying at least a system address of a memory of the control system, where the system address corresponds to a starting address of a predetermined section of the memory; and transferring managed device data from the memory storage to the predetermined section of the memory of the control system by issuing, to the control system and based on the system address of the memory, one or more posted write operations to write the managed device data to the predetermined section of the memory.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: September 29, 2020
    Assignee: Innovium, Inc.
    Inventors: Mani Kumaran, Mohammad Kamel Issa, Gururaj Ananthateerta
  • Patent number: 10754648
    Abstract: A microprocessor having the capability of executing a micro-instruction for series calculation is provided. The microprocessor includes an instruction decoder and an execution circuit for series calculation. The micro-instruction whose source operands correspond to an undetermined number x and a plurality of coefficients a0 to an (for x0 to xn) is decoded by the instruction decoder. Based on x and a0 to an, the execution circuit for series calculation includes at least one multiplier for calculating exponentiation values of x (e.g. xp), and includes at least one MAU (multiply-and-accumulate unit) for combining x, the exponentiation values of x, and the coefficients a0 to an for the series calculation.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: August 25, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Jing Chen, Xiaoyang Li, Weilin Wang, Jiin Lai
  • Patent number: 10719273
    Abstract: SCSI commands that are not supported by a client terminal can be enabled. In scenarios where the client terminal's operating system may not support the same SCSI commands as the server's operating system, a redirected mass storage device that does support the same SCSI commands as the server's operating system can still be initialized on the server as supporting these SCSI commands. Then, to allow the SCSI commands that are not supported by the client terminal's operating system to be provided to the mass storage device, a client-side proxy can employ a SCSI Pass Through Interface to send the unsupported commands rather than providing them to the client-side disk driver. The proxy may still provide supported SCSI commands to the client-side disk driver for typical handling.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 21, 2020
    Assignee: Wyse Technology L.L.C.
    Inventor: Gokul Thiruchengode Vajravel
  • Patent number: 10694023
    Abstract: A testing method for testing mobile communication devices comprises transmitting, by a testing front end module, a testing profile associated with a Universal Integrated Circuit Card, UICC, to a mobile communication device, activating the testing profile on the mobile communication device, setting, by a testing controller, the configuration of the mobile communication device to a testing mode according to the information of the activated testing profile of the UICC, and performing operational tests on the mobile communication device using a testing front end module of a testing system while the configuration of the mobile communication device is set to the testing mode.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: June 23, 2020
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventors: Uwe Baeder, Holger Jauch
  • Patent number: 10691249
    Abstract: An electronic device, an electronic system, or a method may be used for testing an electronic device. The electronic device may include a virtual touch circuit. The virtual touch circuit may be configured to transmit testing data. The testing data may represent sensory input data. The electronic device may include a touch host controller. The touch host controller may be configured to process sensory data inputs. The sensory data inputs may include the testing data. The electronic device may include a validation circuit. The validation circuit may be configured to evaluate performance of the touch host controller. The validation circuit may evaluate the performance of the touch host controller by using the testing data that was processed by the touch host controller. The touch host controller, the virtual touch circuit, and the validation circuit may be included in a single die.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventor: Lakshminarayana Pappu
  • Patent number: 10666507
    Abstract: Various technologies described herein pertain to controlling reconfiguration of a dependency graph for coordinating reconfiguration of a computing device. An operation can be performed at the computing device to detect whether an error exists in the dependency graph for a desired configuration state. The dependency graph for the desired configuration state specifies interdependencies between configurations of a set of features. An error can be detected to exist in the dependency graph when the desired configuration state differs from an actual configuration state of the computing device that results from use of the dependency graph to coordinate configuring the set of features. Feedback concerning success or failure of the dependency graph on the computing device can be sent from the computing device to a configuration source. The dependency graph can be modified (by the computing device and/or the configuration source) based on whether an error is detected in the dependency graph.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 26, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shayak Lahiri, Sean Anderson Bowles, Peter J. Kaufman
  • Patent number: 10642827
    Abstract: Functionality is described herein for presenting representations of the z most recently presented items. The functionality also presents indicators which convey the presentation modes that were last used to present the z items. When the user selects one of the z items, the functionality presents it, as a default, using the last-used presentation mode, as conveyed by the indicator associated with this item. In one particular case, the last-used presentation mode corresponds to a full mode or a snap mode.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: May 5, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John E. Churchill, Joseph Wheeler, Jérôme Jean-Louis Vasseur, Thomas R. Fuller, Jason D. Giles
  • Patent number: 10638601
    Abstract: Systems and methods for routing of conductive traces in a printed circuit board are described. In one embodiment, the method may include routing a first trace in a first layer of a printed circuit board of a solid state drive, routing a second trace in a second layer of the printed circuit board, and routing the first trace and the second trace between a serializer/deserializer (SerDes) of a first controller of the solid state drive and a SerDes of a second controller of the solid state driver. In some cases, the first trace and the second trace may be configured to transmit differential signals to communicate data between the first controller and the second controller. In some embodiments, the second layer may be adjacent to the first layer.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 28, 2020
    Assignee: Seagate Technology LLC
    Inventors: Vinod Arjun Huddar, Abhishek Laguvaram
  • Patent number: 10621354
    Abstract: Systems and methods for verifying Basic Input/Output System (BIOS) boot block code are described. In some embodiments, an Information Handling System (IHS) may include: a processor; a memory coupled to the processor, the memory comprising BIOS instructions stored thereon; and an embedded controller (EC) coupled to the memory, the EC configured to: after a power-on sequence of the IHS is initiated and before a power rail of the processor is turned on, unlock write access to the memory; perform an Error Correction Code (ECC) evaluation of a BIOS boot block code portion of the BIOS instructions; verify integrity of the BIOS boot block code portion; lock write access to the memory; and allow the processor to execute the BIOS instructions.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 14, 2020
    Assignee: Dell Products, L.P.
    Inventor: Craig Lawrence Chaiken
  • Patent number: 10623701
    Abstract: Disclosed is a system that includes a computing device, a presentation system, and a hardware module disposed between the computing device and the presentation system. The hardware module and the computing device each may be configured to exchange a signal that includes media data and emulated input/output (“I/O”) data, audio/visual data (“A/V”); the hardware module may also be configured to supply power to the computing device. The signal and the supplied power may be communicated between the hardware module and the computing device over a single cable.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Facebook, Inc.
    Inventors: Peter John Richard Gilbert Bracewell, Howard William Winter, Oliver Pell
  • Patent number: 10579292
    Abstract: New, more efficient and robust data storage devices and techniques are provided. In some aspects of the invention, a new form of data storage device is provided, incorporating storage units with simple writeable domains, and a readable conditioning structure positioned around the units. The readable structure elaborates the simpler data written in the domains to generate more complex and complete data sets. In some embodiments, the physical arrangement, or other attributes, of structural storage device elements may serve as the patterned reference device for data enhancement and supplementation.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 3, 2020
    Inventor: Christopher V. Beckman
  • Patent number: 10572369
    Abstract: A method for monitoring errors when testing a control program of a control device in a simulation environment, the control program being executed by an emulator on a computer, the emulator assigning an extended range of items to program variables of the control program, a variable value allocated to a program variable being stored in the extended range of items, the emulator marking program variables as erroneous or non-erroneous, the marking being carried out on the basis of an assignment of non-erroneous program variables to a first category and of erroneous program variables to a second category, or the marking being carried out on the basis of an error field stored in the extended range of items, a validity value being allocated to the error field of a non-erroneous program variable and an error value being allocated to the error field, of an erroneous program variable.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 25, 2020
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Thorsten Hufnagel
  • Patent number: 10565068
    Abstract: A backup copy of a production device is used to quantify suitability of host application data for placement on individual managed drives and virtualized managed drives based on storage capabilities associated with those drives. A data analysis program on a data backup storage array may generate block backup statistics to indicate that a production device or certain chunks, blocks or volumes of host application data are highly compressible or reducible via deduplication. The block backup statistics are sent from the data backup storage array to the primary storage array. The primary storage array uses the block backup statistics to select a particular storage resource with suitable storage capabilities for the data. Highly compressible data may be stored on a storage virtualization storage array with data compression capability, and data that is neither highly compressible nor reducible with deduplication may be stored on local resources.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: February 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Arieh Don, Gabriel Benhanokh, Ian Wigmore, Stephen Smaldone
  • Patent number: 10545854
    Abstract: The present disclosure is related in general to software testing and a method and a system for automatically identifying violation in the test cases. A test case validation system categorizes the test cases into event-based test cases and binary test cases. Further, a Part-Of-Speech (POS) pattern is detected in the one or more test cases based on POS tags assigned to each of the tokens in test cases. Thereafter, comparison of the detected POS pattern and the one or more tokens with predefined POS patterns and predefined tokens identifies violations in the one or more test cases if any, using pattern matching and Natural Language Processing (NLP). The predefined POS patterns and tokens used for comparison are filtered based on category of the test case thus accelerating the process of the violation identification. The test case validation system is capable of accurately identifying more than one type of violations simultaneously.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: January 28, 2020
    Assignee: Wipro Limited
    Inventors: Aman Chandra, Varun Anant
  • Patent number: 10462221
    Abstract: A distributed storage resource management in a hyper converged infrastructure is created. The system accesses a virtualized infrastructure comprising a plurality of host machines, each of said plurality of host machines having resources, the resources comprising: a central processing unit (CPU), a memory, and a storage, each of the plurality of host machines communicatively coupled with one or more virtual machines. The resources in each of the host machines are disaggregated. The resources are aggregated based on a nature of the resource into a common pool of shared resources. A request is received for a workload application having a resource requirement. The resource requirement of the workload application is matched with resources in the common pool of shared resources. The matched resources in the common pool of shared resources are assigned to the workload application.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: October 29, 2019
    Assignee: VMware, Inc.
    Inventors: Gireesha Udagani Siddappa, Samdeep Nayak
  • Patent number: 10445441
    Abstract: A hammer system and method thereof for monitoring an organization platform to detect system level problems of one or more applications. The hammer system may include a hammer device, an enhanced trunk group poller, and a client-specific application hammer. The client-specific application hammer may be structured as a simulator that is operable to periodically place calls into the organization platform and emulate real call scenarios. The simulator may include D-channel polling logic.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: October 15, 2019
    Assignee: West Corporation
    Inventors: Mahendra Varman, Mahmood S. Akhwand
  • Patent number: 10412046
    Abstract: There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. It is thus possible to continue using look-up tables while updating process is being carried out for some or all of the table entries. The solution provides benefits for systems that are limited in space and cost, by use of minimal memory thanks to the storing of small shadowed data instead of full shadowed table.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 10, 2019
    Assignee: NXP USA, Inc.
    Inventors: Avishay Moscovici, Michal Silbermintz
  • Patent number: 10346049
    Abstract: Systems and techniques for network on a chip based computer architectures and distributing data without shared pointers therein are described. A described system includes computing resources; and a memory resource configured to maintain a dedicated memory region of the memory resource for distributed read operations requested by the computing resources. The computing resources can generate a packet to fetch data from the dedicated memory region without using memory addresses of respective data elements. The memory resource can receive the first packet, determine whether the first packet indicates the distributed read operation, and determine that the dedicated memory region is non-empty. Further, the memory resource can fetch one or more data elements from the dedicated memory region based on the first packet indicating the distributed read operation and the dedicated memory region being non-empty, and send a packet that includes the one or more fetched data elements.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 9, 2019
    Assignee: Friday Harbor LLC
    Inventors: Andrew White, Douglas B. Meyer
  • Patent number: 10319446
    Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of memory blocks; a voltage generation circuit configured to generate a plurality of operating voltages; a decoder circuit configured to transmit the plurality of operating voltages to the memory cell array in response to a serial data signal that is sequentially inputted; and a control logic configured to generate the data signal, internal address signals and an internal clock signal in response to a command.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Won Sun Park
  • Patent number: 10318194
    Abstract: The apparatus comprises a plurality of interfaces, each interface having an associated interface ID; and a hardware-side processing device including at least one programmable hardware-implemented chip configured to process request packets, which are received from host computers and relate to access requests to one or more file system managed by the apparatus, and to generate response packets for the processed request packets; wherein, for a request packet which is received from a first host computer, at least one programmable hardware-implemented chip is configured to: determine the client ID being associated with the first host computer, determine the interface ID being associated with the first interface, determine whether the determined client ID and interface ID represent a permitted ID set or a prohibited ID set, and refrain from processing the received request packet if the determined client ID and interface ID represent a prohibited ID set.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: June 11, 2019
    Assignee: Hitachi Vantara Corporation
    Inventors: Andrew Stephen Chittenden, Jonathan Mark Smith, Antonio Robert Carlini, Ashwin Payyanadan, Robert Ian Williams
  • Patent number: 10291714
    Abstract: Systems and methods for using general software to control an internet of things (IOT) system with a virtual baseboard management controller (BMC). The system includes a cloud network server provided on a cloud network. When the cloud network server receive a gateway registration request from an IOT gateway device communicatively connected to multiple IOT devices, the cloud network server provides a virtual BMC, and registers the IOT gateway device to the virtual BMC. The virtual BMC may then allow an IOT software to register to the virtual BMC, thus enabling the IOT software to access the IOT gateway device and the IOT devices via the virtual BMC. The virtual BMC may send information to the IOT gateway device registered to the virtual BMC by a push technology. The IOT gateway device and the IOT software may respectively communicate with the virtual BMC using Intelligent Platform Management Interface (IPMI) messages.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 14, 2019
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Santhosh Samuel Mathews, Joseprabu Inbaraj, Chandrasekar Rathineswaran, Manikandan Palaniappan
  • Patent number: 10241703
    Abstract: A multivolume management method, executed by a computer, includes storing a dataset over a plurality of media storage devices, wherein the plurality of media storage devices has a corresponding plurality of physical identifiers, generating a conversion table that assigns the plurality of physical identifiers to a corresponding plurality of sequentially ordered virtual identifiers, wherein each physical identifier is uniquely assigned to one virtual identifier, receiving a request for the dataset, wherein the request references the plurality of sequentially ordered virtual identifiers, in response to receiving the request, generating a response comprising an ordered list of physical identifiers using the conversion table, and responding to the request with the response. A computer system and computer program product corresponding to the above method are also disclosed herein.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Hiroki Nishiyama, Terue Watanabe
  • Patent number: 10230592
    Abstract: Techniques described herein include determining, maintaining, and applying compound service performance metrics, based on data metrics from a plurality of different services. Service-specific data metrics may be received from a plurality of different communication services offered by a service provider, for example, Internet service, voice service, video service, SMS service, etc. Different combinations, relationships, and weighting factors for the data metrics may be defined and stored for each compound performance metric. Compound performance metrics may be defined, including for example, compound customer sentiment metrics, compound customer value metrics, and/or compound customer resource usage metrics. In some cases, machine-learning and/or analytics may be performed using service-specific data metrics and corresponding customer actions, in order to determine correlations between particular combinations of data metrics and customer actions.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 12, 2019
    Assignee: Oracle International Corporation
    Inventor: Hendrik Scholz
  • Patent number: 10205785
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and an access controller communicatively coupled to the processor. The access controller may be configured to, when locally coupled to a second information handling system determine if the second information handling system is authorized to perform virtual crash cart operations on the information handling system and, responsive to determining that the second information handling system is authorized to perform virtual crash cart operations on the information handling system, permit the second information handling system to perform virtual crash cart operations on the information handling system whereby the second information handling system implements one or more virtual information handling resources such that each virtual information handling resource behaves at least in part as a physical information handling resource present at the information handling system.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 12, 2019
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Shawn Joel Dube, Pablo Rafael Arias
  • Patent number: 10191876
    Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 29, 2019
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Wolfgang Kropp, Andreas Schiff
  • Patent number: 10178172
    Abstract: An electronic apparatus and a method for expanding a storage capacity of the electronic apparatus are provided. In the method, at least one storage equipment on a network is searched and logged in by using a network interface. A virtual disk is established and a volume of at least one disk in each storage equipment is attached to the virtual disk as a physical volume of the electronic apparatus. The physical volume is transformed into a logical volume and a file system of the logical volume is established for providing the electronic device to access the logical volume.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 8, 2019
    Assignee: QNAP SYSTEMS, INC.
    Inventors: Chun-Wei Chen, Yao-Ying Chu
  • Patent number: 10176119
    Abstract: Implementations disclosed herein include a method comprising detecting a workload request from a host, estimating a media cache fill-up rate based on the detected workload request, estimating a current media cache usage, predicting, based on the detected workload request, the estimated media cache fill-up rate and the estimated current media cache usage, a workload profile, and determining a preemptive media cache cleaning strategy based on the predicted workload profile.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 8, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: CheeHou Peng, PohGuat Bay, HaiBo Ye, KayHee Tang
  • Patent number: 10156988
    Abstract: Technologies for identifying data stored on a solid state drive (“SSD”) device that correspond to data associated with a delete event, and marking the deleted data stored on the SSD as invalid such that the SSD can avoid unnecessary operations on the invalid data. Included are interfaces operable to communicate invalid data information and providing a remove-on-delete command that provides invalid data information sufficient to identify the SSD data to be marked as invalid.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 18, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Frank J. Shu, Nathan S. Obr
  • Patent number: 10142446
    Abstract: In one embodiment, a method includes receiving, at a server from a client, a first request for a dialog and particular parameters associated with the first request; invoking a method of a class in a server-side library comprising server-side code, wherein the method corresponds to a dialog type of the requested dialog; generating, based on the invoked method, a first dialog code configured to implement functionalities supported by the requested dialog; sending, to the client, the first dialog code for execution to cause the dialog to be displayed; receiving a second request sent from the client in response to a specific user interaction with a component of the displayed dialog, wherein the second request is a modified version of the first request that comprises additional parameters corresponding to the specific user interaction; and sending, to the client, a second dialog code based on the additional parameters.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: November 27, 2018
    Assignee: Facebook, Inc.
    Inventors: Brent Justin Goldman, Naitik Hemant Shah, Wei Zhu
  • Patent number: 10122716
    Abstract: A communication and security device for a portable computer having an interface for connecting the security device to a host device to enable the security device to control encryption and decryption of data communication between a processor of the host device and a data storage of the host device. Examples include a security device with data storage for storing an encryption key for the encryption and decryption of the data communication, a security processor coupled to the interface and to the data storage for controlling the data communication by use of the encryption key, and a wide area communication interface configured for secure communication with a remote device. The security processor may be configured to control the data communication between the processor of the host device and the data storage of the host device based on the secure communication.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: November 6, 2018
    Assignee: ExactTrak Limited
    Inventors: Norman Shaw, John Pragnell
  • Patent number: 10101928
    Abstract: An information handling system for enhanced system management mode (SMM) security may include a processor, system management random access memory (SMRAM), persistent memory, and basic input/output (BIOS) memory. The system may include instructions that, when loaded and executed by the processor, cause the processor to initialize the memory, initialize the BIOS memory, initialize the persistent memory, and check whether the system has previously executed a power-on self test (POST) routine. Based on a determination that the system has not previously executed a POST routine, the processor may unzip the SMM Code located in the BIOS memory store the unzipped SMM Code in the persistent memory and in the SMRAM. Based on a determination that the system has previously executed a POST routine, the processor may create a duplicate copy of the SMM Code from the persistent memory and store the duplicate copy in the SMRAM.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 16, 2018
    Assignee: Dell Products L.P.
    Inventors: Vijay Bharat Nijhawan, Sumanth Vidyadhara
  • Patent number: 10095652
    Abstract: A dynamically configurable device including a connector configured to detect a first status of an interface selection mechanism, and a first Serializer De-serializer (SerDes) configured to drive a first selected interface from among a plurality of interfaces based on the first status. In response to the first status having a first state, the first selected interface is a first interface that causes the dynamically configurable device to present as a first type of device, and in response to the first status having a second state, the first selected interface is a second interface that causes the dynamically configurable device to present as a second type of device.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 9, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dean M. Jenkins, Dale Charles Main
  • Patent number: 10049073
    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 14, 2018
    Assignee: Apple Inc.
    Inventors: Michael J. Smith, Josh P. de Cesare, Brijesh Tripathi, Derek Iwamoto, Shane J Keil
  • Patent number: 10038962
    Abstract: In accordance with an embodiment, described herein is a system and method for testing and certification of media devices for use within a connected media environment. A testing device includes an input mechanism, for example a microphone, and a plurality of test files. Each test file can be used to produce a characteristic signal, for example an audio track having a particular frequency. The testing device emulates a gateway between a media device under test, such as an audio speaker, and a media server. Test scripts can be used to mimic commands to play or otherwise access media content at the device under test. Playback of a particular test file can be detected and recognized according to the characteristic signal produced by that test file. Resultant test information can be used to evaluate the performance and/or certify operation of the media device within the connected media environment.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignee: SPOTIFY AB
    Inventor: Trevor Bentley
  • Patent number: 9996580
    Abstract: A system, method, and computer-readable medium for the calculation of execution time estimates of user defined functions/user defined methods are provided. The execution of a UDF or UDM is timed several times at the time of the UDF/UDM creation, and an average execution time of the UDF/UDM is obtained. The resulting average execution time is then stored in a data dictionary where the optimizer may consult this value to factor it into the cost of execution of a query.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: June 12, 2018
    Assignee: Teradata US, Inc.
    Inventors: Michael Reed, Elizabeth Brealey, Kevin Virgil