I/o Adapter (e.g., Port, Controller) Patents (Class 703/25)
  • Patent number: 10296399
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Patent number: 10268815
    Abstract: An apparatus is described herein. The apparatus includes a controller and a proxy entity. The controller is to detect a peripheral device and authenticate the peripheral device according to a first protocol. The proxy entity that is to configure the peripheral device in an operable protocol in response to the authentication.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventor: Robert A. Dunstan
  • Patent number: 10235194
    Abstract: The disclosed embodiments provide a system that facilitates the use of a computer system with virtualization software. During operation, the system obtains a set of hardware attributes from the computer system and a hardware compatibility list (HCL) for the virtualization software. Next, the system uses the hardware attributes and the HCL to predict a compatibility of a hardware component in the computer system with the virtualization software. The system then uses the predicted compatibility to manage use of the computer system with the virtualization software.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 19, 2019
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Geoffrey G. Thomas, John Whaley, Umesh Agashe
  • Patent number: 10223160
    Abstract: A processing device executing a scheduler receives, by a device, a schedule from a remote server computing device, the schedule having a compact format that is understood by the device. The device stores the schedule and the processing device parses the schedule to identify a scheduled event. The processing device executes the scheduled event at a specified time in accordance with the schedule even in the absence of a network connection between the device and the remote server computing device.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 5, 2019
    Assignee: Ayla Networks, Inc.
    Inventors: Jigar Vora, Joseph R. Eykholt, Sudha Sundaresan, Pablo Sebastián Rivera, David Russell Friedman, Adrian Caceres
  • Patent number: 10114573
    Abstract: A data-serialization system initially uses a recursive serialization algorithm to serialize a hierarchy of nested data objects by translating those objects into a serial stream of data. The system determines that a stack-overflow error is likely to occur whenever the number of objects serialized by the system exceeds a threshold value, or whenever the stack has reached an unacceptable level of utilization. When the system determines that a stack-overflow error is likely or if the system detects that a stack-overflow error will definitely occur if another object is serialized, the system either transfers control to a nonrecursive algorithm that does not require a stack data structure or reduces stack utilization by transferring contents of the stack to a variable-size queue-like data structure.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy P. Ellison, Amit S. Mane, Sathiskumar Palaniappan, Vijay Sundaresan
  • Patent number: 10049038
    Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luca De Santis, Pasquale Conenna
  • Patent number: 10019269
    Abstract: A standalone automation device (100) comprises: a removable memory port (101), configured to transmit data between the device (100) and the equipment (200) which also has a removable memory port; a removable memory control unit (102), comprising a signal convertor (112) for converting a removable memory interface to a serial interface; a power supply unit (103), configured to provide power supply when the device (100) is connected to the equipment (200) and disconnected to the field, and an isolation unit (104), configured to isolate the power supply. Compared with the existing prior arts, the proposed solution is convenient for connecting with the computer or cellphone, especially with isolation solution for power supply.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: July 10, 2018
    Assignee: ABB Schweiz AG
    Inventors: Xiaobo Wang, Liang He, Huan Shi, Zhe Liu, Axel Lohbeck
  • Patent number: 9990452
    Abstract: Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 5, 2018
    Assignee: Mentor Graphics Corporation
    Inventors: Krishnamurthy Suresh, Mukesh Gupta, Praveen Shukla, Sanjay Gupta
  • Patent number: 9870191
    Abstract: A display device communicates with a terminal device and includes a display unit, an extracting unit, a generating unit, and a transmitting unit. The display unit displays display data including at least one of image data and drawn data corresponding to an operation performed by a user on a screen. The extracting unit extracts a part of the display data specified by the user out of the display data displayed by the display unit. The generating unit generates image data in a form corresponding to the terminal device based on the extracted display data. The transmitting unit transmits the image data to the terminal device.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: January 16, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventor: Masayuki Igawa
  • Patent number: 9792208
    Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Ghai, Guy Lynn Guthrie, Hien Minh Le, Hugh Shen, Philip G. Williams
  • Patent number: 9772956
    Abstract: A system and method for emulating a universal serial bus device is disclosed. An example embodiment may include an emulated USB (EUP) device that can emulate a host side of a USB connection. This device may have a microcontroller that is programmable with software to emulate a host connection of a physical USB device. In order to emulate a host connection of a USB device, the EUP device may configure USB host mode bus signals, initiate USB frames on the bus, indicate device status to an emulation process, and relay packets between a device and the emulation process.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: September 26, 2017
    Assignee: Google Inc.
    Inventors: Daniel A. Christian, Baird Jonathan Ramsey
  • Patent number: 9772195
    Abstract: A system for deleting map data comprises an interface and a processor. The interface is configured to determine a location associated with a device. The processor is configured to determine one or more map bundles to delete based at least in part on the location and delete the one or more map bundles.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 26, 2017
    Assignee: Lytx, Inc.
    Inventors: Daniel Lambert, Brendan Peter
  • Patent number: 9760661
    Abstract: A method for providing a virtual optical disk drive (ODD) is provided. The method can comprise: simulating a PCI IDE controller through PCI configuration space IO trap and simulating the ODD through IDE device IO trap.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: September 12, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Hua Shao
  • Patent number: 9747225
    Abstract: An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: August 29, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Tolga Ozguner, Robert Allen Shearer, Elene Terry, Jonathan Ross
  • Patent number: 9740363
    Abstract: The present disclosure describes a system and method for managing and disseminating community information in a cloud. The computer-implemented method and system for comparing service performance comprises receiving, by a server over a communication network from a computer of each of a plurality of client companies, metadata of a plurality of transactions in enterprise resource planning systems being operated by the plurality of client companies, and presenting, by the server over the communication network to a computer of a selected client company of the plurality of client companies, comparative performance information for display on a graphical user interface of the selected client company based on metadata of transactions in enterprise resource planning systems of other client companies that are substantially similar to the enterprise resource planning system of the selected client company.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: August 22, 2017
    Assignee: Velocity Technology Solutions, Inc.
    Inventors: Aaron Michael Gasperi, Thomas Mac Kremer, Ronald Perry Wright, Joshua Ryan Tallen, John Robert Waite, Doug Frey, Paul Mockenhaupt, Mark Rasmussen
  • Patent number: 9697172
    Abstract: One or more devices are configured to receive information regarding network devices associated with a physical network. The one or more devices are configured further to generate configuration data based on the information regarding the network devices. The one or more devices are configured further to generate a virtual network based on the configuration data. The one or more devices are configured to send information regarding the virtual network to a client device. The one or more devices are configured to receive a change to the virtual network from the client device; and cause a change, corresponding to the change in the virtual network, to occur in the physical network.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 4, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Pilar Somohano, Brian P. O'Sullivan, Hal L. Stern, Michael Yip, Aleksey L. Mints
  • Patent number: 9606786
    Abstract: An information-processing apparatus includes a communication unit that transmits a first command to register in a memory a service provided by an application using a first communicative method. The communication unit transmits a second command to register in the memory a service indicator of the service using a second communicative method different from the first communicative method.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 28, 2017
    Assignee: SONY CORPORATION
    Inventor: Yasuo Takeuchi
  • Patent number: 9600310
    Abstract: The disclosed embodiments provide a system that facilitates the use of a computer system with virtualization software. During operation, the system obtains a set of hardware attributes from the computer system and a hardware compatibility list (HCL) for the virtualization software. Next, the system uses the hardware attributes and the HCL to predict a compatibility of a hardware component in the computer system with the virtualization software. The system then uses the predicted compatibility to manage use of the computer system with the virtualization software.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: March 21, 2017
    Assignee: Open Invention Network, LLC
    Inventors: Geoffrey G. Thomas, John Whaley, Umesh Agashe
  • Patent number: 9535622
    Abstract: A method, computer program product, and computing system for defining a master slice pool within a backend storage array of a storage system. The master slice pool includes a plurality of data storage slices. A first portion of the plurality of data storage slices is assigned to a first frontend system included within the storage system, thus defining a first frontend slice pool. One or more data storage slices included within the first frontend slice pool are allocated to one or more storage objects associated with the first frontend system. A quantity of unused data storage slices included within the first frontend slice pool is determined. The quantity of unused data storage slices is adjusted based upon a target slice level.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 3, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Dennis Duprey, Miles A. de Forest
  • Patent number: 9483425
    Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: November 1, 2016
    Assignee: Sony Corporation
    Inventors: Haruhiko Terada, Lui Sakai, Naohiro Adachi
  • Patent number: 9383932
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint T. Fleischer
  • Patent number: 9380224
    Abstract: A method of sensing depth using an infrared camera. In an example method, an infrared image of a scene is received from an infrared camera. The infrared image is applied to a trained machine learning component which uses the intensity of image elements to assign all or some of the image elements a depth value which represents the distance between the surface depicted by the image element and the infrared camera. In various examples, the machine line component comprises one or more random decision forests.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 28, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Cem Keskin, Sean Ryan Francesco Fanello, Shahram Izadi, Pushmeet Kohli, David Kim, David Sweeney, Jamie Daniel Joseph Shotton, Duncan Paul Robertson, Sing Bing Kang
  • Patent number: 9274990
    Abstract: An interface device capable of supporting an unknown I/O device comprises: a transmission module, used for receiving a control signal sent by an I/O device and sending a feedback signal to the I/O device; a signal process module, used for generating a control indicating signal according to the control signal and generating the feedback signal according to a feedback indicating signal; and a USB interface, used for sending the control indicating signal to a data process device and receiving the feedback indicating signal from the data process device; wherein, information content of the control indicating signal and information content of the feedback indicating signal both comprise the information of a first device description unit and a first interaction description unit contained in a first device index chart.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 1, 2016
    Inventor: Yi-Hong Hsu
  • Patent number: 9275518
    Abstract: A wagering game developer can provide an online wagering game community, and receive continuous and current feedback about wagering games. The wagering game developer can use the online wagering game community to gauge popularity of wagering games, demonstrate wagering games, test wagering games, estimate wagering game life cycles, etc. Moreover, the wagering game developer can use the creativity of community members to modify and, perhaps, develop wagering games. The wagering game developer can decompose different aspects of a wagering game into executable code units that are platform independent, re-usable, and/or configurable (“wagering game widgets”). Users combine wagering game widgets, whether derived from a wagering game or user generated, to create a wagering game for playing in the online wagering game community.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 1, 2016
    Assignee: Bally Gaming, Inc.
    Inventor: Damon E. Gura
  • Patent number: 9195623
    Abstract: A plurality of address spaces are assigned to an adapter. To select a particular address space for the adapter, a requestor identifier and address space identifier provided in a request by the adapter are used. Each address space may have a different address translation mechanism associated therewith.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: November 24, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Thomas A. Gregg, Christoph Raisch
  • Patent number: 9148305
    Abstract: A configurable network switch is disclosed. The configurable network switch may include a plurality of network switch chips operatively connected to a plurality of connectors via a programmable crosspoint chip. The programmable crosspoint chip may be configured to operate in one or more network operating modes. In a first network operating mode, the programmable crosspoint chip may be configured to operate at 40 Gigabit Ethernet speeds, whereas in the second network operating mode, the programmable crosspoint chip may be configured to operate at 10 Gigabit Ethernet speeds. The configurable network switch may also include an input interface, such as an I2C interface, that allows an operator of the network switch to select the one or more network operating modes of the configurable network switch.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: September 29, 2015
    Assignee: Google Inc.
    Inventor: Leesa Marie Noujeim
  • Patent number: 9077635
    Abstract: A method and non-transitory computer readable medium for discovering network subnets are disclosed. For example, the method sets a host portion of a network address to a fixed value for a particular network, sends a discovery message to a subnet of a plurality of subnets having the fixed value of the host portion for the particular network, discovers the subnet if a response to the discovery message is received from a device and repeats the sending and the discovering until all of the plurality of subnets are checked, where the sending and the discovering are applied only to the fixed value of the host portion for each of the plurality of subnets.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: July 7, 2015
    Assignee: Xerox Corporation
    Inventors: Lawrence W. Meyer, Vijay Kumar, Walter Igharas
  • Patent number: 9032397
    Abstract: A data processing system facilitates virtual machine migration with direct physical access control. The illustrative data processing system comprises a software-programmable trap control associated with hardware registers of a computer that selectively vectors execution control of a virtual machine (VM) between a host and a guest. The data processing system further comprises a logic which is configured for execution on the computer that programs the trap control to enable the virtual machine to directly access the hardware registers when the virtual machine is not migrated and to revoke direct access of the hardware registers in preparation for virtual machine migration.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: May 12, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Troy Miller, Mark A. Criss, Jerry James Harrow, Jr., Thomas Turicchi, Michael Wisner
  • Patent number: 8966477
    Abstract: A system comprises a guest graphics subsystem with a combined virtual graphics device that combines underlying emulated virtual graphics device and virtual function of a physical graphics device to support virtual machine migration. The VMM in the system may expose to the guest a single combined virtual PCIe graphics device that combines access to the virtual graphics device and the virtual function, and switches between the virtual graphics device and the virtual function for graphics acceleration without triggering a PnP event in the guest OS. In response to the switch, the guest graphics stack and applications may redraw their windows to provide a consistent user experience.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Shanwei Cen, Raman Srinivasan, David J. Cowperthwaite
  • Patent number: 8949105
    Abstract: A disclosed interface between an emulator and a network that is readily scalable. In one aspect, a scalable solution is achieved through a hardware interface board positioned between the network and the emulator to allow proper transfer there between. A computer is separated from and coupled to the hardware interface board and provides the necessary control signals. Because it is done in hardware separated from the computer, the interface board is readily scalable through the simple addition of network chip sets. In another aspect, the interface board can be placed in two modes of operation, a live test mode and a direct test mode. In yet another aspect, packet formats may be changed on the interface board so that it appears to the emulator as if the network is operating at a different data transfer speed than is actually the case.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: William Eugene Jacobus, Robert John Bloor
  • Patent number: 8918307
    Abstract: A configuration manager identifies a first device and a second device within a simulated system. Each device within the simulated system includes an inbound port and an outbound port. Next, the configuration manager injects a simulation only packet, at an “outbound time,” on the first device's outbound port and detects that the second device's inbound port receives the simulation only packet at an “inbound time.” As such, the configuration manager identifies a direct connection between the first device and the second device and computes a latency time for the connection. In turn, the configuration manager configures one or more first device configuration registers and one or more second device configuration registers based upon the computed latency time.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Aaron Ches Brown, Jeff Jerome Frankeny, James Kai Hsu, Glenn Owen Kincaid
  • Patent number: 8893027
    Abstract: In an example embodiment, a device provides a connection to an endpoint coupled with a first network to a virtual desktop client coupled with a second network. The device obtains data from the virtual desktop client which client which includes at least one link to data available from an external server, such as streaming media. The device obtains the data from the external server and provides the data with data obtained from the virtual desktop client to the endpoint.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 18, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Stephan Edward Friedl, Thomas Martin Wesselman, Steven Chervets
  • Publication number: 20140337004
    Abstract: Aspects of the present disclosure relate to methods of managing and delivering digital media content data. In certain embodiments, a management device in communication to a computing device via a universal serial bus (USB) connector is provided. The management device has a processor, a volatile memory and a non-volatile memory. The non-volatile memory includes a first partition storing a firmware and a second partition. When executed at the processor, the firmware emulates an emulated bootable storage device for the computing device at the USB connector. In response to an access instruction from the computing device to access data stored at an emulated address of the emulated bootable storage device, the management device converts the emulated address to a physical address of the second partition, and accesses the data at the physical address. The data includes digital media content data and a control module configured to play the content data.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Applicant: AMERICAN MEGATRENDS, INC.
    Inventors: Sanjoy Maity, Baskar Parthiban, Varadachari Sudan Ayanam, Samvinesh Christopher, Joseprabu Inbaraj, Chandrasekar Rathineswaran, Blake Yang
  • Patent number: 8886513
    Abstract: A bus emulation device in accordance with one aspect of the present description includes an embedded microcontroller and a nonvolatile memory carried on a body. The memory contains firmware which includes boot code adapted to boot the microcontroller to operate in one of a plurality of dedicated operating modes in response to a mode switch. These dedicated operating modes include a learning mode in which bus signals generated by other bus devices are recorded in the nonvolatile memory, and an emulation mode in which recorded bus signals are retransmitted over the bus in response to received signals, to emulate a bus device. Other aspects are described and claimed.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Zailani Bin Mohd Nordin, Eng Tien Ee
  • Patent number: 8849647
    Abstract: Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control of one of the primary firmware or secondary firmware. The selected one of said primary firmware and secondary firmware may be used to certify a hardware driver for either the current generation (primary firmware) or a future generation (secondary firmware).
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: September 30, 2014
    Assignee: LSI Corporation
    Inventors: Rajiv Bhatia, Ankit Sihare
  • Patent number: 8838867
    Abstract: A means for extending a PCI System of a host computer via software-centric virtualization. A Root Complex is virtualized at the host computer, and physically separated with a portion located remotely at an Endpoint, such as at a Remote Bus Adapter. One aspect of the invention avoids the need for a Host Bus Adapter. The invention utilizes 1 Gbps-10 Gbps or greater connectivity via the host's existing standard LAN adapter along with unique software to form the virtualization solution. The invention works within a host's PCI Express topology, extending the topology by adding an entire virtual I/O hierarchy via virtualization. The invention enables I/O virtualization in those implementations where a specialized host bus may not be desirable or feasible. Some examples of this may be a laptop computer, an embedded design, a cost-sensitive design, or a blade host where expansion slots are not available or accessible.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 16, 2014
    Assignee: Nuon, Inc.
    Inventor: David A. Daniel
  • Patent number: 8831029
    Abstract: An integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric is disclosed. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: September 9, 2014
    Assignee: Intel Corporation
    Inventors: Michael Klinglesmith, Mohan Nair, Joseph Murray
  • Patent number: 8812288
    Abstract: A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Minoru Kawarabayashi, Takayuki Shimamura, Tatekuni Onoue, Yasuyuki Umezaki
  • Patent number: 8812287
    Abstract: A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventor: Daniel J Barus
  • Patent number: 8805667
    Abstract: A print control device includes: a creation unit that creates print data; an output unit that outputs the print data created by the creation unit to a printing device through a designated port; a determination unit that determines whether or not the print data is to be output to a non-connected port that is a port not connected to the printing device; and a display unit which, when the determination unit determines that the print data has been output to the non-connected port, displays at least one of a first operation screen that is an operation screen for instructing port switching and a second operation screen that is an operation screen for instructing deletion of the print data.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 12, 2014
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takuma Saito
  • Patent number: 8769448
    Abstract: In one embodiment, a method is provided for processing a circuit design having first and second sets of ports configured to couple to respective first and second sets of ports of a device on a hardware platform. In a data-acquisition mode, the circuit design is simulated using a user-selectable plug-in that couples the ports of the circuit design to an interface circuit. During the simulation, the interface circuit communicates data between respective ports of the circuit design and ports of the device. In a deployment mode, the circuit design is implemented in the hardware platform, in which the first and second sets of ports of the circuit design are respectively coupled to the first and second sets of ports of the device.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 1, 2014
    Assignee: Xilinx, Inc.
    Inventors: Arvind Sundararajan, Nabeel Shirazi, Sean P. Caffee
  • Publication number: 20140180665
    Abstract: The invention is an intellectual network storage device that uses a network to store and retrieve data, and that connects to an existing storage controller of a host computer. The device is transparent to the operating system of the host computer, and thus does not require additional software, such as a device driver, to operate. The device includes a device board, which is connected to an existing storage controller of a host computer via any suitable interface, a set of hardware or software acting as a remote storage server, and a connection that carries signals between the device board and the remote storage server.
    Type: Application
    Filed: March 3, 2014
    Publication date: June 26, 2014
    Inventors: Andriy NAYDON, Sergiy Naydon, Anton Kolomyeytsev
  • Patent number: 8756041
    Abstract: A simulation environment for running a process simulation used to validate an industrial control program. The simulation environment exposes the I/O module configurations defined in the control program and retrieves module configuration information therefrom. This I/O module configuration information is combined with generic, module-specific I/O module profiles to create a pool of available controller I/O points, which can be selectively associated with I/O points in the simulation to create an I/O point mapping. During control program validation, simulated I/O data is exchanged between the process simulation and the I/O module instances in the controller in accordance with the I/O point mapping.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: June 17, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Francisco P. Maturana, Raymond J. Staron, Danny L. Carnahan, Kenwood H. Hall
  • Patent number: 8744832
    Abstract: A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 3, 2014
    Assignee: Global Unichip Corporation
    Inventor: Peisheng Alan Su
  • Patent number: 8731899
    Abstract: Various embodiments of the present invention are generally directed to an apparatus and method for recovering data from a signal generator using a native communication channel and an emulated communication channel coupled in parallel to the native communication channel.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: May 20, 2014
    Assignee: Seagate Technology LLC
    Inventors: Jay Alan Mahr, Jim Everett Wilson, Todd Charles Thaler
  • Patent number: 8731898
    Abstract: A node on a serial bus, preferably a device such as a personal computer (PC), can emulate other devices using virtual device drivers. A PC connected to a 1394 bus exposes its CROM on the bus which presents an image to other nodes on the 1394 bus and describes the functional units supported by the node. The CROM can be changed dynamically by adding unit directories to the CROM detailing peripherals connected to the PC. The PC can then be enumerated as the connected device by other PCs on the bus. The PC can emulate or morph itself into any desired device or even multiple devices at the same time. The invention also allows a PC to create devices that don't yet exist on the bus. The invention allows a user to create virtual device objects with device properties to have just in case a user plugs the particular device in to the PC.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: May 20, 2014
    Assignee: Microsoft Corporation
    Inventor: Georgios Chrysanthakopoulos
  • Patent number: 8676560
    Abstract: In a normal operation, a physical unit simulator is allowed to speculatively perform high-speed continuous execution. Only when an actual input comes in, a speculative input and the actual input are compared with each other. Thereafter, in response to inconsistency between the inputs, the physical unit simulator is returned to a point closest to the point of the actual input and is allowed to execute a variable step module to reach the point of the actual input. Upon arrival at the point of the actual input, the simulator is shifted back to the high-speed continuous execution from there. Thus, a processing speed of the simulator can be significantly improved.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Koichi Kajitani, Hideaki Komatsu, Shuichi Shimizu
  • Patent number: 8612633
    Abstract: Techniques for reducing virtual machine input/output emulation overhead and decreasing the attack surface of a virtual machine architecture are disclosed.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 17, 2013
    Assignee: Microsoft Corporation
    Inventors: Lawrence R. Cleeton, Andrei Warkentin, Andrew Nicholas, Rene Antonio Vega, Jacob Oshins, John A. Starks
  • Patent number: 8560900
    Abstract: Adjusting receiving parameters without known data is disclosed, including: receiving an indication of whether data associated with a sector is error correcting code (ECC) uncorrectable; in the event that the indication is that the data is uncorrectable, determining a plurality of statistical information outputs using a detector; and using at least a subset of the plurality of statistical information outputs to adjust a set of one or more receiver parameters.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: October 15, 2013
    Assignee: SK hynix memory solutions inc.
    Inventors: Jason Bellorado, Marcus Marrow, Yu Kou
  • Patent number: 8532976
    Abstract: To provide an emulator capable of targeting a device capable of accepting connection of an expansion device for expanding a controller connection port to a plurality of controller connection ports. The emulator, targeting a device having at least one controller connection port and capable of accepting connection of an expansion device for expanding the controller connection port to a plurality of controller connection ports so as to accept connection of a plurality of controllers, emulates operation of the targeted device. The emulator assigns port identification information to each of controllers connected via wire or radio, the port identification information indicating to which of a controller connection port of the targeted device and the controller connection ports of the expansion device connected to the device the controller is assumed to be connected. The assigned port identification information is provided to a process for receiving an operation carried out on the controller.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: September 10, 2013
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Shinichi Tanaka, Tadayasu Hakamatani, Masaki Higuchi