Abstract: A method for automatically creating a corner case situation on a bus is provided. The method uses a multi-agent bus interface verification tool to create the corner case situation. Further, a method for verifying a bus interface by creating a corner case situation is provided. Further, a computer system having a multi-agent bus interface verification tool is provided. Further, a multi-agent bus interface verification software tool is provided. Further, a multi-agent bus interface verification tool that can test a bus bridge is provided. Further, a multi-agent bus interface verification tool that generates erroneous response transactions to test circuit performance is provided.

Abstract: A method for verifying the correctness of the functional behavior of a processor cooperating with software is provided. Furthermore, the method allows verification of a CPU having at least a part of its instruction set implemented with microcode. First, the microcode is independently tested by using a functional emulator performing in the same way as the processor hardware according to the processor's functional specification. Then, the microcode is tested by using a hardware emulator behaving in the same way as the processor hardware according to the design of the processor's logic gates. Finally, the microcode is tested against the actual processor hardware. This method allows the functionality of a newly designed CPU to be checked in a simulation, even before actual system integration. Advantageously, many problems in this area, relating to the interaction of the microcode and the processor hardware can be found before the actual processor hardware is manufactured.

Abstract: Techniques for achieving the effects of significantly reducing the amount of computer memory needed to simulate the behavior of a multi-stage pipelined processor, as well as, significantly increasing the performance of the simulation process by eliminating the storing and copying of redundant information are described. These beneficial effects are achieved by reordering the chronological sequence of execution of software models of the various pipeline stages with respect to the actual instruction-flow sequence implemented by the processor hardware. This approach takes advantage of the independence of the stages within a cycle to make the results computed by a previous stage directly available to its subsequent stage without the use of transient data space or data copying. In particular, it is shown how to apply this technique to the simulation of a multi-parallel-stage VLIW array processor, such as the manifold array (ManArray) processor.

Abstract: A computer-implemented graphics system defines an object-oriented framework for describing three-dimensional (3D) graphical objects, systems, and simulations. A 3D graphical image, a system, and a simulation are implemented as a directed multi-graph that includes a plurality of components defined by nodes connected by edges. A directed multi-graph engine in a graphics computer program processes the directed multi-graphs, wherein each node in the graph performs some specific function and the edges define relationships between the nodes. There are no restrictions on node types, and thus nodes may represent graphic objects (a visual representation), rules (rule-base behavior), attributes (data that does not affect the fundamental definition of the object), properties (data that affects the fundamental definition of the object), behaviors (methods), finite state machines (a sequence of actions and states), and any other user-defined component.

Abstract: A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.

Abstract: In a semcard management application, a user interface that consists of several panels that facilitate the use of semcards, the objects they represent, and the knowledge network is described. These panels include an entry point panel, a filter panel, a results panel, and a viewer. One category of entry points is referred to as “context” entry points. Contexts allow semcards to be organized into hierarchically arranged categories. After the user has created a context, this context can be used as an entry point to a set of semcards meeting a certain criteria.

Abstract: A method and system of emulating serial corn port communication. A computer processing system has computer-executable operating system instructions including first instructions that interact with a first serial device according to a predefined input/output (I/O) hardware interface. A first serial device has a receive port and a transmit port and has the predefined (I/O) hardware interface. A second serial device has a receive port and a transmit port. The transmit port of the first serial device is in serial communication with the receive port of the second serial device, and the receive port of the first serial device is in serial communication with the transmit port of the second serial device. Computer-executable instructions emulate serial communication port device communication and include instructions that transmit information over another medium in response to receive requests from the second serial device.

Abstract: The present invention is a method and apparatus for implementing in embedded software the functionality of one or more external user interface circuits either in a surface mountable integrated circuit or in the main system CPU of a telecommunication unit.

Abstract: A method of and apparatus for efficiently and effectively coupling a newly designed peripheral device to a legacy data processing system. The approach utilizes emulation of a SCSI tape device by a SCSI DVD device. Through device emulation, system-wide modifications are minimized.

Abstract: A diagnosis system includes procedures to perform various operations, including diagnosis of problems, in a run-time environment recreated from dump information. The dump information is saved in response to a fault occurring in a node, which may be part of a parallel processing system. The diagnosis system may be separate from the parallel processing system or it may be one of the nodes of the parallel processing system. Setting up the run-time environment includes identifying memory sections associated with a task that caused the fault and filling the identified memory sections with data extracted from the dump information. Diagnosis procedures may then be run in the recreated run-time environment. The diagnosis may be the same diagnosis procedures used in a live run-time environment to save time and costs associated with writing such diagnosis procedures.

Abstract: A circuit arrangement and method facilitate the execution of switch instructions such as Java lookupswitch and tableswitch instructions in hardware through emulation of such instructions using a plurality of conditional branch instructions from the same instruction set as the switch instructions, and which are capable of being directly implemented in hardware. The conditional branch instructions are typically generated by switch instruction handling logic and passed to execution logic capable of natively executing the conditional branch instructions. By emulating a complex switch instruction in switch instruction handling logic using a plurality of conditional branch instructions from the same instruction set, often the amount of custom circuitry needed to fully support a complex switch instruction is substantially reduced from what would be required to natively support the switch instruction in the execution logic of a hardware processor.

Abstract: A method of trace collection in a data processor begins trace data collection even if a trace trigger is received during an interval when a central processing unit is stalled. Trace data collection is deferred if a trace trigger is received during an interval of an invalid instruction boundary until a valid instruction boundary.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Each Target processor is mapped to a Host thread. When a page fault is detected by the Host operating system, it is checked to see if it belongs to the Target system, and if it does, the executing thread transfers its processor identity to a free thread, and then completes processing the page fault. Upon completion, it marks the processes that had been executing on that thread and processor as available for execution, then blocks until activated. Another thread, upon dispatching that process, wakes up the blocked thread and transfers its processor identity to that thread, which continues to execute the interrupted process.

Abstract: A method, apparatus and data construct set for generating simulation data structures which can be used by a modeling system to interface between a PLC and simulator, the construct set encapsulating logic and at least a sub-set of simulation information for a particular resource.

Abstract: A method and system for emulating tape library commands is disclosed. Tape library commands implemented in response to commands received from a data protection application are emulated in a disk based storage medium so that existing data protection applications may be used to copy data to and from the disk based storage medium.

Abstract: Circuit information supplied in an encrypted state (supplied circuit information) is decrypted by a supplied circuit information decrypting section and then encrypted by a stored circuit information encrypting section, to be stored in a storage section as stored circuit information. The stored circuit information is decrypted by a stored circuit information/intermediate data decrypting section and is input to a simulator engine, thereby performing a simulation. Intermediate data generated during the simulation is encrypted by an intermediate data encrypting section, stored in the storage section, decrypted also by the stored circuit information/intermediate data decrypting section, and then input to the simulator engine. In this manner, the simulation is easily performed, while enhancing the confidentiality of the circuit information.

Abstract: A method for emulating one or more file system functions is provided. On a first processing device, a request is received. The request comprises a first data indicating a first file that a file system resident on the first processing device does not support. In an emulation library a second data for emulation of the first file is located. A response based upon the first and second data is formed.

Abstract: An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation file having translation elements corresponding to translation of said identified source elements (86) and having an interface (16) for receiving inputs for modifying said translation.

Abstract: An adapter program couples a legacy operating system to a driver program of an I/O channel which has an incompatible interface to a native operating system. The adapter program includes a translator which receives legacy control structures from the legacy operating system that represents a legacy I/O instruction. The adapter program also includes an interface to the driver program which simulates the native operating system interface. The adapter program further includes an emulator for performing the I/O instruction by interacting with the driver program thru the simulated native operating system interface.

Abstract: A method for modifying operating conditions within a computer which translates instructions from a target instruction set to a host instruction set including the steps of monitoring an event occurring within a component of the computer, counting events occurring within a selected interval, generating an exception if a total of events within the selected interval exceeds a prescribed limit, and responding to the exception by modifying a translated sequence of host instructions.

Abstract: A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.

Abstract: A dynamic binary translator converts input instruction sequences into output instruction sequences that are stored in a translation cache. In order to maintain coherence of the translation cache with the run-time version of the input instructions, translated code is checked by either a conflict detection mechanism or a code-invariance mechanism. For conflict detection, the system preferably uses memory traces generated by the memory management unit of the underlying hardware processor. In order to check for code-invariance, preludes for comparing cached, output instruction sequences with their supposed run-time input instruction equivalents are appended to the cached instructions themselves. Changes in the input sequences then result only in retranslation of instruction sequences in which at least one instruction has changed; this avoids costly total flushes of the translation cache.

Abstract: An apparatus comprising a circuit configured to (i) translate one or more instruction codes of a first instruction set into a sequence of instruction codes of a second instruction set and (ii) present the sequence of instruction codes of the second instruction set in response to a predetermined number of addresses.

Abstract: A system and method for testing the quality of a simulation model for the DUT (device under test) with dynamic constraint solving and test generation for the testing and verification process. The present invention provides such dynamic constraint solving through the creation of a sequence of instructions in a “generator mini-language” (GML). These instructions are then executed in order to provide a correct random solution to any given set of dynamic constraints. The process of execution is preferably performed by a constraint resolution engine, optionally and more preferably implemented as software, which manages the requirements imposed by the constraints on the execution, while simultaneously enabling a random solution to the set of constraints to be provided. Such a constraint resolution engine may optionally be viewed as a type of state machine, in which individual elements of the state machine are more preferably represented by one or more dynamic graph(s).

Abstract: A software emulator for emulating a handheld video game platform such as GAME BOY®, GAME BOY COLOR® and/or GAME BOY ADVANCE® on a low-capability target platform (e.g., a seat-back display for airline or train use, a personal digital assistant, a cell phone) uses a number of features and optimizations to provide high quality graphics and sound that nearly duplicates the game playing experience on the native platform. Some exemplary features include use of bit BLITing, graphics character reformatting, modeling of a native platform liquid crystal display controller using a sequential state machine, and selective skipping of frame display updates if the game play falls behind what would occur on the native platform.

Abstract: In-circuit-emulation of an integrated circuit permits location and identification of optional emulation resources. Each emulation resource is assigned a memory address. The in-circuit-emulation generates a special memory access to memory addresses. If the special memory access corresponds to the address of an emulation resource, the emulation resource responds with an acknowledgement and a corresponding identification number. Nonemulation circuits do not respond to the special memory access. This technique permits manufacture of plural integrated circuits with corresponding sets of emulation resources, where an emulation program can determine the available resources for the particular integrated circuit. The emulation resources preferrably includes a set of emulation resources common to all integrated circuits with predetermined memory addresses and a predetermined identification numbers as well as optional emulation resources.

Abstract: A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin the test program in the uncommitted state. When the random code generators is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Abstract: An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register.

Abstract: A method of debugging code that executes in a multithreaded processor having microengines includes receiving a journal write command and an identification representing a selected one of the microengines from a remote user interface connected to the processor, pausing program execution in the threads executing in the selected microengine, inserting a journal write command at a current program counter in the selected microengine, resuming program execution in the selected microengine, executing a write to a journal routine if program execution in the selected microengine encounters the journal write command and resuming program execution in the microengine.

Abstract: A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined whether a stack underflow exception has occurred and if it has, the move instructions can be flushed, and a micro-code handler algorithm invoked that operates to allow execution of the move instructions in parallel without a stack underflow exception.

Abstract: A test instrument includes a cartridge adapter for receiving existing vehicle diagnostic cartridges programmed for use with an 8-bit microprocessor. The adapter is coupled to a field programmable gate array (FPGA), which is programmed to emulate the operation of the 8-bit microprocessor and supply information to a 32-bit microprocessor coupled to a display and control panel to emulate the operation of a system for which the cartridges have been programmed. Additionally, the 32-bit microprocessor includes programming for new vehicles as well as the ability to read and store updated vehicle information through flash memory to be continuously updated.

Abstract: An information processing system 1 of the present invention includes an information processing terminal 2, an external storage device 3, and a data communication bus 4. The information processing terminal 2 has an I/O control circuit 20, a RISC-type CPU 21, and a code morphing module 22. A code conversion selection sub-module 22a of the code morphing module 22 selects either one of code conversion sub-modules 22b and 22c, based on predetermined information stored in a configuration ROM 30b, which is set in a data memory area 30 of the external storage device 3. The code conversion selection sub-module 22a also switches over the setting used for operations of the information processing terminal 2 to an operating system corresponding to the predetermined information.

Abstract: The present invention utilizes a file locking emulator between an application program and an operating system. The file locking emulator comprises an application program interface and a file lock supervisor. The file locking emulator receives the file locking requests from the application program and generates file requests and file lock query commands. When the application program interface receives a file request it first checks the files lock status and then either returns an error for incompatible file requests or executes the compatible lock request along with any other compatible operation request such as a read, write or truncate file operation. Only code in the file request emulator needs to be rewritten when an application program is ported to different operating systems sharing incompatible but executable processes. In this manner tested code of the application program does not have to be rewritten.

Abstract: In accordance with methods and systems consistent with the present invention, a system that automatically generates Fortran 90 interfaces to Fortran 77 code is provided. These interfaces provide for the use of optional parameters and, because they are written in Fortran 90, also allow for parameter checking. These interfaces are automatically generated to allow a programmer to reap the benefits of Fortran 90 calling without having to rewrite the Fortran 77 underlying code. When generating the interfaces, the method performs an optimization that saves a significant amount of processing time as well as a significant amount of memory. This optimization involves generating the interfaces in such a way as to prevent the compiler from performing a gather and a scatter.

Abstract: A system and method are provided for prioritizing components of an existing network framework. First, a plurality of components required for implementation of a predetermined technology using an existing network framework are provided. Next, a priority listing of the components is complied such that the relative position of the components on the priority listing corresponds to a temporal priority among the components. The existing network framework and the components are pictorially represented. Next, a first component of the existing network framework is indicia coded in order to indicate that the first component must be installed first based on the component's position on the priority listing. Thereafter, a second component and any remaining components of the existing network framework is indicia encoded in order to indicate that the second component and any remaining components must be installed after the first component based on the second component's position on the priority listing.

Abstract: In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation resources to either the emulation function or the application program. Each emulation resource can have three states: unassigned; an emulation state assigned to emulation function; or an application state assigned to the application program. An emulation resource in the unassigned state may be assigned to emulation or application by writing to a predetermined data register. Emulation resources assigned to emulation return to unassigned state upon a test logic reset. Emulation resources assigned to the application return to the unassigned state upon an integrated circuit logic reset.

Abstract: A system is provided which simplifies and speeds up the process of designing a computer system by evaluating the components of the memory hierarchy for any member of a broad family of processors in an application-specific manner. The system uses traces produced by a reference processor in the design space for a particular cache design and characterizes the differences in behavior between the reference processor and an arbitrarily chosen processor. The differences are characterized as a series of dilation parameters which relate to how much the traces would expand because of the substitution of a target processor. In addition, the system characterizes the reference trace using a set of trace parameters that are part of a cache behavior model. The dilation and trace parameters are used to determine the factors for estimating the performance statistics of target processors with specific memory hierarchies.

Abstract: A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.

Abstract: To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as branch prediction, register usage, overflow, a history of branch predictions of groups of branches combined, and a history of register usage for: dynamically modifying instruction parameters of an emulation sequence of instructions; reordering emulated instructions; and adding or changing the dynamic execution information.

Abstract: The objective of the invention is to detect a characteristic in a technical system with reference to model checking. A comparison is made, involving the coordination of several comparative processes, whereby the comparison leads to a result. The comparison is terminated as soon as a comparative process proves that the characteristic is present or not in the appropriate system.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: An electronic device includes an operation processing unit, a main storage unit, a program storing ROM for storing a plurality of divided program codes and for storing loading program codes for loading the program codes to the main storage unit, an information table storing ROM for storing an information table having a description of information about the program codes to be loaded from the program storing ROM to the main storage unit, and a map management element having a description of virtual addresses in the main storage unit at which the program codes stored in the program storage element are mapped. As a result of this construction, only those program codes requiring quick response are loaded without loading all the program codes to the main storage unit and executed promptly, and thus the system activation time can be reduced.

Abstract: The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present invention, a host processor is programmed in its native source and machine code language, and an emulated second processor is programmed in a different native source or machine code language particular to that emulated processor, to allow programming specialists in the different processors to develop common code for use on the same host processor. A multitasking operating system is included to allow time sharing operation between instructions from program code relating to the host processor (e.g., a DSP in the disclosed embodiment), and different program code relating to the emulated processor. The program code relating to the host processor (e.g., DSP) is written in program code which is native to the DSP, while the program code relating to the emulated processor (e.g.

Abstract: A backing out capability backs out a component of a computing environment, while maintaining the availability of the computing environment. In particular, a component of the computing environment which is associated with at least a portion of a unit of work is backed out from one version to another version. In addition, the backed out component is capable of emulating the other version.

Abstract: A software layer (filter driver) residing between software components or application programs running locally or on a client across a network and a persistent store of an operating system provides on-the-fly conversions of persistent information formats. The filter driver determines which format a program expects, and dynamically converts the information from its storage format to the format expected by the program. Conversion includes both data format conversion, and conversion of access semantics. Loadable conversion modules are provided for converting application specific formats due to the potential large number of such formats which can be encountered. The filter driver may change the format that information is stored in based on access history or other system requirements.

Abstract: An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides the native instructions where each native instruction contains at least one register identifier. Flags are provided to each native instruction where each flag indicates whether a register identifier is valid. A bundler checks for dependency among the valid register identifiers in the native instructions.

Abstract: A method of generating a display, or representation, of a simulation model within a graphical user interface (GUI) is described. The simulation model includes a number of objects, which may include state, function, link and modifier objects. The method commences with the display of node representations for at least first and second objects. Thereafter, a link representation, which represents an underlying link object, is selected from a predefined set of link representations to represent a desired relationship condition between the first and second objects. Each link representation of the set is associated with a distinct relationship condition. Each relationship condition may further be defined in terms of an underlying equation. Thereafter, the selected link representation is shown to extend between the respective node representations representing the first and second objects.

Abstract: An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.

Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.

Abstract: A method for emulating a processor of a first endian type on a processor of a second endian type, wherein each memory access address B of string length L is transformed to the address A−B−L+S, wherein A is the total number of bytes allocated to a program, and S is the start address of the program.