Abstract: Software managing long names in an application programming interface receives a request to perform a requested operation on one or more fields, the application comprising a first operation operable to perform the requested operation on at least one field type. The software determines whether the field type of any of the fields is incompatible with the first operation. If the field types of the one or more fields are compatible with the first operation, then the software performs the requested operation on the one or more fields using the first operation. If the software determines that the field type of at least one of the fields is incompatible with the first operation, then it converts the request into a call for a second operation operable to perform the requested operation on the one or more fields and performs the requested operation using the second operation.

Abstract: A two-level transformation scheme to enable a practical fast mesh-free method is disclosed. The first level transformation transforms the original chosen mesh-free shape function to a first transformed mesh-free shape function that preserves Kronecker delta properties. The first transformed mesh-free function allows the essential boundary conditions to be imposed directly. The second-level transformation scheme employs a low pass filter function served as a regularization process that filters out the higher-order terms in the monomial mesh-free approximation obtained from the first-level transformation scheme with desired consistency and completeness conditions. This integration scheme requires only a low-order integration rule comparing to the high order integration rule used in the traditional mesh-free methods. The present invention simplifies the boundary condition treatments and avoids the usage of high-order integration rule and therefore is more practical than the traditional mesh-free methods.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate the proprietary hardware systems of powerful older computers on platforms built using commodity processors. The systems being emulated are often large mainframe computers with large numbers of disks, communications systems and other attached hardware. Because of the size and expense, and also because databases involved must reside in only one location, it is difficult to replicate these systems for testing, development, debug or for providing alternative options to customers. A method for providing a single emulated computer system which provides for multiple views or options in control of the emulator is disclosed in which the options are dependent and selected based on job or user basis. The mechanism continues to provide for high performance and a single copy of the operating system with multiple processes, jobs and threads being emulated under user controlled parameters.

Abstract: A device translates a script command related to teletype (TTY) communications in a network, and generates or receives a TTY signal based on the translated script to test the network.

Abstract: A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function.

Abstract: The present invention provides for native execution of an application on a client using code segments transmitted from a server over a network. The server includes an application code source, and a server code segment manager. The server may also include an application code transformation manager if the code source is not in the native binary format of the client. The client includes a client code segment manager, a code cache linker and manager, a code cache, and a CPU. When the client seeks to execute an application, code segments are transmitted from the server to the client and are stored in the code cache. The CPU then executes the code segments natively. When a code segment branches to a segment not in the cache, control passes to the client code segment manager, which requests the needed code segment from the server code segment manager of the server.

Abstract: Dynamic program analysis is decoupled from execution in virtual computer environments so that program analysis can be performed on a running computer program without affecting or perturbing the workload of the system on which the program is executing. Decoupled dynamic program analysis is enabled by separating execution and analysis into two tasks: (1) recording, where system execution is recorded with minimal interference, and (2) analysis, where the execution is replayed and analyzed. Recording and analysis are carried out on heterogeneous systems so that they can be separately optimized.

Abstract: One embodiment of the present invention provides a system that supports vector operations on a multi-threaded microprocessor. During operation, the system detects a vector instruction in a program. The system maps this vector instruction onto the thread contexts of the multi-threaded microprocessor. As part of the mapping process, the system splits the vector instruction across a set of threads that execute in parallel and generates a set of instructions for the set of threads. This mapping process allows the vector instruction to be executed efficiently across multiple threads.

Abstract: A method is provided to automatically allocate resources of an integrated circuit (IC) to form multipliers in a given design to optimize the use of IC resources. Information about the multipliers in the design is extracted to place the multipliers into a priority order. The priority allows primitives in the IC, like DSP blocks LUTs or MUXCYs to be economically allocated to the multipliers. The ordering criteria can include: (1) a user defined criteria, (2) the number of primitives required to implement a multiplier, or (3) a size of the multiplier operands. This invention further optimally allocates LUTs and MUXCYs when DSP48 blocks are exhausted. The steps for generating a multiplier include: constructing a partial product matrix and minimizing the adders used in the multiplier by minimizing the size of support for the partial products. Either LUTs or MUXCYs are selected depending on the size of support determined.

Abstract: One embodiment is a method for transferring data packets from a virtual computer having a virtual network interface device to a destination over a network, the method includes: (a) storing two or more guest address pointers associated with the data packets in a guest network transmission queue prior to handling the data packets; (b) the virtual network interface device converting the two or more guest address pointers to physical address pointers, and storing the physical address pointers in a physical network transmission queue; and (c) transferring the data packets from the virtual machine of the virtual computer over the network via a physical network interface device based on the physical address pointers in the physical network transmission queue.

Abstract: A construction of the present invention includes a procedure of setting in advance a storing area in a converted instruction storing area table for recording a corresponding relation between a program before conversion and a storing address of a converted program at an initialization processing portion of an emulation program. In setting the storing area, address information on a memory on a portion whose execution frequency is high upon an emulation operation is acquired, and an address that brings about cache conflict on an instruction cache with the portion whose execution frequency is high is excepted and set as an area to store therein a converted instruction.

Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

Abstract: Disclosure of approaches for stabilizing an emulated system. In one approach, a first operating system (OS) is executed on an instruction processor, the first OS including instructions native to the instruction processor. A second OS and a plurality of application programs are emulated on the first OS. The second OS polls the first OS for memory statistics of the first OS. The memory statistics indicate a current state of operating parameters of the memory of the data processing system used by the first OS in managing the data processing system. The second OS controls a number of the application programs allowed to execute in response to the memory statistics provided by the first OS to the second OS.

Abstract: Emulating a computer run time environment as a component of a dynamic binary translation loop that translates target executable code compiled for execution on a target computer to code executable on a host computer of a kind other than the target computer, the target executable code including function calls to functions to be translated. Embodiments of the present invention include: determining, upon encountering in the binary translation loop a function call to a function to be translated, that the function call is a call to a host library function in a host native library; hashing a target executable image of the function to be translated from the target executable code, thereby producing a hash value; and using the hash value as an index to retrieve from a thunk table a host native address of the host library function in the host native library.

Abstract: A forecast class is defined that represents forecasts of different types and identifies relationships of a forecast with various entities related to the forecast.

Abstract: A method to be performed in a process of a computer system initiating physical operations includes receiving, in a computer system, a request to generate a first object and a second object. The first object is to be used in initiating a manufacturing-type operation and the second object is to be used in initiating a warehouse-type operation. The method includes generating the first object and the second object in response to the request. The first and second objects are generated using an object model for physical operations. A computer system includes a first resource and a second resource, and an object generating module configured to generate the first and second objects.

Abstract: A method and apparatus is provided for network node emulation, including a node emulator, comprising a node interface, a memory, and a CPU. A method of generating an emulated network node includes the steps of generating an emulation script using a network node emulation language and operating a computer device according to the emulation script in order to transmit and receive data packets in the computer device. The method comprises receiving an incoming message, transmitting an outgoing message, and recognizing a response requirement in the incoming message. The method comprises responding to the incoming message by transmitting a response outgoing message if the incoming message includes a response requirement.

Abstract: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.

Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.

Abstract: A system comprising a media processing apparatus and a computer where the media processing apparatus emulates a mass storage device and interfaces with the computer is disclosed. In one embodiment the media processing apparatus appears to the computer as a Universal serial bus (USB) mass storage device, and the operating system (OS) on the computer, using its pre-installed USB mass storage device driver, establishes bi-directional communication channel with the media processing apparatus. Thus, the need to develop an OS specific kernel-mode device driver for the media processing apparatus is eliminated. The system may employ a proprietary communication protocol on the USB bus to send and receive data between the computer and the media processing apparatus.

Abstract: Provided are a method, system, and article of manufacture for mapping programming interfaces. A synchronous request for reading data is received. An asynchronous request to fill selected buffers of a plurality of buffers is sent. The synchronous request is responded to with the data from at least one buffer of the plurality of buffers.

Abstract: An apparatus for transcoding encoded content, the encoded content being encoded using a first coding algorithm, with a first interface for communicating with a content sink, the first interface being adapted for receiving a request for content being encoded using a second coding algorithm and for providing a transcoded content being encoded using the second coding algorithm. The apparatus further has a second interface for communicating with the content source, being adapted for providing a request for the encoded content being encoded using the first coding algorithm and for receiving the encoded content being encoded using the first coding algorithm. The apparatus further has a processing unit being adapted for processing the encoded content being encoded using the first coding algorithm to provide the transcoded content being encoded using the second coding algorithm.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: Systems and methods provide for emulating a host architecture in guest firmware. One aspect of the systems and methods comprises determining whether an emulated instruction would cause a transition into a legacy mode. A current execution context is converted into a legacy mode context, and the firmware emulator proceeds to a group of legacy mode instructions in a native mode for the processor. The firmware emulator detects an end instruction and converts the legacy context back to the guest firmware context.

Abstract: The present invention is directed to an extensible console emulator for Hyperion Performance Suite interaction. An emulator system in accordance with an embodiment of the present invention includes: a Hyperion Performance Suite (HPS) console emulator for receiving commands from a source and for performing actions based on the commands; and an HPS Software Development Kit (SDK) for receiving output from the HPS console emulator and for interacting with the HPS; wherein the HPS console emulator provides an interface that allows a user to interact with the HPS via the HPS SDK.

Abstract: Systems, methods, and devices are provided for embodiments of the present invention to describe a technique that provides an operation region and associated operation region handler to define a virtual device for extending the functionality of an existing operating system.

Abstract: The system and method of the present invention “emulates” the TCAM function using a data structure which is stored in an SDRAM device in such way that the size of emulated TCAM is substantially larger than the original TCAM device, thereby allowing the increase of the number of PPE programs which can be resident in memory. The present invention provides a new “emulCAM” algorithm which builds partially on BaRT, but is extended by providing multiple results per hash table entry with flexible assignment to “match-condition-combinations”, by utilizing MUX control vectors for extracting hash index instead of “index-mask-based extraction”, by moving part of CAM function to invoking emulCAM instruction and by providing “Pathological case handling” using multiple emulCAM instructions.

Abstract: A virtualization program for being able to execute a simulation at high speed, allows a native code simulator to have a stack specific to each task that is managed by a multitask OS. Processes of creation, save, restoration and erasure of a context that a target CPU executes by means of a special control register operation is executed by an API provided by the native code simulator. When porting the multitask OS, the source code is altered so as to call the API. A stack specific to a task is assigned at the API and the stack is switched for switching the task to make context switching possible.

Abstract: A method includes generating a storage device request directed to a register of a computing device that is used to access a storage device of the compute device. The method further includes determining with a media redirection device to redirect the storage device request to a storage device connected to a network. The method further includes transmitting over a host bus of the computing device a packetized message representing the storage device request from the media redirection device to a network controller. An associated apparatus is also disclosed.

Abstract: Processor emulation using fragment level translation is disclosed. A target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element may be emulated with a host system having one or more host processors and a host memory. Two or more target system code instructions for the secondary target processor may be grouped into one or more fragments with known starts and ends. A data structure that maps the host memory locations of the starts and ends may be maintained. Each fragment may be translated into a corresponding set of position-independent translated fragments executable by the host system. The translated fragments may be loaded into one or more of the host processors. If a memory layout for target system code corresponding to the one or more fragments has changed, the fragments may be dynamically re-linked, without re-translation, and executed.

Abstract: Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.

Abstract: The conversion of Mobile Display information used in a wide variety of Mobile Devices into Unified Image Formats is disclosed to enable viewing on a desktop computer system in addition to manual and automated testing of Mobile Content. In order to support the variety of Mobile Displays available, and to process the Mobile Display information in real-time, a configurable emulation system may be employed to model the Image Commands being used for each type of available Mobile Display. This emulation system can then provide a representative view of the image as it would be displayed on the Mobile Display, but in a format that can be utilized by other manual or automated systems.

Abstract: In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device controller. The standard block device command is to invoke functionality from the device controller unrelated to the standard block device command. The functionality invoked by the standard block device command is performed by the device controller.

Abstract: Disclosed is a host terminal emulator installed in a client computer to detect a coordinate at which a non-protecting attribute is set from coordinates in CUI screen data when it is received from a host computer, to generate GUI screen data in which GUI parts corresponding to the non-protecting attribute are set at respective coordinates following the detected coordinate, to correct the GUI screen data so as to transform the GUI parts in response to the coordinate at which the non-protecting attribute is set, and to display a screen based on the corrected GUI screen data on a monitor.

Abstract: A computer implemented method, apparatus, and computer usable program code to execute a set of instructions a selected number of times to simulate user loads for a selected number of users. A selected number of traces are obtained in response to executing the set of instructions the selected number of times. The selected number of traces are played back concurrently to simulate the workloads on the database.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses preprogrammed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: Malicious behavior of a computer program is detected using an emulation engine, an event detector and an event analyzer. The emulation engine includes a system emulator configured to emulate, in an isolated computer environment, at least a part of a computer system and a program emulator configured to emulate in the isolated computer environment execution of the computer program, including execution of a plurality of executable components of the computer program, such as execution processes and threads. The event detector is configured to monitor events being generated by two or more of the executable components. The event analyzer is configured to determine, substantially in real time, based at least on one or more events generated by each of two or more of the plurality of executable components whether or not the computer program exhibits malicious behavior, wherein individually one or more of the plurality of executable components may exhibit benign behavior.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.

Abstract: Attempts by drivers of a virtualized legacy computer game to communicate with nonexistent legacy game system hardware are converted into calls to actual hardware of the host computer game system. An access control list (ACL) restricting and/or reducing page permissions is used to explicitly forbid the drivers of the legacy computer game operating on the virtualized legacy computer game platform from writing to the MMIO addresses of the legacy computer game system. When the operating system of the virtualized legacy computer game platform attempts to touch its driver memory by writing to the MMIO addresses, the operating system of the host computer game system perceives a memory access violation, suspends the virtual machine implementing the virtualized computer game platform, and passes the intended write to an exception handler of the host operating system.

Abstract: The invention models software as a physical device with causality. It develops interaction between software and user in a software dynamic system that connects software or modeled software with a software controller. The software is modeled with its input/output behavior on a discrete sampling domain and is controlled by the controller in a modeling software dynamic system while its behavior is observed real-time to identify its model. The modeled software is controlled by the same controller in a simulation software dynamic system, which can be augmented programmatically. Augmentations integrated with the controller construct a software amplifier coupling the modeled software and user interactively and automatically. The modeled software represents domain knowledge simulated in the augmented system as software intelligence. A software-2 including the modeled software, the software controller, and augmentations is created.

Abstract: Architecture for efficient translation and processing of PowerPC guest instructions on an x86 host machine. In an x86-based architecture, signed integer values are projected into the unsigned integer value space for processing by the host using the negation of the left-most (sign) bit. Compare operations are performed in the unsigned space and the compare results are written into the host flags register. Once the compare results are written into the host flags register, the flag values can be read out and used in a table lookup to retrieve the corresponding values for the guest register. The guest flag values are then passed into the guest flags register for processing by the guest application.

Abstract: A simulation device capable of verifying coordinated operation of software and hardware faster and more accurately. The simulation device has a framework including a virtual OS and a virtual CPU to execute software under test. The virtual OS and CPU also serve as a first scheduler that manages an execution schedule for the software under test. The framework includes a communication interface for communication between the software under test and hardware models. A second scheduler manages simulation processes of the framework and the hardware model. The virtual OS and CPU release their execution right to the second scheduler according to the execution schedule of the software under test.

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

Abstract: Switching of the allocation of a device to a guest OS is implemented through transmission of a virtual suspension interrupt to a guest OS in a VMM; a power control notification process module that causes the guest OS to start a return process from a suspended state; a guest power process module that traps a suspension process of the guest OS; an I/O configuration change process module that updates a logical device definition of the VMM in the suspended state of the guest OS; a guest I/O emulation process module that emulates an I/O instruction that is issued by an I/O reconfiguration process module and that is executed when the guest OS has returned from the suspended state, thereby to provide a new logical device configuration to the guest OS.

Abstract: A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of