Abstract: A method for obtaining real-time debug information, e.g., state information and trace information, from an FPGA acting as a virtual microcontroller that is attached to a microcontroller under test. The two devices, the microcontroller and the FPGA execute the same instructions in lock-step with the FPGA acting as an emulator. The FPGA emulates the actual microcontroller and relieves the actual microcontroller from having debug logic installed thereon. FPGA and microcontroller, are coupled using a four pin interface. The FPGA is directly coupled to the PC for both programming and control. The system is implemented such that the microcontroller forwards information regarding I/O reads, interrupt vector information and watchdog information to the FPGA in time before the execution of the next instruction. Thus, the FPGA has an exact copy of the state information of the microcontroller.

Abstract: A method for distributing a program code to a plurality of measuring instruments, each of which is coupled to a control computer respectively via a second bus wit the control computer being coupled to a central computer via a first bus which is, in turn, coupled with a storage-medium reading device and/or an inter-regional network. In this respect, the program code is fed to the central computer by placing a storage medium on which the program code is stored in the storage-medium reading device or by transmitting the program code via the inter-regional network. The program code is transmitted from the central computer to the control computers over the second bus. The control computers transmit the program code via the first bus to the coupled measuring instruments.

Abstract: The various embodiments of the invention relate to analyzing operations of an emulated input-output processor. Instructions native to the first type of instruction processor are emulated on a second-type instruction processor. The instruction processor emulator executes an operating system that includes instructions native to the first type of instruction processor. The operating system includes instructions that write input/output (IO) requests to the memory arrangement in response to IO functions invoked by a program. An IOP emulator that is executable on the second-type processor emulates IOP processing of IO requests from the memory arrangement. The IOP emulator maintains in the memory arrangement a first set of data structures used in processing the IO requests. State data currently contained in the data structures is stored on a retentive storage device, and in response to user input controls, the state data is read from retentive storage and displayed.

Abstract: Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.

Abstract: In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: An analytical virtual machine (AVM) analyzes computer code using a software processor including a register that stores behavior flags indicative of behaviors identified by virtually executing the code within the virtual machine. The AVM includes a sequencer that stores the sequence in which behavior flags are set in the behavior flags register. The AVM analyzes machine performance by emulating execution of the code being analyzed on a fully virtual machine and records the observed behavior. When emulation and analysis are complete, the AVM returns the behavior flags register and sequencer to the real machine and terminates.

Abstract: The present invention relates to a protocol test device including a network processor where the network processor has the following features: protocol levels of a protocol stack can be programmed in it for at least one protocol per software; it is capable of simultaneously processing input signals of different transmission formats, in particular of different clock rates; a plurality of channel ports for network subscribers in parallel architecture; and one standardized interface for a control unit; with the network processor being designed for in-stream operation, i.e. signals arriving at the ports for network subscribers can be redirected to at least one other port for network subscribers, if necessary after a pre-processing step. A host processor which has been programmed for performing protocol emulations and/or simulations is coupled to the network processor, with the signals of the network subscribers forwarded to the channel ports terminating in the protocol test device.

Abstract: An application infa operating system (AIOS) is provided. The AIOS provides an operating platform for integrating, embedding, managing and controlling an application program, wherein a main function thereof is to integrate different application programs which are developed from different information companies and different program designers via different developing languages and tools (e.g., C, C++, database, or Java, etc.) for mutually conversing and swapping data at different space-times through the integration of the present invention, so as to benefit an update, an upgrade and an integration of the application programs, shorten a developing time of integrating a new and a old systems, and save a cost of developing a system for improving a re-use rate of the application programs.

Abstract: A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.

Abstract: A method and system for simulating system conditions at a kernel-level is provided. In one aspect, process identifiers of processes for which simulation is to be performed are transmitted along with simulation pattern or rules from a user-space to a kernel space. Emulator in the kernel space intercepts system calls invoked by processes running in the user space. If the system calls originated from the one or more processes for which emulation was to be performed, return results according to the simulation pattern are generated and returned to the calling process.

Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Abstract: A program authoring system, prior to distributing a program, preprocesses the program to verify the integrity of the program. The program is written in a language that uses a restricted set of data type specific instructions. The program preprocessor, upon verification of the program's integrity, generates a modified version of the program containing an array of supplemental information. The supplemental information consists of data type snapshots of the program stack and local variables immediately prior to execution of each of a set of identified target instructions, which are successors of conditional jump, unconditional jump, branch and flow control instructions, if any, in the program. In client devices that receive programs, a program verifier verifies the integrity of each received program. The instructions of the program are emulated to determine whether any instruction in the program would violate the data type restrictions for that instruction.

Abstract: A system and method for intelligently generating computer code. The system being comprised of a local computer, which is connected to a remote computer via a network system or the Internet and which is capable of exchanging files with the remote computer. The local computer is further comprised of a document manager for transferring files between the local computer and the remote computer and for providing enhanced file management functions. The document manager works in connection with the server module, the site manager and the connectivity layer to connect to remote computers, to transparently exchange files with the remote computer and to manage server profiles and connection information that is related to remote computers and transferred files. Once the file is transferred to the local computer, the editor can modify the code associated with the file; the editor is also capable of creating new files.

Abstract: A method for enabling access to a resource shared by at least two processors over a bus that supports an atomic instruction, wherein a first processor does not support the atomic instruction, the method comprising the steps of providing an atomic instruction emulator coupled to the bus, the atomic instruction emulator including at least two register sets for implementing an atomic instruction; receiving by the emulator over the bus an emulation request from the first processor to perform the atomic instruction on the shared resource, the request including an address location; and performing by the emulator the atomic instruction for the processor using the data and the address location from the request.

Abstract: A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.

Abstract: Program instructions in the form of Java bytecodes may be subject to fixed mappings to processing operations or programmable mappings to processing operations. A system is provided with a fixed mapping hardware interpreter, a programmable mapping hardware interpreter and a software interpreter. The fixed mapping hardware interpreter is able to provide high speed interpretation of the common and simple bytecodes. The programmable mapping hardware interpreter is able to provide high speed interpretation of the simple and performance critical programmable bytecodes with the remaining bytecodes and more complicated bytecodes being handled by the software interpreter.

Abstract: In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some of the processor settings of the processor with processor settings associated with software routines or data structures provided by the guest operating system. The replaced processor settings are written to memory. During this period, when the processor calls a software routine or accesses a data structure associated with the replaced processor setting, the processor will call or access a software routine or access a data structure associated with the guest operating system, bypassing the host operating system and communicating directly with the guest operating system. When the host operating system is to be recoupled to the processor, the processor settings that have been saved to memory are rewritten to the appropriate registers of the processor.

Abstract: A system (10) operable to cache and retrieve flight availability data comprises a cache database (50) for storing flight availability data, an airline cache control (60) for configuring the cache database (50) for a plurality of airlines, a subscriber cache control (70) for configuring the cache database (50) for a plurality of subscribers (20), a cache query utility (80) for interacting with the cache database (50). The system (10) further comprises a data display utility (90) for displaying flight availability data stored in the cache database (50), a success rate utility (100) for tracking statistics associated with use of the cache database (50), and a dual mode processing utility (110) that allows a technician to access flight availability data from either the cache database (50) or a real-time response. The system (10) is preferably used as an intermediary between the subscribers (20) and a plurality of airline servers (25).

Abstract: A method for functional verification of hardware design. First, a first memory region storing a test pattern and a second memory region storing interrupt instructions are provided. Then, the test pattern stored in the first memory is hardware-simulated. If an external interrupt is received during the simulation of the test pattern, the second memory region is accessed and the interrupt instructions are hardware-simulated. Thereafter, the simulated result of the interrupt instructions is self-tested to obtain a first verification result, and the hardware design is verified according to the first verification result.

Abstract: A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set.

Abstract: Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.

Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

Abstract: In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing unit, the commands are divided into groups of test commands. A group of commands is transferred to the emulator server unit and stored in a memory unit of the emulator server unit. The emulator server unit then applies each command of the group of commands to a target processing unit. The resultant data generated as a result of the application of each command is stored in the emulator server unit. When all the commands of the group of commands have been executed by the target processing unit and the resultant data stored in the emulator server unit, the resultant data is transferred to the host processing unit in a single communication bus access.

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract: Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: The invention embeds an emulation module in removable media, for use in replicating an operating environment on a laptop or other remote machines. The emulation module prompts the user to capture environmental settings on an originating machine, such as display settings, network settings, input/output, applications, working data files and other parameters on a removable media. The user may then insert the removable media in a compatible reader attached to the laptop or other secondary or host machine, and upon activation of the emulation module reproduce the screen display, applications, data files and other resources on the host machine. When the user is finished working on the host machine, the emulation module may restore the settings of the operating environment on that machine to their preexisting state. Working data may be synchronized between the originating and host machines.

Abstract: An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.

Abstract: Method and system for automatically backtracing through a testcase file. First the testcase file is accessed. Next, a start line identifier for specifying an instruction line in the testcase file at which to begin processing is received. The instruction line in the testcase file that is specified by the start line identifier is processed first. The previous instruction lines in the testcase file are then processed in a sequential fashion until the beginning of the testcase file is reached.

Abstract: A three-tiered data caching system is used on a distributed computer system comprising hosts connected by a network. The lowest tier comprises management facade software running on each machine that converts a platform-dependent interface written with low-level kernel routines that actually implement the data caching system to platform-independent method calls. The middle tier is a set of federated Java beans that communicate with each other, with the management facades and with the upper tier of the system. The upper tier of the inventive system comprises presentation programs that can be directly manipulated by management personnel to view and control the system. In one embodiment, the federated Java beans can run on any machine in the system and communicate, via the network. A data caching management facade runs on selected hosts and at least one data caching bean also runs on those hosts.

Abstract: A SmartHandle and method is provided which can extend capabilities of the EJB Handle. The SmartHandle can be mapped to a multi-column relational database. Additionally, the SmartHandle enables two EJB Handles to be compared without instantiating the actual EJB objects.

Abstract: Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

Abstract: Disclosed are systems and methods for testing a network service. In one embodiment, a system and a method pertain to sending an initial request to the network service, redirecting a related request sent by the network service to an actual network service such that the related request does not reach the actual network service, emulating operation of the actual network service, and returning at least one response to the network service being tested, the at least one response being responsive to the related request.

Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.

Abstract: A surveillance monitoring and automated reporting method is used for detecting observable changes in data sources over a network, such as the internet, for accessing changing data, such as world wide web content data, and for providing scheduled change detection notifications and results through user defined search criteria for automated monitored search criteria matches on a recurring basis by user defined scheduling. The method extracts content data from the data sources and updates a master database, then detects changes in the content data within the search criteria. Upon detection, the user is notified using graphical interfaces, electronic mail messages, pager messages, or personal data assistant messages.

Abstract: One embodiment of the present invention provides a system for emulating computer viruses and/or malicious software that operates by patching additional program instructions into an emulator in order to aid in detecting a computer virus and/or malicious software within suspect code. During operation, the system loads a first emulator extension into the emulator. This first emulator extension includes program instructions that aid in the process of emulating the suspect code in order to detect a computer virus and/or malicious software. The system also loads the suspect code into an emulator buffer. Next, the system performs an emulation using the first emulator extension and the suspect code. This emulation is performed within an insulated environment in a computer system so that the computer system is insulated from malicious actions of the suspect code. During this emulation, the system determines whether the suspect code is likely to exhibit malicious behavior.

Abstract: A method and apparatus for processing program instructions, utilizes native fixed length instructions that include at least one flag modification enable bit. The flag modification enable bit is typically sent with the operation code and other information in the native instruction and is set to allow updating of one or more flags, such as stored in flag registers, associated with non-native instructions, such as variable length instructions. In addition, a flag modification enable bit may be set to preserve flag bit setting for variable length instructions that are emulated using the fixed length native instructions, to prevent overwriting of flag settings during emulation of variable length instructions.

Abstract: A method and a apparatus for testing a software emulator while executing the software emulator on a target machine architecture are disclosed. The method may include the steps of executing a test program on a target machine architecture, with a test program producing a first output, executing an emulator on the target machine architecture, and the emulator executing the test program under emulation, with the test program producing a second output.

Abstract: Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

Abstract: A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin a test program in the uncommitted state. When the random code generator is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Abstract: A method which simulates the operating speed of an emulated target system with a consistent rate of instruction execution on a plurality of host systems with varied and variable instruction execution speeds. An arbitrary “time quantum” is selected as a referent and is multiplied by the target's speed of instruction cycle execution to determine the quantity of instructions the target system executes in the specified time period. When non-native code is executed on the host system, a counter is used to track the number of instructions executed and to interrupt when that target quantity is reached. A processor-activity-independent timing source is queried to determine the time elapsed; that measurement is then compared to the original “time quantum.” The resulting ratio is a timing reference that is independent of the operating speed characteristics of any particular host system.

Abstract: An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the reconfigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: A method and apparatus for handling masked exceptions that receives an exception from the operating system on which an emulator is running a user program and determines the origin of the exception. If the emulator generated the exception, the emulator handles the exception internally and returns it to the operating system. If the emulated user program generated the exception, the emulator checks the status of the exception type. If that type of exception is blocked, the exception is marked as deferred. Otherwise, the exception is delivered to the user application or marked as pending for later delivery. The system and method can maintain a virtual exception mask to indicate the status of the exception type.

Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

Abstract: A virus detection system (VDS) (400) operates under the control of P-code to detect the presence of a virus in a file (100) having multiple entry points. P-code is an intermediate instruction format that uses primitives to perform certain functions related to the file (100). The VDS (400) executes the P-code, which provides Turing-equivalent capability to the VDS. The VDS (400) has a P-code data file (410) for holding the P-code, a virus definition file (VDF) (412) for holding signatures of known viruses, and an engine (414) for controlling the VDS. The engine (414) contains a P-code interpreter (418) for interpreting the P-code, a scanning module (424) for scanning regions of the file (100) for the virus signatures in the VDF (412), and an emulating module (426) for emulating entry points of the file. When executed, the P-code examines the file (100), posts (514) regions that may be infected by a virus for scanning, and posts (518) entry points that may be infected by a virus for emulating.

Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.