Abstract: The system includes a novel software application interactive representation modeling language, a software application (82) operative to use the modeling language to create, read and modify interactive representation models of the proposed applications, a memory (86) to store requirement data and interactive representation model data, a software application (92) operative to read and update the interactive representation model data across a computer network, a software application (76) operative to maintain a record of the requirements and to administer operation of the system, a software application (78) operative to render interactive representations of the proposed applications in browser readable format, a software application (82) operative to allow multiple instances of other applications to access interactive representation data and requirement data residing in the memory and a software application (84) operative to allow an individual user's interactions with the system to be broadcast across a network

Abstract: An emulation system includes a controller, an emulation calculator, an emulation storage unit, and an interface unit. The emulation calculator includes a device under test (DUT) and emulates the DUT. The emulation storage unit stores emulation data of the DUT emulated by the emulation calculator under the control of the controller. The interface unit distributes and transfers the emulation data to a plurality of computers under the control of the controller.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterable memories may be dynamically mapped.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.

Abstract: A computing device hosts a virtual machine executing a guest that issues guest hardware requests by way of any of a plurality of paths. Such paths include a path to non-existent virtual hardware, where an emulator intercepts and processes such guest hardware request with a corresponding actual hardware command; a path to an instantiated operating system, where the instantiated operating system processes each such guest hardware request with a corresponding actual hardware request; and a path to device hardware, where the device hardware directly processes each such guest hardware request.

Abstract: A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two candidate ROM design modifications are identified. At least one of the candidate ROM design modifications comprises inversion of bit values of data to be stored in the ROM. A plurality of criteria are applied, including at least an amount of yield improvement and a difficulty of implementation associated with each candidate ROM design modification. One of the candidate ROM design modifications is selected based on the application of the criteria. A modified ROM fabrication process is performed to fabricate a ROM according to the selected ROM design modification.

Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

Abstract: An electronic processing boot up system and method are presented. The electronic processing boot up system and method can utilize ROM emulation to store bootstrap instructions and to facilitate reduction of relatively expensive ROM. For example, a ROM emulation system and method utilizes minimal or no ROM. An electronic processing boot up system can include a bus, a processor, and a ROM emulation system for making bootstrap information available to the processor. The processor can issue an initial memory fetch request and the ROM emulation system can perform a ROM emulation process in response to the memory fetch request. The ROM emulation process can include receiving a fetch request for information, translating the fetch request into memory compatible commands for retrieving the information, holding off the processor while the information is retrieved, and forwarding the information in a format compatible with a reply to the memory fetch.

Abstract: A system and method for emulating a telephone driver of a mobile device to assist in the development and testing of mobile telephony applications is described. An emulated telephony driver maintains internal states of a wireless network and characteristics of the mobile device. A wireless network is simulated such that neither a cellular radio nor a mobile subscription are required for handset application development and testing.

Abstract: A method and apparatus are provided for updating or changing configuration data stored in the PROM of a target system, the data being used to configure one or more reprogrammable logic devices such as FPGAs. In one embodiment the apparatus comprises a modem used to communicate remotely with a host system, a shadow PROM for receiving new configuration data intended for use in a target system, an interface for relaying configuration data from the shadow PROM to the target, and means for controlling the components of the update system.

Abstract: A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc. In a further aspect, power supply information can be viewed, such as current and voltage levels, air temperature, fan speed, board temperatures at particular points, etc.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

Abstract: A halt control gatekeeper for an In-Circuit Emulation system. Halt commands are implemented through a gatekeeper forming a portion of a virtual microcontroller that operates in lock-step synchronization with a real microcontroller under test. When a halt command is received, the gatekeeper determines if the microcontroller is in a sleep mode and, if so, appropriately notifies a host computer and queues up a halt command. If the microcontroller is not in a sleep mode, the gatekeeper simply queues a halt command and notifies the host computer when the microcontroller has halted and it is safe to perform debug operations on the virtual microcontroller.

Abstract: A removable magnetic storage device uses an optical drive interface to appear to the operating system as an optical drive. Thus, a removable magnetic drive appears to the operating system as a large optical device similar to DVD/CD, and receives similar functionality. By appearing as an optical device, the removable magnetic storage device can use many features not currently available to magnetic storage devices, such as autorun, multiple volume sets, larger capacity, and efficient space allocation.

Abstract: An event architecture. The event architecture may have a number of event engines for monitoring conditions and also chain logic coupled to the event engines. The event architecture may further have a memory array for storing data to configure the chain logic to configure an execution scheme of the event engines. The chain logic may be re-configured by additional data from the memory to re-configure the execution scheme of the event engines.

Abstract: Techniques are described for emulating an instruction processor for use during the development of a computer system. Specifically, the techniques describe an emulated instruction processor that accurately and efficiently emulates an instruction processor having separate interfaces to fetch op-codes and operands. Further, the emulated instruction processor may provide detection of errors associated with the separate interfaces. By making use of the techniques described herein, detailed information relating to errors associated with the memory architecture may be gathered for use in verifying components within the memory architecture, such as first and second-level caches.

Abstract: A method for routing a message from a source node to a destination node, where the source node and the destination node are connected by a plurality of nodes in a cycle-based system, is disclosed. The method includes generating a maze data structure including the plurality of nodes, where each of the plurality of nodes is associated with a dimension corresponding to time, and routing the message from the source node to the destination node using the dimension corresponding to time.

Abstract: A method for monitoring and emulating privileged instructions of a program that is being executed at a privilege level in a virtual machine is disclosed. A privilege level associated with a received instruction is determined. The instruction privilege level is compared to the program execution privilege level. If the instruction privilege level is valid with respect to the program execution privilege level, the instruction is executed. If the instruction privilege level is invalid with respect to the program execution privilege level: the instruction result is emulated; the number of times the instruction has been received from the program is checked; and if the instruction has been received more than a specified number of times, the instruction is overwritten with one or more instructions with a valid privilege level with respect to the program execution privilege level.

Abstract: A configuration contains a test unit that, during emulation, replaces a program-controlled unit that is used in normal operation of the system containing the program-controlled unit. The test unit has a first program-controlled unit and a second program-controlled unit. The first program-controlled unit contains only some of the components of the program-controlled unit replaced by the test unit, and the second program-controlled unit contains those components of the program-controlled unit replaced by the test unit that are not contained in the first program-controlled unit. In addition, the first program-controlled unit contains a control device which monitors whether one of the components of the first program-controlled unit requests access to a component not present in the first program-controlled unit and which, if this is so, prompts appropriate access to the corresponding component in the second program-controlled unit.

Abstract: A method for obtaining real-time debug information, e.g., state information and trace information, from an FPGA acting as a virtual microcontroller that is attached to a microcontroller under test. The two devices, the microcontroller and the FPGA execute the same instructions in lock-step with the FPGA acting as an emulator. The FPGA emulates the actual microcontroller and relieves the actual microcontroller from having debug logic installed thereon. FPGA and microcontroller, are coupled using a four pin interface. The FPGA is directly coupled to the PC for both programming and control. The system is implemented such that the microcontroller forwards information regarding I/O reads, interrupt vector information and watchdog information to the FPGA in time before the execution of the next instruction. Thus, the FPGA has an exact copy of the state information of the microcontroller.

Abstract: Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.

Abstract: A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.

Abstract: Data streams are generated for tracing target processor activity. When multiple streams are on, they are written at different times into their individual FIFO. It is possible that for a specific stream, the length and fields of the data that should be exported vary. This invention is a scheme to send out only the relevant fields.

Abstract: A watchdog timer control using a gatekeeper in an In-Circuit Emulation system. The In-Circuit Emulation system has a microcontroller operating in lock-step synchronization with a virtual microcontroller. When a watchdog event occurs, the gatekeeper, forming a part of the virtual microcontroller, crowbars the reset line of the virtual microcontroller as well as the real microcontroller. This freezes the state of the virtual microcontroller so that debug operations can be carried out. The gatekeeper operates with its own gatekeeper clock independent of the microcontroller clock. When a watchdog event occurs, the gatekeeper clock is rerouted to the virtual microcontroller to facilitate debug operations of the virtual microcontroller.

Abstract: A system and method for diagnosing an electronic device remotely using a network is provided. The electronic device includes one or more programmable logic devices that are configurable. A diagnostic microcontroller functions to communicate to the programmable logic devices and to communicate to the network. To diagnose the electronic device, communication is established to the network and to a diagnostic/repair center. The diagnostic/repair center selects diagnostic commands and transmits them to the electronic device. The diagnostic microcontroller initiates the diagnostic commands on the one or more programmable logic devices to test their configuration and/or functionality. Test results are collected and transmitted back to the diagnostic/repair center for analysis. Based on the analysis, if appropriate, reconfiguration commands are sent to reconfigure the programmable logic device to correct identified errors.

Abstract: A method and system for simulating system conditions at a kernel-level is provided. In one aspect, process identifiers of processes for which simulation is to be performed are transmitted along with simulation pattern or rules from a user-space to a kernel space. Emulator in the kernel space intercepts system calls invoked by processes running in the user space. If the system calls originated from the one or more processes for which emulation was to be performed, return results according to the simulation pattern are generated and returned to the calling process.

Abstract: A real time functional replicator (10) of a specific integrated circuit comprised of a processing unit and peripherals in order to perform specific digital and/or analog functions controlled by specific software, this specific integrated circuit being designed to be incorporated into a specified application board.

Abstract: Data processing resources are distributively provided to an emulation system to locally and correspondingly generate testing stimuli, and applying the generated testing stimuli to partitions of an IC design to be emulated. In one embodiment, the distributed data processing resources further locally and correspondingly retrieve state data of emulation state circuit elements, analyze the retrieved state data for one or more events, and report the one or more events upon their detection. In one embodiment, the distributed data processing resources are disposed on logic boards of an emulation system. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs of the logic boards.

Abstract: A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.

Abstract: In an integrated circuit, test signals are routed from test points through a hierarchy of distributed multiplexers to output pads. The multiplexers are distributed locally to various regions that are arranged in a hierarchy of regional levels. Thus, each test signal is routed to the locally distributed multiplexer, and only a portion of the test signals reach the top-level multiplexer.

Abstract: In support of data processing emulation, a data processing condition indicated by a predetermined number of digital data processing signals can be detected by applying the digital data processing signals to a lookup table (LUT) that is programmable according to how the digital data processing signals (23) indicate the data processing condition. The lookup table is responsive to said digital data processing signals for determining whether said data processing condition exists.

Abstract: An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM.

Abstract: A method apparatus for hardware and software co-simulation in ASIC development includes developing hardware and software concurrently and co-simulating the hardware and software therebetween via a network while the hardware and software are being developed. The method and apparatus for hardware and software co-simulation allows the software development and testing of hardware and software to start with the design of hardware so as to reduce an overall system development cycle involving ASICs.

Abstract: A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.

Abstract: An emulation and debugging system that includes an in-circuit emulator couplable to a microcontroller. The in-circuit emulator is adapted to execute an event thread in lock-step with the microcontroller. Event information generated as a result of executing the event thread is sampled at selected points and the sampled event information is stored in memory. Trace information is also recorded at the selected points. The sampled event information and the recorded trace information are time-stamped. In one embodiment, a display device is coupled to the in-circuit emulator. The display device is used for displaying analog and/or digital waveforms representing the sampled event information and the recorded trace information. Accordingly, an in-circuit emulator system can also function as an oscilloscope and/or as a logic analyzer, allowing a user to view event and trace information, along with other information, that are generated as part of the debugging process.

Abstract: Communications between a device and a debugging system are effectuated by programming an ICE with a first logic set, which enables the ICE to establish communications with the device and determine a unique identifier thereof. The ICE communicates the device's unique identifier back to a host computer. The host computer matches the unique identifier to a second logic set and a plug-in module. The host computer then programs the ICE with the second logic set and activates the plug-in module. The second logic set allow the ICE and the device to execute program instructions downloaded with the second logic set in lock-step fashion. The plug-in module allows the host computer to interact in the debugging process as necessary. This achieves flexibility, because any ICE may be programmed to communicate with any device.

Abstract: A combined in-circuit emulation system and device programmer. A pod assembly used in an in-circuit emulation system has both a real microcontroller used in the In-Circuit Emulation and debugging process as well as a socket that accommodates a microcontroller to be programmed (a program microcontroller). Programming can be carried out over a single interface that is shared between the microcontroller and the program microcontroller and which is also used to provide communication between the real microcontroller and the In-Circuit Emulation system to carry out emulation functions. In order to assure that the emulation microcontroller does not interfere with the programming process for a microcontroller placed in a programming socket, a special sleep mode is implemented in the emulation microcontroller. This sleep mode is activated by a process that takes place at power on in which the a reset line is released with a specified data line held in a logic high state.

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that has a physical portion and a simulated portion. A target monitor determines when the target processor is attempting to access simulated hardware. The address bus of the microprocessor is monitored to detect an address in the address space of the simulated hardware. Lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware may also indicate simulation. A bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

Abstract: An apparatus for emulating the behavior of an electronic device under test (DUT) includes a computer and one or more resource boards containing emulation resources suitable for emulating portions of the DUT. Each resource board includes transaction device for communicating with one another and with the computer network via data packets transmitted over a packet routing network. The packet routing network and the transaction device on each resource board provide “virtual signal paths” between input and output terminals of resources mounted on separate resource boards. To do so, a transaction device on one resource board sends packets containing data indicating output signal states of local emulation resources to a transaction device on another resource board when then drives signals supplied to input terminals of its local emulation resources to the states indicated by the data conveyed in the packet.

Abstract: One or more processor operations are emulated in a programmable logic device (PLD) (205) that selectively mimics processor behavior by a program that downloads (505) one or more processor operations into the PLD (205). Each operation may be selected (501) and repeated (513) continuously without interruption from any other processor operation unless such interruption is desired to take place. In addition, the PLD (205) has an adjustable or variable clock speed that provides for the ability to select (507) and change (511) the clock speed under which the test circuit is exercised.

Abstract: A data storage system includes memory, a controller, and an Ethernet interface enabling sending and/or receiving Ethernet packets to or from a client system, according to a first protocol. The controller is coupled between the memory and the Ethernet interface and essentially carries out a translation function. Information packets from the client system are translated from a first protocol to a second protocol for use by the memory, and information from the memory is translated from the second protocol to the first protocol for use by the client system as Ethernet packets.

Abstract: An integrated circuit with multiple circuit cores each of which have integrated emulated circuits, and an emulation interface module, such that the integrated circuit has an on-chip debugging system. As cores other than a processor core have integrated emulation circuits, debugging of programs and operations of systems-on-a-chip becomes viable.

Abstract: A power management system and circuit comprising instructions stored in computer memory for the prevention of simultaneous coupling of more than one power source to a device under test (DUT). Instructions stored in memory prevent the simultaneous application of power to the DUT from both the in circuit emulator power grid and an external power source. External power applied to the DUT results in at least one activity signal detected by the computer. If no activity signal appears, a fault condition in the DUT is interpreted. If an activity signal is detected, testing continues under control of Debug Software.

Abstract: Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace information indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.

Abstract: Data processing resources are distributively provided to an emulation system to locally and correspondingly generate configuration signals to configure selected ones of reconfigurable logic and interconnect resources of corresponding collections of reconfigurable logic and interconnect resources, to emulate corresponding partitions of an IC design. In one embodiment, the distributed data processing resources further locally and correspondingly determine inteconnect routing within the selected ones of the reconfigurable logic resources of the corresponding collections of reconfigurable logic resources. In one embodiment, the distributed data processing resources are disposed on logic boards having emulation ICs that include the reconfigurable logic and interconnect resources. In other embodiments, at least some of the distributed data processing resources are disposed on the emulation ICs.

Abstract: A communication device for a target integrated circuit chip having a digital processor, an on-chip emulator for controlling the digital processor and for collecting operation data from the digital processor for communicating to off-chip circuitry, and a target on-chip universal serial bus interface connected to the on-chip emulator, the communication device including an Ethernet port, an universal serial bus port and a further integrated circuit chip having on-chip universal serial bus interface, the on-chip Ethernet interface being connected to the Ethernet port, the interfaces being connected to the processing circuitry for translating between Ethernet protocol data on an Ethernet bus connected to the Ethernet port and universal serial bus data for the target on-chip universal serial bus interface.