Abstract: A method of, and apparatus for, processing the output of a design tool for an integrated circuit, the output relating to a circuit under design. A part of the circuit to be investigated is selected. Information relating to each signal in the selected part of the signal is then selected, and an output containing the selected information for the signals in the selected part of the circuit is generated.

Abstract: A method for efficiently changing the embedded processor type in verification of system-on-chip (SOC) integrated circuit designs containing embedded processors. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. Typically, the embedded processor type changes as SOC designs change. However, changing the processor type may cause errors in verification due to the presence of processor-specific code distributed throughout the verification software. Thus, changing the processor type can entail a substantial re-write of the verification software. In the method according to the present invention, in verification software for verifying a SOC design including an embedded processor, processor-specific code is localized in a processor driver.

Abstract: This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and concurrently solved in a distributed computing environment. This permits the user to use, in a scalable fashion, additional computing resources to rapidly solve difficult equivalent functionality checks. The method allows difficult checks to be solved using (1) a divide-and-conquer approach, (2) by a competitive approach in which many independent attempts are made to solve the same check, or (3) by allocating more resources to solve the difficult check.

Abstract: A method and apparatus are disclosed for verifying the functional design of a system's response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays. A programmable delay.element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array.

Abstract: An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation device can be configured to emulate blocks of memory on a target processor system. Each block of memory responds to three different memory buses and can receive up the three simultaneous memory requests. Arbitration circuitry selects the highest priority memory request for service on each cycle. Each memory block is configured to respond to a block of addresses beginning at a selected starting address. Two blocks of memory can be linked to form a single merged block of memory in which both arbitration circuits operate in lock step by masking a most significant address bit of the block of address selected for the memory block.

Abstract: In-circuit-emulation of an integrated circuit including a digital data processor capable of executing program instructions selectively assigns emulation resources to either the emulation function or the application program. Each emulation resource can have three states: unassigned; an emulation state assigned to emulation function; or an application state assigned to the application program. An emulation resource in the unassigned state may be assigned to emulation or application by writing to a predetermined data register. Emulation resources assigned to emulation return to unassigned state upon a test logic reset. Emulation resources assigned to the application return to the unassigned state upon an integrated circuit logic reset.

Abstract: An apparatus for estimating a microcontroller for executing program estimation and system estimation of the microcontroller comprises, in an estimation device, a data holding unit for holding data rewritably; a processing unit for operating the microcontroller on the basis of a control signal and processing the data; an interface unit for external communication, for taking out the control signal from signals supplied from the external and sending it to the processing unit; and an internal bus monitoring unit for monitoring the state of an internal bus connecting mutually the data holding unit, the processing unit and the interface unit for external communication. This apparatus is constituted in such a manner that the data obtained by writing the state of the internal bus, ant the time when the microcontroller is operated, into the internal bus monitoring unit is inputted to the data holding unit, or is sent to the external, via the interface unit for external communication.

Abstract: A cross-platform development system includes a computing device that generates an image of an operating system, and a software development peripheral connected to the computing device that runs the operating system corresponding to the image. The software development peripheral communicates information, such as image data, generated by the operating system back to the computing device where the information is displayed on a display device connected to the computing device.

Abstract: The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the proper test method selected by an established hierarchy of methods. In one embodiment, an impedance is shown for control purposes between test methods.

Abstract: An apparatus, program product and method incorporate into an enhanced programmable core model an embedded debug monitor to provide integrated graphical debugging functionality in the model. The debug monitor supports the performance of one or more debug operations on the programmable core model during simulation thereof. In addition, the debug monitor is configured to receive a debug parameter from a user through a graphical user interface, and report a result of the debug operation to a user via the graphical user interface. Through the use of a graphical user interface, interaction with a user is greatly facilitated. Moreover, by embedding the debug monitor within the programmable core model, a completely integrated simulation and debug environment may be provided to a user, with debugging functionality similar to that available to software developers and hardware-based processor designers. As a result, validation of a model's performance can be performed more efficiently and with less effort.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.

Abstract: A procedure and processor are disclosed for avoiding lengthy delays in debug procedures during access by a memory mapped peripheral device. The processor includes in-circuit emulation means comprising one or more scan chains or serially connected registers for access by an external host computer system. The procedure comprises: a) the host computer system carrying out a debug procedure via said scan chains, and selectively interrupting such debug procedure for access to a peripheral memory mapped device; b) the host computer system writing into an area or memory of the processor a program for reading and/or writing data at a specified memory location; and c) the host computer system causing said processor to run said program, and then to return to said debug procedure.

Abstract: An interface system enables conventional software applications running on host computers linked via a network to communicate with in-circuit emulators having component ports accessed through the network. The interface system represents each in-circuit emulator as a separate communication object model (COM) object. Each COM object has a set of interfaces, with each interface including a set of methods for carrying out various in-circuit emulator programming and data transfer functions. To communicate with an emulator, a software application links to an instance of the emulator's COM object and thereafter makes calls to the methods included in the object's interfaces. The system permits an application linking to an instance of an in-circuit emulator's COM object to optionally block other applications from linking to other instances of that COM object to prevent conflicts in control over the in-circuit emulator.

Abstract: To check operation of a circuit to be checked connected to a bus to which at least one master circuit and at least one slave circuit are connected, a model is connected to a bus in place of a master circuit or a slave circuit and cause given signals to be outputted at given timing for checking the operation of the circuit to be checked. Especially, by causing various data transfer to occur at random timing by a plurality of models, it is early to cause severer than actual conditions to take place easily, enabling to enhance efficiency of checking. For example, when checking operation of a bus arbiter, a plurality of master models are connected in place of a plurality of master circuits to cause a request of bus accessibility to be outputted from each master model at random timing to check arbitration operation of a bus arbiter.

Abstract: An apparatus in an ICE system is disclosed, which uses the buses connected to the ICE to access data from an external memory. The apparatus includes a first buffer, a second buffer, a higher-bit address bus, a lower-bit-address/data multiplexing bus, a lower-bit address bus, and a control unit. The first buffer transmits the signal of the higher-bit address bus of the ICE to the higher-bit address bus when the buffer enable signal is enabled. The second buffer transmits or receives the signal of the address/data multiplexing bus of the ICE to and from the lower-bit-address/data multiplexing bus when the buffer enable signal is enabled. The control unit receives control signals of the ICE and generates the buffer enable signal and the direction control signal. The buffer enable signal is enabled when an address-latch-enable signal of the ICE is enabled, and is disabled when a higher-bit address bus signal of the ICE does not fall within a predetermined range.

Abstract: An apparatus for optimal control of distributed actuator and sensor arrays includes a control system having a state estimator including an operator which acts on estimation error through convolution with respect to a spatial variable to generate a state estimate, and a control output generator which applies a control operator to the state estimate through convolution with respect to the spatial variable. A method of designing an optimized control system includes the steps of obtaining a system model, computing a transform of the model with respect to the spatial domain, solving linear matrix inequalities to generate auxiliary variables, performing an inverse transform on the auxiliary variables, and computing an estimator operator and a control operator for a model-based estimator control system.

Abstract: A method and system for characterizing and validating the timing of LVS circuits. In particular, based upon an input of a topological description of an LVS circuit (e.g., a netlist) and other circuit parameters such as a clock specification or any mutex or logical correlations between inputs and ignored devices, an output of all paths and arcs from primary inputs to sense amplifier inputs is generated. A complete set of valid input vectors required to exercise all paths is generated. These vectors may then be exhaustively simulated to provide input waveforms to all sense amplifiers.

Abstract: In an evaluation system for evaluating a target board produced for use with a microprocessor, an evaluation microcomputer is connected between the target board and an evaluation tool. In the evaluation microcomputer: an emulation circuit emulates functions of the microprocessor, and supplies an emulation result to the evaluation tool through an interface circuit; the interface circuit interfaces the emulation circuit with the evaluation tool; and a data storing circuit stores data relating to the microprocessor. The emulation circuit and the interface circuit are powered by the target board, and the data storing circuit is powered by the evaluation tool. Alternatively, when the interface circuit further has the function of the data storing circuit, the interface circuit is powered by the evaluation tool.

Abstract: A Test and debug processor that can execute JTAG scans without the involvement of an external CPU or dedicated hardware. The processor includes a JTAG-bus controller logic, a JTAG port coupled to the JTAG-bus controller logic, memory capable of storing JTAG instructions, and an instruction decoding unit capable of fetching or requesting JTAG instructions from the memory. During use, the JTAG scan functions are encoded in instructions that are natively executable by the processor hardware without software interpretation. The instructions are then stored in a memory structure, fetched and executed directly by the processor. The instruction could optionally include the end-state of the bus after the operation, information about the bit count of the data to be scanned, information about the location of the data to be sent out of the JTAG port and also the location to store the received information from the test subject.

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Abstract: The present invention is used to verify an equivalence between a software for realizing a predetermined function and a hardware data created according to the software and constituting a hardware operating identically as a processing by the software. The LSI verification method of the present invention simulates each of the hardware data and the software and compares, according to a signal I/O condition defining operation of the hardware, an I/O signal state as a simulation result by the hardware data to a software variable as a simulation result of the software for verification of the equivalent.

Abstract: A program-controlled unit has debug resources for monitoring the operations proceeding within the program-controlled unit. The program-controlled unit described is distinguished by the fact that the debug resources contain a CPU, and/or that a portion of the debug resources is provided for monitoring the operations proceeding within the remainder of the debug resources. Debug resources constructed in this way make it possible for errors occurring in program-controlled units to be localized and eliminated rapidly and simply under all circumstances.

Abstract: A software controlled device comprises a central processing unit (CPU) and a memory unit. The CPU comprises a digital signature algorithm and a private key; wherein the memory unit stores run-time binary code. A digital signature is derived during manufacture from the digital signature algorithm, the private key and the run time binary code, then stored in the CPU and, in use, the CPU recalculates the digital signature and compares it with the stored digital signature, such that if the two signatures are not identical, the run-time code will not execute. A method of preventing fraudulent use of an electronic device comprising a central processing unit (CPU) and a memory unit is also provided.

Abstract: A microcomputer including a built-in storage portion capable of executing an evaluation program by an ICE through a simple operation also when the evaluation program cannot be written in the built-in ROM is obtained. A debugging circuit (2) outputs a reset vector selection signal (S2) indicating generation of a reset vector (V1/V2) in response to a control signal (S1) indicating a normal mode/a RAM starting mode, and a reset circuit (3) generates a reset vector (V1/V2) indicating a starting address (A1/A2) after reset cancellation by indication of the reset vector selection signal (S2). The microcomputer can be set to execute the evaluation program from the starting address (A2) on a RAM area (5) after reset cancellation by registering the evaluation program (start address=starting address (A2)) in the RAM area (5) from the ICE through the debugging circuit (2) and thereafter supplying a control signal (S1) indicating the RAM starting mode to the debugging circuit (2).

Abstract: A system for integrating an emulator and a processor, the system comprises a device for integrating the emulator and the processor, the emulator emulating the processor; an ICE universal controller connecting to the device for communicating with the emulator and obtaining an emulation result from the emulator; a computer connecting to the ICE universal controller for observing the emulation result and controlling the ICE universal controller.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: A debug circuit (2) and a microcomputer incorporating the debug circuit (2). The debug circuit (2) is capable of receiving a trace event from a functional block A as long as a CPU (5) does not generate any trace event, and capable of receiving the trace event from the functional block A in synchronization with a standard clock signal CLK used in the CPU (5) when the reception of the trace event from the functional block A is permitted.

Abstract: A method of and an apparatus for designing a test environment and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emulating an actual test environment. A virtual device emulating the actual electronic device is implanted into the virtual test environment, and that virtual device is stimulated with an input test signal emulating the actual input signal applied to the actual electronic device in the actual test environment. The integrity of the input test signal and the resulting output signal is evaluated. An adjustment might be made to the virtual calibration of the virtual test environment and/or to the virtual device, or both, and the design of the actual device might be improved. The invention can be implemented on a properly programmed general purpose processing system or on a special purpose system.

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found.

Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to short-circuit the address translation. In a system additionally supporting segments framing portions of virtual memory, the direct page table pointers are associated with segment registers and point to the page table entry corresponding to the first location in a segment. Direct page table pointers are invalidated when underlying virtual memory management tables are modified.

Abstract: The present invention discloses an emulation system and method. The present invention comprises a control FPGA with a bi-direction interface means, a target FPGA, a microcomputer, and a data storage unit.

Abstract: Emulation information indicative of internal operations of a data processor can be provided for use by an apparatus external to the data processor. A stream of emulation trace infonnation indicative of data processing operations performed by the data processor is provided. A stream of timing information indicative of operation of a clock used by the data processor to perform data processing operations is also provided. The trace stream and the timing stream have inserted therein information indicative of a temporal relationship between the trace information and the timing information.

Abstract: There is disclosed a method of communicating with an integrated circuit chip having plural components thereon, the components including digital processing circuitry and an on-chip emulator connected to the digital processing circuitry for initiating command and control sequences for the digital processing circuitry in response to externally applied signals or in response to detected states of the digital processing circuitry.

Abstract: An apparatus and method for verifying a logic function of a semiconductor chip in a logic chip emulation environment where a processing engine and a target interface engine interact with each other. The apparatus in accordance with the present invention generally includes a processing engine for executing a software algorithm corresponding to the logic design of the target chip, and a target interface engine interfacing with the target system for transmitting/receiving pin signals to/from the target system. The software algorithm has one or more software variables, and the transmission/reception of the pin signals by the target interface engine occurs with the execution of the software algorithm by the processing engine. The software variable and the pin signals are time-variant with the execution of the algorithm.

Abstract: A device for verifying the operation of a functional logic circuit such as a VLSI implements a circuit fictionally equivalent to the functional circuit, and supplies electric signals thereto. The device includes an equivalent logic circuit, a functional equivalent board and an input/output section. The equivalent logic circuit, mounted on an LSI socket board, is composed of programmable logic elements that implement logic specifications of a first part of the verified functional logic circuit to the level of the gate circuit diagram of the first part. The functional equivalent board implements a circuit functionally equivalent to the other part of the functional circuit in point of input and output. The functional equivalent board implements memory and arithmetic operation circuits.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port for off-chip communication, the chip further comprising an on-chip interface having a first port connected to said communication port of said on-chip emulation device and a second port for connection to a non-proprietary bus wherein said interface is operable to convert between a format suitable for said on-chip emulation device and a format suitable for said non-proprietary bus.

Abstract: A circuit configuration allowing for in-circuit emulation, comprising a memory containing an operating program; and a first and second microcontrolller. Each microcontroller has a computer core, at least five external connection ports, and a setable connecting device selectively connecting the computer core to the connection ports. A first connection port of the first microcontroller is connected to a first connection port of the second microcontroller. The memory is connected to at least a second one of the connection ports of the first microcontroller. The connecting devices are set to provide the computer core of the first microcontroller with the operating program contained in the memory, and are set to provide data transfer between the first connection port of the first microcontroller and the first connection port of the second microcontroller.

Abstract: A digital television satellite or cable system broadcasts to receiver/decoders which also receive control information (control programs, i.e. applications) to allow such tasks as reviewing television programme listings, setting up home banking interactions, and answering quiz questions connected with programmes being transmitted. The invention provides a method of developing such control programs on a workstation 4013. The workstation is coupled to a receiver/decoder-type unit 2021 which substantially duplicates the receiver/decoder with a television set 2023 coupled thereto. Control programs are developed including control statements responsive to signals from the workstation and test statements which return signals to the workstation. The program is passed to the receiver/decoder-type unit, and a synthetic broadcast digital television signal is generated (at 4045) and fed to the receiver/decoder-type unit.

Abstract: A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first aspect, the embedded CPU system includes a CPU and a plurality of devices which are accessible by the CPU, via a device control register bus. The embedded CPU system includes logic coupled to the device control register bus for allowing access to the devices within the embedded CPU system by an external CPU. In a preferred embodiment the present invention provides a highly integrated set top box controller with a processor performance that services the low-end with the added advantage of additional performance with the EMCPU operating as an I/O assist processor to the EXCPU. When the EXCPU operates as the primary processor these two processors serve as a high end set top box controller.

Abstract: An debug and emulation system includes a target device embodied in a single integrated circuit. The target device includes a function clock circuit and an operation circuit operating in synchronism with the function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. The trace data is sensed in synchronism with the oscillator clock. The emulator is coupled to the target device to control the clock selection.

Abstract: A first supply voltage is applied to a computer-controlled apparatus and to a first block of a simulator, while a second supply voltage is applied to a designator unit and to a second block of the simulator. The operation of the computer-controlled apparatus is simulated by the simulator in response to instruction signals supplied from the designator unit.

Abstract: Trace data outputted by an evaluation chip of a tracing circuit of an in-circuit emulator are successively written into a current bank of a trace memory cyclically. When trace data that matches a designated access event is outputted by the evaluation chip, the trace data corresponding to the designated access event is written into the current bank (#1) of the trace memory and thereafter the write pointer is moved to the front end of the next bank (#2). Thereafter, the trace data writing into the current bank (#2) is repeated cyclically. When trace data that matches a designated fetch event is outputted by the evaluation chip, the trace data corresponding to the designated fetch event is written into the current bank (#2) of the trace memory and thereafter the write pointer is moved to the front end of the next bank (#3).

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator.

Abstract: A technique for system-wide emulation of an embedded system. The technique includes the addition of emulation software and an intermediary operating system. The intermediary operating system is used to avoid modification of system software. The emulation software is used to generate objects that simulate hardware features of the embedded system and to signal when control features of these objects have been selected.

Abstract: A system which provides real-time code coverage data on a memory monitored by the system, the code coverage data providing information regarding accesses to the monitored memory, the monitored memory being connected to address lines and data lines, the system comprising: a code coverage memory, the code coverage memory having address inputs and data inputs, wherein signals on the address lines connected to the monitored memory are received at the address inputs of said code coverage memory; and a code coverage control circuit for providing predetermined code coverage data to the data inputs of the code coverage memory. In a preferred embodiment, the code coverage memory is comprised of multiple locations, each of the locations having a predetermined width, and where the code coverage control circuit is adapted to provide predetermined code coverage data in real-time concurrently with the accesses to the monitored memory.

Abstract: A method of, and apparatus for, obtaining a representation of an electrical circuit (400) suitable for time-domain simulation. The electrical circuit comprises a physical structure (102), which is modelled using electromagnetic field analysis, and also comprises a remainder circuit (104) of circuit components which are interconnected with the physical structure. The electromagnetic field analysis is capable of generating at least a high-frequency equivalent circuit which is representative of the physical structure (102) and is valid at the operating frequency of the circuit but not at DC. The method comprises including a set of DC sources (E1 to Ek) to ensure that, in a time-domain simulation, improved DC bias conditions are provided for any non-linear components in the remainder circuit. The DC sources may be voltage sources in each interconnection, current sources between each interconnection and a zero voltage reference interconnection, or a combination of the two.

Abstract: A test system for functionally testing disk drives over a wide range of power conditions. The system simulates the power conditions using a computer controlled system architecture featuring several major components. The first of these components is a computer enhanced with features allowing the computer to communicate with disk drives having either IDE or Small Computer System Interface (SCSI) formats. The computer communicates with a second component termed the programmable power supply (PPS) and a third component having simulation circuitry termed universal power simulator, or UPS. The computer uses a combination of hardware and software to create simulated power conditions which are used to test the disk drives for correct operation and to glean out defective drives. The UPS is responsive to control signals from the host computer and the PPS and sends simulated power signals to the disk drives under test.

Abstract: A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator.