Abstract: A multi-valued logic emulation system reads a specifying value for specifying with which value, logic emulation is performed, and represents the logic value by a plurality of physical signal lines equal to (Log2 a raised integer of the specifying value). Then, the system performs multi-value supporting synthesis and automatic place/automatic route processing, and maps resulting information to a programmable gate array, thereby making it possible to execute multi-valued logic emulation.

Abstract: A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data processor allows the internal registers used during execution of a user program to be examined. Debug operation can be initiated via debug instruction which replaces an existing instruction in the user code, the replaced instruction being held in a special purpose register such that it can be executed on return from the debug mode. Single step operation of the data processor can be performed in debug mode and data and instructions can be exchanged with the data processor in debug mode, optionally via a single pin so as not to sacrifice any user resources.

Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: An RS232C driver inside target firmware controls an RS232C interface. An OS debugger steals an input to and an output from another function block that is the actual target firmware, and exchanges that input and output with the RS232C driver 1005. This configuration makes it possible to easily connect a device that executes the target firmware to, for example, a personal computer, using a general purpose RS232C interface, and makes it possible to easily obtain debugging operation using the PC side debugger.

Abstract: A testing integrated circuit device comprises a plurality of external terminals for being connected to a circuit board, a plurality of internal terminals provided corresponding to the external terminals each of which is provided with a plurality of connection terminals including a signal terminal, and a plurality of signal terminal setting. corresponding to the internal terminals for setting characteristics of the signal terminals. The connection terminals are provided so that a desired one of the connection terminals in the internal terminal can be connected to the corresponding external terminal.

Abstract: A data processor is provided in which an embedded emulator communicates with a control emulation system using a serial communications link involving one pin of the data processor package.

Abstract: A multiple use chip socket supporting more than one type of permanent storage chip in a single chip socket is disclosed. The multiple use chip socket provides a plurality of address bit lines which are used to specify an address of a particular location within a memory device installed in the socket. In general, the number of address bit lines directly coupled to the socket correspond to the number of address bit lines required for the smallest memory device to be installed in the socket. Additional address bit lines are coupled to control logic of the present invention. The control logic selectively applies addressing signals to the chip socket depending on the type of memory device inserted in the socket. As part of the initialization process, the processing logic of the present invention first determines if an access to a device installed in the chip socket is required by a circuit board as part of its initialization or boot process.

Abstract: A method of providing redundancy in a LAN Emulation network in the event an LES fails. The method is light in that it does not require complicated database synchronizations between LECSs and their associated complex message protocol exchanges. The method comprises defining a plurality of LESs per ELAN, but permitting only one of the LESs to be active at any one moment in time. All the LECSs are configured with the same Topology Database which include the all the potential LESs for each ELAN. The LECSs try to connect to each LES and the results are logged. The operative LESs having the highest priority is chosen as the active LES whereby all LECs get assigned to the active LES. When the active LES fails the LECs attempt a new connection to LECs. The LECs assigns the LECs to another operative LES in the database list. All the LECs previously connected to the failed LES, are attached to the new LES assigned by the LECs and communications are reestablished with the new LES.

Abstract: A method and system are disclosed that utilize the expressiveness of hardware description languages for providing comprehensive runtime monitoring during hardware accelerated simulation of a digital circuit design. According to the present invention a design entity forming part of a digital circuit design that will be translated and assembled into a simulation executable model, is described utilizing a hardware description language. Next, an instrumentation entity designed to send a failure signal in response to detecting an occurrence of a failure event within the simulation executable model is described utilizing the same hardware description language. Thereafter, a simulation test is initiated on the simulation executable model utilizing a hardware simulator. Finally, during the simulation test, and in response to receiving a failure signal from the instrumentation entity, the simulation test is terminated such that the failure event may be efficiently identified and diagnosed.

Abstract: A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (32) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (22). The simulation process (22) and the hardware pod (32) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (20) in the disengaged mode commences if a disengagement event occurs in the hardware pod (32). Operation of the system (20) in the disengaged mode terminates if the simulation process (22) sends stimulation-control data to the hardware pod (32), or if the hardware pod (32) sends response data to the simulation process (22).

Abstract: Accordingly, provided is an apparatus and method for generating a computer system interrupt emulation having the effect of a hardwired interrupt. A service processor with a test circuit interface can be coupled to an integrated circuit, which has a test circuit with an access to a register of the integrated circuit. A program, executable by the processor, responds to an interrupt request by instructing the processor to save a system state of the integrated circuit and to set a system state of the integrated circuit. The method for emulating an interrupt of an integrated circuit provides for receiving an interrupt request. A register of an integrated circuit is then accessed through a test circuit of the integrated circuit. The contents of the register are saved to a storage location, and the register is then set to a state responsive to the interrupt request. The interrupt request may be made locally or remotely.

Abstract: The microcomputer provides with surroundings where data in a RAM can be monitored on the outside without employing an external bus. When a command requesting accessing to a RAM is received from an external monitor, a real time debugger built in the microcomputer confirms that a CPU is not accessing the RAM, and accesses the RAM. On the other hand, when accessing to an emROM, which emulates an actual ROM, is requested from the monitor, the real time debugger accesses one of emROMs which is not being used by the CPU at present.

Abstract: A method for emulating a non-bond-out version of a microcontroller that has a standard port, a microcontroller allowing such emulating, and a system for executing the emulation. For emulating a non-bond-out version of a microcontroller, a standard port is used to multiplex among user data and program store addresses. An external register is connected to the port for latching therein program store addresses. The microcontroller is synchronized according to a machine cycle that has a plurality of states, each of which comprises at least two clock pulses. The standard port is used for outputting mutually exclusive parts of a program store address in contiguous sections of a machine state of external parallel evaluation.

Abstract: An inverse assembler that uses a memory map as a substitute for some microprocessor status signals. This reduces the number of signals needed from a microprocessor to perform disassembly.

Abstract: A method of initializing a CPU (14) to run emulation code from a debugger (11). Emulation logic (13) associated with the CPU (14) has a finite state machine (13b) with three modes: a reset mode in which no requests from said debugger or said CPU are serviced, a normal mode in which requests from said debugger are given priority, and a start-up mode in which only requests from said debugger are serviced. For initialization, the finite state machine (13b) is placed in reset mode and held in reset while the start-up mode is requested. When the reset mode is released the start-up mode is immediately serviced. This permits an initialization state to be cleanly applied to the CPU (14).

Abstract: An in-system debugging (ISD) capability is incorporated into a production microcontroller. The ISD capability is incorporated without the costly addition of any extra pins to read out the data for debugging by using the oscillator pins of the production microcontroller to read out the data. Building such an ISD capability into the microcontroller, enables debugging to be performed on the actual production board (instead of a special debug board) having the actual production microcontroller (instead of a bond-out microcontroller). This allows designers to debug programming using the actual production system instead of an emulation system.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.

Abstract: An information processing system such as a microprocessor includes a processor core, a debug register circuit and a trace unit. The processor core is for processing information according to a program. The program includes a plurality of instructions for execution by the processor core. Each of the plurality of instructions has a corresponding address. The debug register circuit is coupled to the processor core. The debug register circuit includes a dedicated initiate trace breakpoint register coupled to receive and store an initiate trace address and a dedicated terminate trace breakpoint register coupled to receive and store a terminate trace address. The trace unit is coupled to the debug register circuit and the processor core. The trace unit initiates a program trace responsive to the program accessing the initiate trace address. The trace unit terminates the program trace responsive to the program accessing the terminate trace address.

Abstract: An interactive graphical software tool is provided that can be used to report the configuration data (i.e., the state of the various configuration bits) in a programmed device as well as to probe and stimulate circuits in the programmed device. A graphical or textual representation of the configuration data can be displayed. When used with a programmable device having addressable flip-flops, such as a member of the Xilinx XC6200 family, one embodiment of the invention can change the state of any addressable flip-flop in the configured device. The graphical tool of the invention is preferably implemented using a high level programming language such as Java and features a graphical point and click user interface, remote access to hardware, and symbolic debug capability. According to another aspect of the invention, data can be written into a programmable device using an interactive software tool and a hardware device designed to interface with the programmable device.

Abstract: A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator.

Abstract: A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can "swap the order" of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells.

Abstract: An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit. One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks. The buffers isolate the plurality of reconfigurable logic networks from one another. The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers. The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network. The integrated circuit may also comprise a local memory. The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor.

Abstract: Emulation modules containing an increased number of emulation processors are logically reconfigured into a plurality of planes which are interconnected by means of multiplexors to avoid I/O pinout complexities introduced by the increase in the number of emulation processors. The emulation processors present on an emulation module chip or board are partitioned into a plurality N of different planes or arrays which are interconnected with one another and with off-chip or off-board components via N-way multiplexors. One set of multiplexors provides an input function for each of the planes. Another N-way multiplexor provides output functionality for these same set of planes. An output driver for off-board or chip communication is connected to an N-way output multiplexor. Likewise, an input receiver receives input from off-chip or off-board sources and supplies this signal to all of the N-way multiplexors which provide input signals to the various arrays of emulation processors.

Abstract: A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device. The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycles on a simulated hardware component. The system further includes a simulator library for modeling and verifying hardware components of a desired electronic device. The simulator library includes built-in models and routines for simulating multiple internal hardware components. The simulator library is used with the cycle-accurate simulator. The system also includes a simulation Application Program Interface ("API") for allowing user-customized model and routines of internal and external hardware components to be used with the cycle-accurate simulator. The system can be used to design, verify and develop on-chip and off-chip components for a system-on-a-chip used in a desired electrical device.