Abstract: The disclosure relates to a method for estimating the number of leader vectors with norm lp equal to r?p,d, of dimension d, having co-ordinates which are lower than, or equal to k. The method is characterized in that r p delta, d is determined by the sum of the results of a function T(Xi) for i varying between 1 and d, the function T(Xi) providing, for at least some of the leader vectors, the result of the division of the co-ordinate Xi raised to the power p by a delta precision factor, the result of the division being rounded to the nearest whole number. The method does not comprise a step of determining leader vectors.

Abstract: A computer-implemented method includes dividing an image into one or more image channels for image compression. The method also includes dividing one or more of the image channels into one or more blocks. At least one of the blocks includes floating point representations of pixel values included in the block. The method also includes converting the floating point representations of pixel values into integer representations such that the sign of each floating point representation is preserved. The method also includes storing the difference of adjacent integer representations as a compressed version of the image.

Abstract: Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division.

Abstract: A method for decoding run-length encoded (RLE) data includes the steps of receiving the RLE data and storing a predetermined value (e.g., zero) in each of a plurality of consecutively-accessible storage locations of a buffer. The method further includes writing a first value different than the predetermined value to a first storage location based on the RLE data, jumping over (i.e., skipping) a number of the consecutively-accessible storage locations from the first storage location to a next storage location based on the RLE data, and writing a next value different than the predetermined value to the next storage location based on the RLE data. In the case of JPEG, the values stored in the storage locations of the buffer are quantized coefficients associated with a block of image data. A run-length decoder is also described.

Abstract: The LLMICT transform matrices are orthogonal, hence their inverses are their transpose. The LLMICT transform matrices are integer matrices, which can be implemented with high precision eliminating the drift error in video coding. The fast algorithms for the LLMICT transform are found, thus allowing a lower requirement on computation hardware. The LLMICT is also found to have high transform coding gain due to its similarity to the DCT.

Abstract: The present application addresses a fundamental problem in the design of computing systems, that of minimizing the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.

Abstract: An integrated memory controller (IMC) may sit on the main CPU bus or a high speed system peripheral bus and couple to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for format definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.

Abstract: Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: An image coding method including: binarizing a first component and a second component which are included in last position information, to generate a first binary signal and a second binary signal, respectively; coding, by first arithmetic coding, a first partial signal which is a part of the first binary signal and a second partial signal which a part of the second binary signal, and coding, by second arithmetic coding, a third partial signal which is another part of the first binary signal and a fourth partial signal which is another part of the second binary signal; and placing the coded first through fourth partial signals in a bit stream, wherein in the placing, (i) the coded second partial signal is placed next to the coded first partial signal, or (ii) the coded fourth partial signal is placed next to the coded third partial signal.

Abstract: A method of compressing data output from an acceleration measurement means configured to be transported, carried or worn by a user is provided. Acceleration values indicative of the movement of the user are measured at a first frequency and values representative of the measured acceleration values are generated at a second frequency, which is lower than the first frequency. The step of generating comprises: defining a plurality of time windows, each time window containing a plurality of measured acceleration values; and applying a transformation to the measured acceleration values within each time window to generate a plurality of transformed values. For each time window, storing at least one of said plurality of transformed values and/or one or more parameters associated therewith.

Abstract: The invention concerns data processing by passage between different subband domains, of a first number L to a second number M of subband components. After determining a third number K, least common multiple between the first number L and the second number M: a) if K is different from L, it consists in arranging in blocs, by a serial/parallel conversion, an input vector X(z) to, obtain p2 polyphase component vectors (p2=KL); b) applying a square matrix filtering T(z) of dimensions K×K, to the p2 polyphase component vectors to obtain p1 polyphase component vectors for forming an output vector Y(z), with p1=K/M, and if the third number K is different from the second number M, providing a block arrangement by a parallel/serial conversion to obtain the output vector Y(z).

Abstract: A mantissa/exponent splitter splits an input value X=(1+X1/223)×(2^X2) into a mantissa X1 and an exponent X2. An interpolation processor references the mantissa/exponent splitter using the mantissa X1 and determines a power value (log2(1+X1/223)) through an interpolation process. A logarithmic calculator determines a logarithmic value Z=log2 XY=Y(X2+log2(1+X1/223)) from the exponent X2 and the power value from the interpolation processor. The integer/fraction splitter splits the logarithmic value Z into an integer Zint and a fraction Zamari. The interpolation processor references a power of fraction table storage unit in response to the fraction Zamari and determines a power value (2^Zamari) through the interpolation process. The power calculator determines XY=2^Z=(2^Zamari)×(2^Zint), thereby resulting in the input value X to the power of Y.

Abstract: When an image processing apparatus capable of connecting to a digital camera is to perform image-correction processing on irreversible-compression encoded image data acquired from the digital camera, it is determined whether the image-correction processing can be executed by the connected digital camera. When the processing can be executed, it is confirmed whether or not RAW data that corresponds to the irreversible-compression encoded image data is present in the digital camera. If the corresponding RAW data is present in the digital camera, the digital camera is requested to execute the image-correction processing based on the RAW data. This makes it possible to suppress degradation in the image quality more than when directly correcting an irreversible-compression encoded image.

Abstract: Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A hardware integer saturation detector that detects both whether packing a 32-bit integer value causes saturation and whether packing each of first and second 16-bit integer values causes saturation, where the first 16-bit integer value is the upper 16 bits of the 32-bit integer value and the second 16-bit integer value is the lower 16 bits of the 32-bit integer value. The detector includes hardware signal logic, configured to generate four signals with information about the integer values. The hardware integer detector also includes saturation logic, configured to gate the four signals to generate a saturation signal. Each bit of the saturation signal indicates whether packing the 32-bit integer value or whether packing one of the first and second 16-bit integer values will cause saturation respectively.

Abstract: Techniques are described to reduce rounding errors during computation of discrete cosine transform using fixed-point calculations. According to these techniques, a discrete cosine transform a matrix of scaled coefficients is calculated by multiplying coefficients in a matrix of coefficients by scale factors. Next, a midpoint bias value and a supplemental bias value are added to a DC coefficient of the matrix of scaled coefficients. Next, an inverse discrete cosine transform is applied to the resulting matrix of scaled coefficients. Values in the resulting matrix are then right-shifted in order to derive a matrix of pixel component values. As described herein, the addition of the supplemental bias value to the DC coefficient reduces rounding errors attributable to this right-shifting. As a result, a final version of a digital media file decompressed using these techniques may more closely resemble an original version of a digital media file.

Abstract: A computation apparatus includes an inverse conversion table creation unit configured to create an inverse conversion table in which discrete values obtained by applying a predetermined conversion on predetermined data correspond to inverse conversion values obtained by applying a conversion inverse to the predetermined conversion on the discrete values, a range decision unit configured to decide in which range the predetermined data is included when the predetermined data is input among ranges where the inverse conversion values adjacent in the inverse conversion table are set as border values, and a discrete value decision unit configured to decide the discrete value corresponding to the inverse conversion value whose value is close to the predetermined data among the inverse conversion values serving as the border values of the range decided by the range decision unit.

Abstract: Stored executable logic causes a processor to operate so as to receive route parameter data, including a start location and end location for future travel, from various users. The processor generates route data based on the received route parameter data for each user. The generated route data for each user includes geographic coordinate data with imbedded strings of geographic coordinate identifiers corresponding to strings of geographic coordinates defining a travel path between the start and end locations included in that user's route parameter data. The processor stores, in a database, the generated route data for each user in association with an identifier of that user and contact information for contacting that user while in route.

Abstract: A system and method for compressing and/or decompressing data uses a field programmable gate array (FPGA). In an embodiment, the method includes receiving data at the FPGA device, filtering the received data in a first dimension using a first logic structure of the FPGA device, storing the first filtered data in a memory of the FPGA device, filtering the received data in a second dimension using a second logic structure of the FPGA device, storing the second filtered data in the memory, quantizing the filtered data using a third logic structure of the FPGA device, encoding the quantized data using a fourth logic structure of the FPGA device to compress the data, and storing the encoded compressed data in a memory of the FPGA device.

Abstract: Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Abstract: Compression and decompression of numerical data can apply to floating-point or integer samples. Floating-point samples are converted to integer samples and the integer samples are compressed and encoded to produce compressed data for compressed data packets. For decompression, the compressed data retrieved from compressed data packets are decompressed to produce decompressed integer samples. The decompressed integer samples may be converted to reconstruct floating-point samples. Adaptive architectures can be applied for integer compression and decompression using one or two FIFO buffers and one or two configurable adder/subtractors. Various parameters can adapt the operations of adaptive architectures as appropriate for different data characteristics. The parameters can be encoded for the compressed data packet. This abstract does not limit the scope of the invention as described in the claims.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: Nonlinear compression of high precision image data (e.g., 12-bits per subpixel) conventionally calls for a large sized lookup table (LUT). A smaller sized and tunable circuit that performs compression with piecewise linear compressing segments is disclosed. The piecewise linear data compressing process is organized so that lumping together of plural ‘used’ high precision value points into one corresponding low precision data value point is avoided or at least minimized. In one embodiment, the compressed data is image defining data being processed for display on a nonconventional display screen where the piecewise linearly compressed data can be stored adjacent to other image data in a frame buffer where a composite image is assembled.

Abstract: A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C having a high order portion 160 and a low order portion 170. The apparatus has adding circuitry 130 configured to: (i) add an operand A to one of the high order portion 160 and the low order portion 170 to generate an intermediate sum value; and (ii) add the intermediate sum value to a remaining one of the high order portion 160 and the low order portion 170 to generate a result A+B*C.

Abstract: A device for counting photons includes a detector unit that is configured to generate an detected signal. A switching unit is configured to be impinged upon by the detected signal and to trigger a switching state for each detection pulse so as to generate a state signal. A sampling unit is configured to sample the state signal at a predetermined sampling frequency. A serial-parallel converter unit is configured to parallelize the serially generated sampled data by grouping successive sampled data into a sampled data packet. An evaluation unit is configured to evaluate the binary values of sampled data packets so as to identify a partial counter result indicating the number of switching state changes occurring in the switching unit, and to add partial counter results identified in individual clock cycles.

Abstract: Compression of an initial dataset is implemented on a data processing system. The initial dataset can be transformed (210) into a group of initial wavelet coefficients using a wavelet basis function. Magnitudes of initial wavelet coefficients in the group of initial wavelet coefficients can be calculated (220). Initial wavelet coefficients having magnitudes beyond a cutoff value can be deleted (230). A compressed group of wavelet coefficients can be identified (240) from the wavelet coefficients remaining within the cutoff value. The initial dataset can be approximated (250) using the compressed group of wavelet coefficients and the wavelet basis function.

Abstract: A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1.

Abstract: A signal processor for compressing signal data, including a function shapes generator for receiving as input time and frequency scale parameters, and for generating as output a plurality of shape parameters for a corresponding plurality of localized functions, wherein the shape parameters govern the centers and spreads of the localized functions, a matrix generator for receiving as input the plurality of shape parameters and a sequence of sampling times, and for generating as output a matrix whose elements are the values of the localized functions at the sampling times, a signal transformer for receiving as input an original signal and the matrix generated by the matrix generator, and for generating as output a transformed signal by applying the matrix to the original signal, and a signal compressor for receiving as input the transformed signal, and for generating as output a compressed representation of the transformed signal.

Abstract: A method for compressing a set of small strings may include calculating n-gram frequencies for a plurality of n-grams over the set of small strings, selecting a subset of n-grams from the plurality of n-grams based on the calculated n-gram frequencies, defining a mapping table that maps each n-gram of the subset of n-grams to a unique code, and compressing the set of small strings by replacing n-grams within each small string in the set of small strings with corresponding unique codes from the mapping table. The method may use linear optimization to select a subset of n-grams that achieves a maximum space saving amount over the set of small strings for inclusion in the mapping table. The unique codes may be variable-length one or two byte codes. The set of small strings may be domain names.

Abstract: Systems and methods to reduce I/O (input/output) with regard to out-of-core liner solvers and/or to speed up out-of-core linear solvers.

Abstract: Exemplary embodiments comprise memory for storing the look-up table values. One exemplary memory comprises a decoder, an encoder, and one or more patterns of crisscrossed interconnect lines that interconnect the encoder with the decoder. The patterns of crisscrossed interconnection lines may be implemented on one or more planar layers of conductor tracks vertically interleaved with isolating material.

Abstract: The LLMICT transform matrices are orthogonal, hence their inverses are their transpose. The LLMICT transform matrices are integer matrices, which can be implemented with high precision eliminating the drift error in video coding. The fast algorithms for the LLMICT transform are found, thus allowing a lower requirement on computation hardware. The LLMICT is also found to have high transform coding gain due to its similarity to the DCT.

Abstract: The invention relates to a computer-implemented method for compressing numerical data comprising a structured set of floating point actual values. A floating point value is defined by a sign, an exponent and a mantissa. The method comprises computing a floating point predicted value related to a target actual value of the set. The computing includes performing operations on integers corresponding to the sign, to the exponent and/or to the mantissa of actual values of a subset of the set. The method also comprises storing a bit sequence representative of a difference between integers derived from the target actual value and the predicted value. Such a method is particularly efficient for reducing the storage size of a CAD file.

Abstract: According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.

Abstract: A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.

Abstract: An analog optical adder system that achieves high precision results. The system uses an analog optical carry function to provide a result having a precision higher than the precision of the individual elements of the system. The optical carry function is created by optical carry determinators that are configured to add an optical carry, if any, to an optical signal associated with a next adjacent byte of the digital signals being added. The use of optical carry enables greater overall addition precision.

Abstract: A method and apparatus for fractional digital integration of an input signal is provided, the input signal including a time series of numerical values and the method or apparatus including applying the input signal time series to one input of a two-input summer at a time I, providing an output of the summer to a delay register at time I, providing an output of the delay register from time i?1 to a two-input multiplier, providing an output of the multiplier to the summer at time I, using a resettable counter to determine a value i and index a lookup table with i to provide the indexed value of the lookup table as an input to the multiplier, and obtaining an output signal time series from the output of the summer.

Abstract: A system and method for waveform compression includes preprocessing a collection of waveforms representing cell and/or interconnect response waveforms and constructing a representative waveform basis using linear algebra to create basis waveforms for a larger set of waveforms. The collection waveforms are represented as linear combination coefficients of an adaptive subset of the basis waveforms to compress an amount of stored information needed to reproduce the collection of waveforms. The representation of coefficients may be further compressed by, e.g., analytic representation.

Abstract: A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.

Abstract: A method and apparatus for compressing signal samples uses block floating point representations where the number of bits per mantissa is determined by the maximum magnitude sample in the group. The compressor defines groups of signal samples having a fixed number of samples per group. The maximum magnitude sample in the group determines an exponent value corresponding to the number of bits for representing the maximum sample value. The exponent values are encoded to form exponent tokens. Exponent differences between consecutive exponent values may be encoded individually or jointly. The samples in the group are mapped to corresponding mantissas, each mantissa having a number of bits based on the exponent value. Removing LSBs depending on the exponent value produces mantissas having fewer bits. Feedback control monitors the compressed bit rate and/or a quality metric. This abstract does not limit the scope of the invention as described in the claims.

Abstract: This disclosure provides implementations of dither-aware image coding processes, devices, apparatus, and systems. In one aspect, a portion of received image data is selected. First spatial domain values in the selected portion of the image data are transformed to first transform domain coefficients. Second spatial domain values in a designated dither matrix are transformed to second transform domain coefficients. A ratio of each of the first transform domain coefficients to a respective second transform domain coefficient is determined. The first transform domain coefficients are selectively coded in accordance with the determined ratios to define coded first transform domain coefficients. A reverse transformation is performed to transform the coded first transform domain coefficients to third spatial domain values defining a coded portion of the image data. By way of example, transformations such as discreet cosine transforms or discreet wavelet transforms can be used.

Abstract: Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths.

Abstract: A system and method are provided for use with streaming blocks of data, each of the streaming blocks of data including a number bits of data. The system includes a first compressor and a second compressor. The first compressor can receive and store a number n blocks of the streaming blocks of data, can receive and store a block of data to be compressed of the streaming blocks of data, can compress consecutive bits within the block of data to be compressed based on the n blocks of the streaming blocks of data, can output a match descriptor and a literal segment. The match descriptor is based on the compressed consecutive bits. The literal segment is based on a remainder of the number of bits of the data to be compressed not including the consecutive bits. The second compressor can compress the literal segment and can output a compressed data block including the match descriptor and a compressed string of data based on the compressed literal segment.

Abstract: A decoding apparatus includes a random number generating section and a decoding section. The random number generating section generates random numbers according to distribution of original data corresponding to respective quantization indexes. The decoding section generates decoded data on a basis of the random numbers generated by the random number generating section.

Abstract: An image processing apparatus includes: a reference-based coding unit that encodes image information for an image partition having a predefined size by referring to image information for another image partition; an independently coding unit that encodes the image information for the image partition independently of any other image partition; and a bounds defining unit that defines bounds of reference to be made by the reference-based coding unit.

Abstract: Compression of exponents, mantissas and signs of floating-point numbers is described. Differences between exponents are encoded by exponent tokens selected from a code table. The mantissa is encoded to a mantissa token having a length based on the exponent. The signs are encoded directly or are compressed to produce fewer sign tokens. The exponent tokens, mantissa tokens and sign tokens are packed in a compressed data packet. Decompression decodes the exponent tokens using the code table. The decoded exponent difference is added to a previous reconstructed exponent to produce the reconstructed exponent. The reconstructed exponent is used to determine the length of the mantissa token. The mantissa token is decoded to form the reconstructed mantissa. The sign tokens provide the reconstructed signs or are decompressed to provide the reconstructed signs. The reconstructed sign, reconstructed exponent and reconstructed mantissa are combined to form a reconstructed floating-point number.

Abstract: The disclosed embodiments relate to methods and apparatus for accurately, efficiently and quickly executing a fused multiply-and-accumulate instruction with respect to floating-point operands that have packed-single-precision format. The disclosed embodiments can speed up computation of a high-part of a result during a fused multiply-and-accumulate operation so that cycle delay can be reduced and so that power consumption can be reduced.