Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: In an embodiment, a method performs computer operations using a first fractional precision and a second fractional precision. A computer program has a source variable, a destination variable, and an operation. The source variable has a first dynamic fractional precision, the destination variable has a second dynamic fractional precision that differs from the first dynamic fractional precision, and the operation is related to the source variable and the destination variable. The source variable is aligned to a format of the destination variable, according to the first dynamic fractional precision and the second dynamic fractional precision. The operation is performed using the destination variable and the source variable. A value is assigned to the destination variable according to the operation. In this manner, a single codebase may be written that operates on various hardware that each have different bit precision capabilities, without requiring additional development and verification effort.

Abstract: A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number.

Abstract: A computer-implemented method includes dividing an image into one or more image channels for image compression. The method also includes dividing one or more of the image channels into one or more blocks. At least one of the blocks includes floating point representations of pixel values included in the block. The method also includes converting the floating point representations of pixel values into integer representations such that the sign of each floating point representation is preserved. The method also includes storing the difference of adjacent integer representations as a compressed version of the image.

Abstract: Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware.

Abstract: A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value.

Abstract: The present application addresses a fundamental problem in the design of computing systems, that of minimizing the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.

Abstract: Data measured by PS-OCT is corrected in a non-linear manner to enhance the quantitative analysis capability of PS-OCT and permit accurate quantitative diagnosis, including diagnosis of disease stage of lesions, as a useful means for computer diagnosis. Even when retardation per PS-OCT 1 contains error and becomes noise and its distribution is not normal or symmetrical around the true value, measured data is converted using a distribution conversion function obtained by analyzing the characteristics of noise via Monte Carlo simulation to remove the systematic error and estimate the true value otherwise buried in noise and thereby correct the PS-OCT 1 image more clearly.

Abstract: A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors.

Abstract: A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.

Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

Abstract: A data converting method and device therefor are disclosed by the invention, relating to data converting algorithm field, solving the problem of complicate data converting method in prior art. Steps of the invention are obtaining offset from the predetermined byte of the data string to be converted; obtaining the predetermined bits of data from the data string to be converted according to the offset; converting the obtained bits to decimal number; determining whether size of the decimal number is smaller than the first predetermined length, if so, keeping adding 0 to the upper digit of the decimal number till the first predetermined length is reached, and taking the data with added 0 as the converted data; otherwise keeping obtaining data from low bit of the decimal number, till the first predetermined length is reached, and taking the obtained data as the converted data. The method of the invention is mainly used for devices and methods requiring data converting, e.g.

Abstract: A programmable device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step. To conserve resources, rather than configuring the every intermediate operation to have the same mantissa size, in the internal format the mantissa size may start out smaller and grow after each operation.

Abstract: Methods and devices for automatically determining a suitable bit-width for data types to be used in computer resource intensive computations. Methods for range refinement for intermediate variables and for determining suitable bit-widths for data to be used in vector operations are also presented. The invention may be applied to various computing devices such as CPUs (Central Processing Units), GPUs (Graphic Processing Units), FPGAs (Field Programmable Gate Arrays), etc.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.

Abstract: An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

Abstract: A method is described to combine two integer lookup tables to realize a single integer lookup table. The method converts each lookup table to a set of floating point values. The conversion process generates a set of floating point values that are as close as possible to the underlying analytic or smooth function that generated the tables in the first place. A system to implement the method is also described.

Abstract: Compression and decompression of numerical data can apply to floating-point or integer samples. Floating-point samples are converted to integer samples and the integer samples are compressed and encoded to produce compressed data for compressed data packets. For decompression, the compressed data retrieved from compressed data packets are decompressed to produce decompressed integer samples. The decompressed integer samples may be converted to reconstruct floating-point samples. Adaptive architectures can be applied for integer compression and decompression using one or two FIFO buffers and one or two configurable adder/subtractors. Various parameters can adapt the operations of adaptive architectures as appropriate for different data characteristics. The parameters can be encoded for the compressed data packet. This abstract does not limit the scope of the invention as described in the claims.

Abstract: A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.

Abstract: The disclosed embodiments facilitate converting binary values into the BCC format. One technique facilitates the direct conversion of binary numbers into BCC. A second variation first converts a binary number into an intermediate BCD value, and then converts that BCD value into a BCC value. Look-ahead comparators can further improve conversion performance by decreasing the latency of the conversion operation. By speeding up the conversion of binary values to decimal-format values, the disclosed techniques facilitate leveraging dedicated binary-format hardware for decimal-format operations, and thus improve the performance of decimal-format operations.

Abstract: When converting an affine representation representing a 2r-th degree algebraic torus T2r(Fq) (r is a prime number, and q is an integer) to a projective representation representing a quadratic algebraic torus T2(Fq^r), a representation converting apparatus acquires member (c0, c1, . . . , cr-2), (ci is a member of a finite field Fq, where 0?i?r?2) of a 2r-th degree algebraic torus T2r(Fq) represented by the affine representation. The apparatus performs a multiplication operation on the acquired member. The multiplication operation is determined by a condition under which a member of a quadratic algebraic torus T2(Fq^r) is included in the 2r-th degree algebraic torus T2r(Fq), a modulus and a base of a quadratic extension, and a modulus and a base of an r-th degree extension. The representation converting apparatus then performs an addition and subtraction operation determined by the condition, the moduli, and the bases.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value.

Abstract: The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.

Abstract: An automatic graphics delivery system that operates in parallel with an existing Web site infrastructure is provided. The system streamlines the post-production process by automating the production of media through content generation procedures controlled by proprietary tags placed by an author within URLs embedded within Web documents.

Abstract: An embedded control system capable of ensuring precision in arithmetic with data in the floating-point format and also avoiding a shortage of the storage area of a memory is provided. According to an embedded control system in the present invention, when discrete data in the floating-point format is stored in a read-only memory, the discrete data in the floating-point format is converted into data in a significand-reduced floating-point format before being stored. Here, a significand-reduced floating-point number is a number obtained by deleting low-order bits of the significand of a floating-point number. Further, an interpolation search is performed using discrete data, the discrete data in the significand-reduced floating-point format stored in the read-only memory is brought back to the discrete data in the floating-point format before an interpolation search being performed.

Abstract: Disclosed is a system and method for converting a digital number to text and for pronouncing the digital number. The system includes a filtration system for determining whether the digital number has nonnumeric symbols and for generating a filtrated number, an analyzing system for analyzing the filtrated number, a composition system configured to collect words associated with ternary units of the filtrated number, a linking system configured to link the words, and a pronouncing system for pronouncing the linked words.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including an insert biased exponent or extract biased exponent instruction.

Abstract: The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves.

Abstract: A system and method which multiplies the bits using integer multiplication is set forth. More specifically, performing a floating point operation using integer multiplication includes performing a high precision multiplication of an input ‘x’ having a first bit width using a plurality of integer multiplication operations of a second bit width, the second bit width being smaller than the first bit width, the plurality of integer multiplication operations each generating a result corresponding the first bit width.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions.

Abstract: An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm.

Abstract: A system, method, and apparatus for converting a decimal real number in ASCII format to a decimal real number in floating point binary decimal format in a vector processor are described. The method results in the performance of the conversion in a branchless manner and in a constant-time regardless of the size of the ASCII string, within a given range of sizes provided for by the vector processor architecture. The method may take advantage of the single instruction multiple data (SIMD) feature of the vector processor, although it is not restricted to a single instruction.

Abstract: Systems and methods for managing floating point variables are described in the present disclosure. According to one example, an embodiment of a method includes analyzing a constraint on a floating point variable in a system that supports both floating point variables and integer variables. The constraint is designed to have the ability to numerically limit the domain of the floating point variable. The method also includes determining whether or not the floating point variable can be handled as an integer variable and converting the floating point variable to a pseudo integer variable when it is determined that the floating point variable can be handled as an integer variable. This conversion of the floating point variable to a pseudo integer variable allows the domain of the floating point variable to be processed as an integer domain.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format, and to reformat the first and the second 2N-bit complex numbers to a second format such that a lower portion of each real and imaginary part of each 2N-bit complex number is positive. The second circuit may be configured to multiply the first and the second 2N-bit complex numbers using at least one N-bit signed complex multiplier, where N is an integer.

Abstract: Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.

Abstract: A system and method for converting from decimal floating point (DFP) into scaled binary coded decimal (SBCD). The system includes a mechanism for receiving a DFP number. The system also includes at least one of a mechanism for performing coefficient expansion on the DFP number to create a binary coded decimal (BCD) coefficient part of a SBCD number and a mechanism for performing exponent extraction on the DFP number to create an exponent part of the SBCD number.

Abstract: A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.

Abstract: Described herein are technologies pertaining to matrix computation. A computer-executable algorithm that is configured to execute perform a sequence of computations over a matrix tile is received and translated into a global directed acyclic graph that includes vertices that perform a sequence of matrix computations and edges that represent data dependencies amongst vertices. A vertex in the global directed acyclic graph is represented by a local directed acyclic graph that includes vertices that perform a sequence of matrix computations at the block level, thereby facilitating pipelined, data-driven matrix computation.

Abstract: A method for double precision approximation of a single precision operation is disclosed. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor.

Abstract: In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.

Abstract: An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.

Abstract: Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.

Abstract: Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantise and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.

Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

Abstract: Systems and methods for matching data based on numeric difference are described herein. Input data elements are parsed to identify a first number and a second number. A difference between the first number and the second number is calculated based on a predefined formula. Based on the difference, a matching score between the input data elements is evaluated. The matching score is proportional to a base matching score corresponding to a threshold difference, and a maximum score corresponding to a match between the first number and the second number. A similarity between the input data elements is reported based on the evaluated matching score.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions.

Abstract: The subject matter disclosed herein provides methods and systems for converting fixed-point soft bit values, provided by a demapper, into floating-point soft bits values. In one aspect, there is provided a method. The method may include receiving, from a demapper, soft bits formatted as a fixed-point value. Moreover, the soft bits may be converted from the fixed-point value to a floating-point value. The floating-point value is punctured to remove a bit. The converted soft bits are provided to a buffer to enable decoding of the buffered soft bits. Related systems, apparatus, methods, and/or articles are also described.

Abstract: Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window.