Abstract: A system and method for transforming data from a first format to a second format. A pre-existing set of software instructions may be used to transform the data from the first format to the second format. A user may document a set of format parameters for the first format of data, which can be used to determine which portion of the pre-existing software instructions are used to transform the data from the first format to the second format.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions.

Abstract: According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.

Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

Abstract: A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number.

Abstract: Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding logic then can provide the valid data values so that operations on the valid data values can be performed in accordance with instructions received from an associated program.

Abstract: A data converting method and device therefor are disclosed by the invention, relating to data converting algorithm field, solving the problem of complicate data converting method in prior art. Steps of the invention are obtaining offset from the predetermined byte of the data string to be converted; obtaining the predetermined bits of data from the data string to be converted according to the offset; converting the obtained bits to decimal number; determining whether size of the decimal number is smaller than the first predetermined length, if so, keeping adding 0 to the upper digit of the decimal number till the first predetermined length is reached, and taking the data with added 0 as the converted data; otherwise keeping obtaining data from low bit of the decimal number, till the first predetermined length is reached, and taking the obtained data as the converted data. The method of the invention is mainly used for devices and methods requiring data converting, e.g.

Abstract: A method is described to combine two integer lookup tables to realize a single integer lookup table. The method converts each lookup table to a set of floating point values. The conversion process generates a set of floating point values that are as close as possible to the underlying analytic or smooth function that generated the tables in the first place. A system to implement the method is also described.

Abstract: In an embodiment, a method performs computer operations using a first fractional precision and a second fractional precision. A computer program has a source variable, a destination variable, and an operation. The source variable has a first dynamic fractional precision, the destination variable has a second dynamic fractional precision that differs from the first dynamic fractional precision, and the operation is related to the source variable and the destination variable. The source variable is aligned to a format of the destination variable, according to the first dynamic fractional precision and the second dynamic fractional precision. The operation is performed using the destination variable and the source variable. A value is assigned to the destination variable according to the operation. In this manner, a single codebase may be written that operates on various hardware that each have different bit precision capabilities, without requiring additional development and verification effort.

Abstract: A method and apparatus of processing floating point number(s) is provided. The method which processes a plurality of first floating point numbers each having a mantissa and an exponent includes: normalizing exponents of the first floating point numbers according to a minimum value of the exponents to generate normalized exponents of the first floating point numbers; generating a plurality of second floating point numbers respectively corresponding to the first floating point numbers according to mantissas and the normalized exponents of the first floating point numbers; utilizing a processor to perform a specific computation on the second floating point numbers to generate a plurality of third floating point numbers; and de-normalizing each of the normalized exponents to accordingly generate a de-normalization result and adjusting the third floating point numbers according to the de-normalization result.

Abstract: Provided is a method for finding a minimal signed digit with variable multi-bit coding. The method includes the steps of: scanning and grouping given multi-bit and checking the type of each group; deciding whether each group is to be performed by any one of a coding for positive number and a coding of negative number depending on the type of each group; converting the value of each group into a corresponding value of different number system and finding a signed digit based on the converted value; if the type of each group indicates the coding for negative number, performing bitwise inverting on the value of each group; and converting multi-bit subjected to the bitwise inverting into a corresponding value of different number system, and finding a signed digit based on the converted value.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: Methods and devices for automatically determining a suitable bit-width for data types to be used in computer resource intensive computations. Methods for range refinement for intermediate variables and for determining suitable bit-widths for data to be used in vector operations are also presented. The invention may be applied to various computing devices such as CPUs, GPUs, FPGAs, etc.

Abstract: The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, an?1, and n?1 fractional bits, an?2, an?3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ? i = 0 n - 2 ? - a i ? 2 i - n + 1 .

Abstract: A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations.

Abstract: Apparatus and computer programs are provided for generating n high-precision data elements corresponding to an n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision data elements and b is an n×1 vector corresponding to n predefined high-precision data elements. The apparatus (1) comprises memory (3) for storing input data defining the data elements of matrix A and of vector b, and control logic (2). In a first processing step (a), the control logic (2) implements a first iterative process for generating from the input data n low-precision data elements corresponding to an n×1 vector x1 satisfying A1x1=b1. Here, A1 is an n×n matrix corresponding to the n×n data elements of matrix A in low precision and bi is an n×1 vector corresponding to the n×1 data elements of vector b in low precision. The control logic (2) terminates the first iterative process on occurrence of a first convergence condition.

Abstract: According to one embodiment, a NAF conversion apparatus which converts a binary representation of an integer into a w-NAF redundant binary representation includes an acceptance device, a storage device, a shift register, and an update device. The acceptance device accepts the binary representation of the integer for every bit from lower bits. The storage device stores a state value expressed by 1 bit. The shift register stores a state value expressed by (w-1) bits. The update device determines a state of the storage device and a state of the (w?1)-bit shift register at next time, and determines a w-bit parallel output at current time by referring to a 1-bit value accepted by the acceptance device, the state value in the storage device, and the state value in the (w?1)-bit shift register.

Abstract: In a client, a system receives a set of transformation functions for use in transforming a first content, requests the first content from a gateway, and receives the first content from the gateway, including an invocation of at least one transformation function maintained on the client. The system invokes the at least one transformation function to transform the first content to access a second content on the server. In a gateway communicating with a server, a system transmits a set of transformation functions to at least one client for use in transforming a first content, receives a request from at least one client for the first content residing on the server, rewrites the first content to include the invocation of at least one transformation function maintained on the client, and transmits the first content including the invocation of at the least one transformation function maintained on the client.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: An apparatus generally having a lookup table and a circuit is disclosed. The lookup table may be configured to store a plurality of results including remainders of divisions by a particular polynomial. The circuit may be configured to (i) parse a first polynomial into a plurality of data blocks and an end block, (ii) fetch a plurality of results from the lookup table by indexing the lookup table with each of the data blocks and (iii) generate a second polynomial by adding the results fetched from the lookup table to the end block. The second polynomial generally has a second degree that is lower that a first degree of the first polynomial.

Abstract: A system, method, and apparatus for the constant time, branchless conversion of decimal integers of varying size in ASCII format to a decimal integer in binary decimal format in a vector processor utilizing simultaneous conversion of the string to a binary format, followed by simultaneous multiplications of the binary result by appropriate powers of ten and a fixed number of steps of vector addition, followed by a final step of a scalar multiplication of a sign value.

Abstract: A compiler (or interpreter) detects source language instructions performing arithmetic operations using a fixed point format (preferably packed decimal). Where the operation can be performed without loss of precision or violation of other constraints of the source language, the compiler automatically converts the operands to a floating point format (preferably Decimal Floating Point (DFP)) having hardware support, and re-converts results to the original fixed point format. Preferably, the compiler may combine multiple operations and instructions in an expression tree, analyze the tree, and selectively convert where possible. The compiler preferably performs a heuristic cost judgment in determining whether to use a particular conversion.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: Methods and apparatus for multiplying integers using a double-base numbering system are presented. In one embodiment, a method includes splitting a first integer into a plurality of binary blocks. The method may also include encoding the plurality of binary blocks into a plurality of encoded blocks in a double-base numbering system. Additionally, the method may include producing a plurality of multiples of a second integer. The method may also include producing a plurality partial results. The method may include selectively shifting the plurality of partial results to generate a plurality of shifted partial results, and adding the plurality of partial results and the shifted partial results to create the product of a plurality of integers.

Abstract: An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.

Abstract: The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient partial product generation through sharing of at least one partial product result.

Abstract: A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value.

Abstract: A method and system to compensate for inaccuracy associated with processing values with finite precision includes a process for selecting a display value whereby an initial value is provided in a first numbering system. The initial value is then converted into an equivalent stored value in a second numbering system. Then a display value in the first numbering system is determined and selected such that the selected display value includes the least number of significant digits that convert from the first numbering system to the second numbering system exactly as the stored value. The selected display value in the first numbering system is then used for display and/or further processing when the stored value in the second numbering system is recalled.

Abstract: A detecting method for network intrusion includes: selecting a plurality of features contained within plural statistical data by a data-transforming module; normalizing a plurality of feature values of the selected features into the same scale to obtain a plurality of normalized feature data; creating at least one feature model by a data clustering technique incorporated with density-based and grid-based algorithms through a model-creating module; evaluating the at least one feature model through a model-identifying module to select a detecting model; and detecting whether a new packet datum belongs to an intrusion instance or not by a detecting module.

Abstract: A method for generating partial sums from at least four multiple-digit sequences in a computing device includes partitioning the multiple-digit sequences into at least a first set of multiple-digit sequences and a second set of multiple-digit sequences. The method also includes generating at least one auxiliary set of multiple-digit sequences. The auxiliary set includes digits copied from respective digit positions of multiple-digit sequences in the first and second sets. The method further includes replacing the copied digits in the first and second sets by zeros to obtain a first altered set and a second altered set, respectively, of multiple-digit sequences each comprising multiple segments separated by the replaced zeros.

Abstract: A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c1, and a source exponent, n, of an input value represented by a floating-point number in a source base, b1; converting the source coefficient to a common base, b2, and storing the converted coefficient in a first digit collection; iteratively multiplying the contents of the first digit collection by b1 and storing the intermediate results therein, wherein one or more overflow bits of the first digit collection are carried and added to one or more additional digit collections once a nonzero value is reached; and an output value in the common base is stored in the digit collections after n multiplication iterations, represented by c2×b2m, wherein c2 is the converted coefficient of the output value in the common base b2 and m is the exponent of the output value.

Abstract: A system to improve numerical conversion may include a data processor and a controller configured to convert a floating-point number from the data processor to more than one different floating-point type number. The conversion may enable the selection of the more than one different floating-point type number that satisfies the requirements of an executing application and/or is closest to the original number.

Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.

Abstract: A operator is located between two converters that convert data between floating-point format and a predetermined format. The operator operates on predetermined format data, which consists of the same sign bit, the same exponent, and the two's complement of the mantissa of the corresponding floating-point data. When the operator is an arithmetic logic unit (ALU), the number of operations for a given calculation can be reduced.

Abstract: Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.

Abstract: A data processing apparatus and method are provided for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus comprises a data processing unit operable to execute instructions, with the data processing unit being responsive to a format conversion instruction to apply a format conversion operation to a number to perform a conversion between the fixed-point representation of the number and the floating-point representation of the number. Furthermore, a control field is provided which is arranged to provide a programmable value specifying a decimal point location within the fixed-point representation of the number, and the data processing unit is operable to reference the control field and to control the formal conversion operation in accordance with the programmable value.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: An arithmetic program conversion apparatus, an arithmetic program conversion program and an arithmetic program conversion method that can convert the floating-point arithmetic of an arithmetic program into a fixed-point arithmetic without degrading the accuracy.

Abstract: A data converting apparatus includes a segmenting unit for setting a predetermined access unit, as an access unit to be processed, out of input data containing at least one access unit containing a plurality of data components per pixel, and for segmenting the access unit to be processed into at least one block; an analyzing unit for generating a basis for converting an expression format of each of the plurality of data components by respectively setting, as at least one analysis block, at least one segmented block and for performing a main component analysis on the plurality of data components; and a converting unit for converting the expression format of each of the plurality of data components per pixel forming the block to be processed.

Abstract: A system and method for converting bases of floating point numbers using fixed-point computation includes tables having different related spacings of exponent indices. The tables are adapted to cross-reference conversion ratios between exponent bases. The tables are characterized by bi-uniform spacings of source and target exponents and including near-unity table entries representing the conversion ratios. A source number is converted into a target number in a different radix by a sequence of reduction operations using a sequence of the tables. The reduction operations include reducing a source number exponent magnitude and accumulating a target exponent and multiplying a source number mantissa by a selected conversion ratio including a near-unity ratio of powers. A final mantissa is normalized and rounded to produce the target number in a new radix.

Abstract: An abstraction apparatus for processing data is provided. The abstraction apparatus implements an abstraction layer that supports a variety of physical objects (hardware). The abstraction apparatus only manages information related to data denormalization and/or denormalization separately without embedding the information in the logical objects (software), thereby reducing overhead due to the normalization and/or denormalization.

Abstract: Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Abstract: A computer implemented method for determining when to change a representation type of at least one number stored in a memory of a data processing system. An operation is received in a processor of the data processing system. The operation references a number stored as a class of an object-oriented programming language. The number is stored as a first representation type. Responsive to the operation being biased towards the first representation type, a first counter is incremented. Responsive to the operation being biased towards a second representation type, a second counter is incremented. A counter reference is equal to a first value of the first counter subtracted from a second value of the second counter. Responsive to the counter reference exceeding a threshold number, representation of a subsequent number is changed from the first representation type to the second representation type.

Abstract: An method and/or apparatus for representing and/or operating on numerical values in binary systems whereby numerical values having integer and fractional portions are stored in non-contiguous memory locations.

Abstract: Various technologies and techniques are disclosed for providing a numeric tower that represents a structure supporting statically defined numeric data types. The numeric data types each are operable to implement a different but accurate representation of a particular value. Numeric operations are supported for the numeric tower that can be performed with any of the statically defined numeric data types. The numeric tower is extensible, and allows for additional statically defined numeric data types to be added, as well as operations. The numeric tower is also operable to detect overflow situations. For example, suppose a result of an operation will result in an overflow situation because the operation does not fit within a range supported by the particular numeric type. The system converts the numeric type to a different one of the numeric data types when the result does not fit within a range supported by the first one.

Abstract: An encoding circuit is disclosed which comprises: a data-for-encoding storing register that stores n-bit data for encoding; a data-for-calculation storing register that stores m-bit data for calculation generated by shifting the data for encoding; a shifter that shifts the data for encoding stored in the data-for-encoding storing register, and shifts and inputs the shifted data into the data-for-calculation storing register; a first coefficient register that stores m-bit first coefficient data indicating a first coefficient for executing encoding; a first logic circuit that is inputted with the data for calculation stored in the data-for-calculation storing register and the first coefficient data stored in the first coefficient register and outputs the logical product for each bit of the data for calculation and the first coefficient data; and a second logic circuit that is inputted with m-bit data outputted from the first logic circuit and outputs the exclusive logical sum of the m-bit data as the encoded da

Abstract: A programmable logic device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.