Normalization Patents (Class 708/205)
  • Patent number: 11416215
    Abstract: Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: August 16, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Casper Van Benthem
  • Patent number: 11074072
    Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a bipolar binary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the bipolar binary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
  • Patent number: 10908878
    Abstract: A method, computer readable medium, and system are disclosed for rounding floating point values. Dynamic directional rounding is a rounding technique for floating point operations. A floating point operation (addition, subtraction, multiplication, etc.) is performed on an operand to compute a floating point result. A sign (positive or negative) of the operand is identified. In one embodiment, the sign determines a direction in which the floating point result is rounded (towards negative or positive infinity). When used for updating parameters of a neural network during backpropagation, dynamic directional rounding ensures that rounding is performed in the direction of the gradient.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Alex Fit-Florea, Boris Ginsburg, Pooya Davoodi, Amir Gholaminejad
  • Patent number: 10846053
    Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10846054
    Abstract: Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Son T. Dao, Silvia Melitta Mueller
  • Patent number: 10824618
    Abstract: A set of data is identified that includes a plurality of observed values generated by a plurality of sensor devices located in a plurality of different locations. For each of the plurality of observed values, a modality of the value, a spatial location of the value, and a timestamp of the value is determined. Values for one or more missing values in the set of data are determined from the modalities, spatial locations, and timestamps of the plurality of observed values.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Guang-He Lee, Shao-Wen Yang
  • Patent number: 10770091
    Abstract: A method includes: receiving time instants of audio signals generated by a set of microphones at a location; determining a distortion measure between frequency components of at least some of the received audio signals; determining a similarity measure for the frequency components using the determined distortion measure; and processing the audio signals based on the determined similarity measure.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 8, 2020
    Assignee: GOOGLE LLC
    Inventors: Willem Bastiaan Kleijn, Sze Chie Lim
  • Patent number: 10698655
    Abstract: Hardware logic arranged to normalise (or renormalise) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalisation block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 30, 2020
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 10579333
    Abstract: An arithmetic unit includes a multiplier multiplying first and second inputs to output a multiplication result, an adder adding the third input to the multiplication result to output a multiplication addition result, a normalization shift circuit shifting the multiplication addition result left with a left shift amount, and a left shift amount prediction circuit. The adder includes a carry-save adder adding a first addition value and a first carry value to the third input and a full adder outputting the multiplication addition result. The left shift amount prediction circuit includes a leading zero count circuit generating a leading zero count, a leading one count circuit generating a leading one count, and a correction circuit correcting the leading one count to zero when NOR of respective least significant bits of the M upper order bits of the second addition value and the second carry value of the full adder is true.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kenichi Kitamura
  • Patent number: 10564931
    Abstract: In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: February 18, 2020
    Assignee: Apple Inc.
    Inventors: Richard T. Witek, Brian D. Clark, Peter C. Eastty
  • Patent number: 10474429
    Abstract: Configurable specialized processing blocks, such as DSP blocks, are described that implement fixed and floating-point functionality in a single mixed architecture on a programmable device. The described architecture reduces the need to construct floating-point functions outside the configurable specialized processing block, thereby minimizing hardware cost and area. The disclosed architecture also introduces pipelining into the DSP block in order to ensure the floating-point multiplication and addition functions remain in synchronicity, thereby increasing the maximum frequency at which the DSP block can operate. Moreover, the disclosed architecture includes logic circuitry to support floating-point exception handling.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: November 12, 2019
    Assignee: Altera Corporation
    Inventors: Keone Streicher, Martin Langhammer, Yi-Wen Lin, Hyun Yi
  • Patent number: 10223068
    Abstract: Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 10120651
    Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: November 6, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Freddie Rupert Exall, Theo Alan Drane, Joe Buckingham
  • Patent number: 10114642
    Abstract: A processor includes a front end to decode an instruction and an allocator to assign the instruction to an execution unit to execute the instruction to compute a floating point result subject to a cancellation effect. The execution unit includes a threshold to control notification the cancellation effect, a logic to compute the maximum exponent from a source value, a logic to compute the floating point exponent, a logic to compute the detected cancellation value, and a logic to compare the detected cancellation value to the threshold.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Nikita Astafev
  • Patent number: 10114641
    Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Ronen Zohar, Shane Story
  • Patent number: 10114640
    Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Ronen Zohar, Shane Story
  • Patent number: 10108398
    Abstract: According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating-point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating-point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating-point operands.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Eric C. Quinnell
  • Patent number: 10108416
    Abstract: In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Ronen Zohar, Shane Story
  • Patent number: 9830129
    Abstract: According to one general aspect, an apparatus may include a floating-point addition unit that includes a far path circuit, a close path circuit, and a final result selector circuit. The far path circuit may be configured to compute a far path result based upon either the addition or the subtraction of the two floating point numbers regardless of whether the operands or the result include normal or denormal numbers. The close path circuit may be configured to compute a close path result based upon the subtraction of the two floating point operands regardless of whether the operands or the result include normal or denormal numbers. The final result selector circuit may be configured to select between the far path result and the close path result based, at least in part, upon an amount of difference in the exponent portions of the two floating point operands.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: November 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Eric C. Quinnell
  • Patent number: 9760536
    Abstract: A method and device for reducing the computational complexity of a processing algorithm, of a discrete signal, in particular of the spectral estimation and analysis of bio-signals, with minimum or no quality loss, which comprises steps of (a) choosing a domain, such that transforming the signal to the chosen domain results to an approximately sparse representation, wherein at least part of the output data vector has zero or low magnitude elements; (b) converting the original signal in the domain chosen in step (a) through a mathematical transform consisting of arithmetic operations resulting in a vector of output data; (c) reformulating the processing algorithm of the original signal in the original domain into a modified algorithm consisting of equivalent arithmetic operations in the domain chosen in step (a) to yield the expected result with the expected quality quantified in terms of a suitable application metric; (d) combining the mathematical transform of step (b) and the equivalent mathematical operatio
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 12, 2017
    Assignee: Ecole Polytechnique Fédérale de Lausanne (EPFL)
    Inventors: Georgios Karakonstantis, Aviinaash Sankaranarayanan, Andreas Burg, Srinivasan Murali, David Atienza Alonso
  • Patent number: 9703525
    Abstract: Hardware logic arranged to normalize (or renormalize) an n-bit input number is described in which at least a proportion of a left shifting operation is performed in parallel with a leading zero count operation. In various embodiments the left shifting and the leading zero count are performed independently. In various other embodiments, a subset of the bits output by a leading zero counter are input to a left shifter and the output from the left shifter is input to a renormalization block which completes the remainder of the left shifting operation independently of any further input from the leading zero counter.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 11, 2017
    Assignee: Imagination Technologies Limited
    Inventor: Theo Alan Drane
  • Patent number: 9658827
    Abstract: A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: May 23, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess
  • Patent number: 9557963
    Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Scott Hilker
  • Patent number: 9549197
    Abstract: A system and method for enhancing data coherency and potential of at least one metadata associated with a video data configured to operate in a visual dynamic range (VDR) format are detailed. One system embodiment employs a metadata framing structure which includes a header start of frame bit set, a packet type bit set, a configuration bit set, a variable depth configuration/metadata bit set, a header end of frame bit set, a timestamp bit set for specifying a frame delay count to apply the at least one metadata to the video data and a checksum check bit set. The at least one metadata is designed to embed within a code word guard bit position of at least one color channel of the video data and adaptable to embed within the VDR pipeline to enhance the quality of the video data.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: January 17, 2017
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: Neil W. Messmer, Brent Wilson
  • Patent number: 9519456
    Abstract: A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 13, 2016
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess
  • Patent number: 9483232
    Abstract: A data processing apparatus and method are provided for multiplying first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalized version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalized floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalized result significand.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: November 1, 2016
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess
  • Patent number: 9329848
    Abstract: A mechanism is described for facilitating dynamic and efficient fusion of computing instructions according to one embodiment. A method of embodiments, as described herein, includes monitoring a software program for a program region having fusion candidate instructions for a fusion operation at a computing system; evaluating whether the macro operation of the candidate instructions is valuable to the software program; and performing the fusion operation if it is evaluated to be valuable.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Marc Lupon, Raul Martinez, Enric Gibert Codina, Kyriakos A. Stavrou, Grigorios Magklis, Sridhar Samudrala
  • Patent number: 9112464
    Abstract: A method and device for normalizing the power of an electrical signal, referred to as an original sound signal S1. The method detects the envelope of the original sound signal S1 and compares the power value of the envelope signal S2 with a threshold value K1. The gain signal S3 is calculated in accordance with the comparison and smoothed to obtain a smoothed gain signal S4. The original sound signal S1 is delayed by a delay T. The smoothed gain signal S4 is applied to the delayed original sound signal S1 to obtain a normalized sound signal S5. The method is suitable for a source including a plurality of channels.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: August 18, 2015
    Assignee: ARKAMYS
    Inventors: Frederic Amadu, Thomas Esnault, Alexandre Fenieres
  • Publication number: 20150106414
    Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 16, 2015
    Inventor: Eric B. Olsen
  • Patent number: 8862647
    Abstract: Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 14, 2014
    Assignee: NEC Corporation
    Inventor: Atsufumi Shibayama
  • Publication number: 20140297704
    Abstract: The present invention relates to a parallel device for solving linear equations over finite fields, including a processor, an input port, an output port, a pivot finding component, a partial inversion component, a normalization component and an elimination component. The processor is connected to each of the pivot finding component, the partial inversion component, the normalization component, the elimination component, and the input port and the output port. The partial inversion component is connected to the elimination component and the normalization component. The pivot finding component is connected to the elimination component. The present invention enables parallel computing to a certain extent with fast solving speed and simple design, and thus can be widely used in various engineering fields.
    Type: Application
    Filed: May 25, 2012
    Publication date: October 2, 2014
    Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Shaohua Tang, Haibo Yi
  • Publication number: 20140297703
    Abstract: A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a measurement vector set represented by a matrix H. Each of the measurements corresponds to a respective row of the matrix H. (For example, each of the measurements may correspond to an inner product between the signal and a respective row of the matrix product HD, wherein D is a generalized permutation matrix.) A total-variation primal-dual hybrid gradient (TV-PDHG) algorithm is executed based on data including the matrix H and the vector s, to determine an estimate for the signal. The TV-PDHG algorithm is implemented in fixed-point arithmetic.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 2, 2014
    Applicant: InView Technology Corporation
    Inventors: Thomas A. Goldstein, Matthew A. Herman
  • Publication number: 20140280405
    Abstract: A normalized n-bit value is converted into a normalized m-bit value in accordance with a predetermined rounding mode. An initial m-bit value is determined, where the bits of the initial m-bit value are equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the normalized n-bit value. An output state is selected based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode. The output state indicates how the normalized m-bit value is to be determined from the initial m-bit value. In accordance with the selected output state, the normalized m-bit value is determined to be equal to one of a plurality of candidate m-bit values, wherein the plurality of candidate m-bit values consists of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: IMAGINATION TECHNOLOGIES LIMITED
    Inventor: Thomas Rose
  • Publication number: 20140089361
    Abstract: Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision. A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 27, 2014
    Applicant: NEC CORPORATION
    Inventor: Atsufumi Shibayama
  • Patent number: 8650231
    Abstract: A programmable device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step. To conserve resources, rather than configuring the every intermediate operation to have the same mantissa size, in the internal format the mantissa size may start out smaller and grow after each operation.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: February 11, 2014
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 8639736
    Abstract: A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic frequency domain of an input signal; multiplying the calculated cyclo-stationary characteristic values with each other; and detecting the signal from the input signal based on the result of the multiplication.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: January 28, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sunmin Lim, Sang-Won Kim, Changhyun Park, Myung Sun Song, Gwangzeen Ko, Chang-Joo Kim
  • Patent number: 8631056
    Abstract: In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: January 14, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Shankar Krithivasan, Erich James Plondke, Lucian Codrescu, Mao Zeng
  • Patent number: 8626807
    Abstract: A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Maarten Boersma, Markus Kaltenbach, Michael Klein, Silvia Melitta Mueller, Jochen Preiss
  • Patent number: 8605841
    Abstract: A method is provided for processing received data symbols in an orthogonal frequency division multiplexing (OFDM) transmission scheme, and an OFDM baseband receiver which performs this method, in order to support frequency selective noise estimation, especially in interference limited environments, and to offer improved estimation performance and reduced computational complexity.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: December 10, 2013
    Assignee: Intel Mobile Communications Technology Dresden GmbH
    Inventor: Andreas Bury
  • Publication number: 20130312111
    Abstract: Embodiments of the invention broadly described, introduce systems and methods for combining multiple field values into a normalized value, generating codes using the normalized value, and using the codes as activation codes. One embodiment of the invention discloses a computer-implemented method for generating a code. The method comprises receiving a plurality of field values associated with a set of fields, each of the fields being associated with a field radix, converting the field values into numeric field values, combining, by a processor, numeric field values, each associated with a field, each of the fields associated with a field radix, to generate a normalized value, and generating, by the processor, a code representative of the plurality of field values using the normalized value.
    Type: Application
    Filed: March 11, 2013
    Publication date: November 21, 2013
    Inventors: Mark Carlson, Steven Cheatham
  • Patent number: 8554819
    Abstract: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Limited
    Inventor: Kunihiko Tajiri
  • Patent number: 8533250
    Abstract: Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: September 10, 2013
    Assignee: Altera Corporation
    Inventors: Kok Yoong Foo, Yan Jiong Boo, Geok Sun Chong, Boon Jin Ang, Kar Keng Chua
  • Patent number: 8533245
    Abstract: Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: September 10, 2013
    Assignee: Altera Corporation
    Inventor: Colman C. Cheung
  • Patent number: 8521529
    Abstract: An input signal is converted to a feature-space representation. The feature-space representation is projected onto a discriminant subspace using a linear discriminant analysis transform to enhance the separation of feature clusters. Dynamic programming is used to find global changes to derive optimal cluster boundaries. The cluster boundaries are used to identify the segments of the audio signal.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: August 27, 2013
    Assignee: Creative Technology Ltd
    Inventors: Michael M. Goodwin, Jean Laroche
  • Patent number: 8521793
    Abstract: A math engine is provided capable of supporting large complex mathematical computations, such as modulo math computations involved in cryptography, while remaining easily reconfigurable, upgradeable and scalable. As new algorithms and specifications are desired to be solved, the math engine can be easily updated to accommodate the new requirements. These systems employ layers of cells, wherein individual cells are responsible for calculations. Thus, the complexity of the mathematical computation is broken down into cells which are easily added, removed, changed or substituted. The cells may be interchangeable and programmable, and provide flexibility and reconfigurability to the system at low or near-zero cost. When additional algorithms are desired, additional appropriate cells are simply added or changed.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 27, 2013
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Kyle Gilsdorf, Clinton L Hardy
  • Patent number: 8510364
    Abstract: Methods for matrix processing and devices therefor are described. A systolic array in an integrated circuit is coupled to receive a first matrix as input; and is capable of operating in two modes, namely a triangularization mode and a back-substitution mode. The systolic array, when in a triangularization mode, is coupled to triangularize the first matrix to provide a second matrix. When in a back-substitution mode, the systolic array is coupled to invert the second matrix.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: August 13, 2013
    Assignee: Xilinx, Inc.
    Inventors: Raghavendar M. Rao, Christopher H. Dick
  • Patent number: 8499017
    Abstract: A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus 100 has multiplying circuitry 110 configured to multiply operands B and C to generate a product B*C having a high order portion 160 and a low order portion 170. The apparatus has adding circuitry 130 configured to: (i) add an operand A to one of the high order portion 160 and the low order portion 170 to generate an intermediate sum value; and (ii) add the intermediate sum value to a remaining one of the high order portion 160 and the low order portion 170 to generate a result A+B*C.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: July 30, 2013
    Assignee: ARM Limited
    Inventors: Antony John Penton, Simon John Craske, Ian Michael Caulfield
  • Patent number: 8495116
    Abstract: A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yoo-jin Baek
  • Patent number: 8495124
    Abstract: A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N?1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Adam B. Collura, Michael Kroener, Silvia Melitta Mueller
  • Patent number: 8484265
    Abstract: Circuitry for deriving a range-reduced value of an angle represented by a number having a mantissa and an exponent includes memory that stores a table that identifies, for each one of a plurality of values of the exponent, a base fractional rotation associated with said one of said plurality of values of said exponent, and an incremental fractional rotation associated with each increment of said mantissa. The circuitry further includes a multiplier that multiplies the mantissa by the incremental fractional rotation to provide a product representing a mantissa contribution. An adder adds the base fractional rotation to any fractional portion of the mantissa contribution. The fractional portion of the result of that addition represents the range-reduced angle. That representation can be multiplied by a constant representing one complete rotation in a desired angular measurement system, to convert that representation to a value representing the range-reduced angle in that measurement system.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 9, 2013
    Assignee: Altera Corporation
    Inventor: Martin Langhammer