Abstract: A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of the floating point adder. The leading zero anticipator outputs a control signal to a shifter to shift the sum of the significand adder to eliminate the leading zeros. The number of leading zeros is also provided to an exponent circuit that reduces the magnitude of the exponent to reflect the shifted significand. The leading zero anticipator includes a pattern generator that outputs an intermediate pattern with a number of leading zeros approximately equal to the number of leading zeros in the sum. A counter circuit counts the number of leading zeros and provides one or more one-hot control signals to the shifter. In one embodiment, the significand shifter implements two stages of one-hot multiplexers to provide the desired shift.

Abstract: A floating point result in a processor is efficiently normalized by predicting the mantissa shift required to normalize the result to an error of one bit position in one direction, resulting in minimum and maximum predicted shifts. Concurrently with an addition of operands to generate a result mantissa, an inversion of the minimum predicted shift is added to the operand exponent to generate an intermediate exponent corresponding to a maximum predicted shift. When the operand addition is complete, the result mantissa is partially shifted in response to the minimum predicted shift. The location of the leading one is then ascertained and compared to the remaining minimum predicted shift. If the minimum predicted shift is the actual shift required to normalize the result, the result mantissa is further shifted by the remaining minimum predicted shift and an exponent carry-in is asserted.

Abstract: Normalization circuitry comprises an AND gate for computing the AND of a reference signal generated from an exponent input with a mantissa input, and an OR gate for computing the OR of all the bits of the output of the AND gate. A leading one detector detects the bit position of the leading 1 of the mantissa input, and then generates a signal only one bit at the detected bit position of which is set to 1. A priority encoder then subtracts 1 from the number showing the bit position of the leading 1 counted from the most significant bit (MSB). A one-bit shifter shifts all the bits of the signal except its MSB from the leading one detector one bit position to the right.

Abstract: A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered.