Abstract: A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the exponent of the result may be adjusted due to normalization or renormalization. The exponent adjustment due to renormalization or the exponent adjustment due to normalization and renormalization is combined with the significand rounding operation.

Abstract: A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

Abstract: A data processing apparatus and method are provided for normalizing a data value to produce a result value. The data processing apparatus includes prediction logic for generating a shift indication based on a prediction of the number of bit positions by which the data value needs to be shifted in order to normalize the data value. Further, normalizer logic is used to apply a shift operation to the data value based on the shift indication. In addition, correction logic is operable in parallel with the normalizer logic to determine from the data value and a least significant bit of the shift indication whether the shift indication has correctly predicted the number of bit positions by which the data value needs to be shifted in order to normalize the data value, or whether instead the prediction is incorrect, and to generate an output signal dependent on that determination.

Abstract: Provided are methods of using electromagnetic waves for detecting metal and/or dielectric objects. Methods include directing microwave and/or mm wave radiation in a predetermined direction using a transmission apparatus, including a transmission element; receiving radiation from an entity resulting from the transmitted radiation using a detection apparatus; and generating one or more detection signals in the frequency domain using the detection apparatus. Methods may include operating a controller, wherein operating the controller includes causing the transmitted radiation to be swept over a predetermined range of frequencies, performing a transform operation on the detection signal(s) to generate one or more transformed signals in the time domain, and determining, from one or more features of the transformed signal, one or more dimensions of a metallic or dielectric object upon which the transmitted radiation is incident.

Abstract: A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit.

Abstract: A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the initial flow an output state, the occurrence of a word, all the bits of which have identical states, alternately resulting in the assignment of a first state or of a second one.

Abstract: A review system and method gathers and analyzes data related to ownership of and encumbrances on intellectual property assets from relevant recordation locations. The system and method analyzes the data and interprets the data and the chain of ownership of intellectual property assets.

Abstract: A biosensor system determines analyte concentration from an output signal generated by an oxidation/reduction reaction of the analyte. The biosensor system adjusts a correlation for determining analyte concentrations from output signals at one temperature to determining analyte concentrations from output signals at other temperatures. The temperature-adjusted correlation between analyte concentrations and output signals at a reference temperature may be used to determine analyte concentrations from output signals at a sample temperature.

Abstract: Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.

Abstract: Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.

Abstract: A detecting method over network intrusion comprises: selecting a plurality of features contained within plural statistical data by a data-transforming module; normalizing a plurality of feature values of the selected features into the same scale to obtain a plurality of normalized feature data; creating at least one feature model by a data clustering technique incorporated with density-based and grid-based algorithms through a model-creating module; evaluating the at least one feature model through a model-identifying module to select a detecting model; and detecting whether a new packet datum belongs to an intrusion instance or not by a detecting module.

Abstract: A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural format based on an operation code and a data type of a microinstruction.

Abstract: A frequency domain transforming section 2 transforms mixed signals observed by multiple sensors into mixed signals in the frequency domain, a complex vector generating section 3 generates a complex vector by using the frequency-domain mixed signals, a normalizing section 4 generates a normalized vector excluding frequency dependence of the complex vector, and a clustering section 5 clusters the normalized vectors to generate clusters. Then, a separated signal generating section 6 generates separated signals in the frequency domain by using information about the clusters and a time domain transforming section 7 transforms the separated signals in the frequency domain into separated signals in the time domain.

Abstract: Methods and apparatus for identifying disease status according to various aspects of the present invention include analyzing the levels of one or more biomarkers such as riboflavin carrier protein (RCP). The methods and apparatus may process the biomarker data, for example by normalizing the RCP concentration data. The RCP data may be used to detect diseases, such as cancer.

Abstract: In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and two sub-moduli. In order to improve the safety of the RSA CRT calculations against cryptographic attacks, a randomization of the auxiliary exponents and/or a change of the sub-moduli are performed. Thus, there is a safe RSA decryption and RSA encryption, respectively, by means of the calculating time efficient Chinese Residue Theorem.

Abstract: In order to provide an exponent encoder circuit for obtaining an exponent constituted by a left shift amount for normalizing input data with code bits, there is provided a first logic circuit for inverting data portions other than code bits and shifting the code bits to least significant bit positions when inputted data is a negative number and allowing data portions other than the code bits to pass as is and moving the code bits to least significant bit positions when the inputted data is a positive number, and a second logic circuit for putting a plurality of logic operation equations for obtaining each bit of an exponent from output of the first logic circuit as decided by a truth table for outputs of the first logic circuit and corresponding exponents in a form where common terms are cancelled out.

Abstract: A extendable method for including display rendering metadata within Unicode character streams. Metadata is distinct from character data, even though it is embedded in the Unicode character stream using tag mechanism. The method allows for an unlimited number of tag identifiers. Legacy Unicode methods such as Bidi, Normalization, and Line Breaking, can be recast using the invention in a more manageable context according to the metadata framework, thereby allowing the methods to be detectable, reversible as well as convertible. The traditional Unicode Control Layer is eliminated because the syntax of controls are captured universally by the new Metadata Layer, irrespective of whether the control relates to presentation or pcontent. By replacing the indistinct boundary separating characters and control with a well defined division, applications that rely on Unicode are easier to develop and to maintain.

Abstract: Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.

Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Abstract: The processing elements if a single instruction multiple data (SIMD) massively parallel processor (MPP) are provided with two register blocks. One register block includes logic for performing limited left shifting, while the other register block includes logic for performing limited right shifting. A method is disclosed for using the registers blocks with their associated logic to perform floating point significand alignment and normalization. The limited shifting logic occupies less die space than a full feature barrel shifter, thereby permitting a greater number of processing elements.

Abstract: Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “?1” respectively, sum-of-product calculation section 207 multiplies the data output from data conversion section 206 by the demodulated data (soft decision value) stored in demodulated data storage section 201 and then calculates the sum of the products for 1 TTI and stores the sum-of-product result for each data rate, data rate decision section 208 decides the data rate corresponding to a maximum value of the sum-of-product results as the data rate of the demodulated data. This makes it possible to improve the accuracy of data rate decision and reduce decoding errors of a received signal.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: A method of determining a biased leading-zero count for a floating-point operation is disclosed. First, a binary vector is divided into subvectors. Then, multiple subvector leading-zero counts are generated. The subvector leading-zero counts are biased by a constant amount. Next, one or more prefix bits are calculated. Finally, at least a portion of a selected subvector leading-zero count is concatenated to the prefix bits to yield a total leading-zero count for the binary vector.

Abstract: In a renormalization processing device of MQ-CODER, the value of an augend register A is calculated by a shift quantity calculating unit without performing loop processing, and the number of left shifts SHIFT_A of A up to the end of renormalization processing is calculated. The renormalization processing device judges whether byteout processing or bytein processing occurs or not, on the basis of the positive or negative sign of (SHIFT_A-CT) and the value of CT. When byteout/bytein processing occurs, the values of a code register C and a free byte counter CT that are immediately before the occurrence of processing are found. When byteout/bytein processing does not occur, the values of C and CT that are after the end of normalization processing are found. If the value of (SHIFT_A-CT) is a positive value after byteout/bytein processing, this value is substituted in SHIFT_A and renormalization processing is performed again.

Abstract: An exponent unit receives an operand and outputs an exponent of the operand that is equal to the number of consecutive bits of the operand that have the same value as the most significant bit (MSB) of the operand. The exponent unit can obtain an exponent value of an operand having a bit width that is greater than a processing bit width of a leading one detector (or a leading zero detector).

Abstract: An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module generates second detection bits from the first and second operands, where the second detection bits indicate a difference of one. A combiner combines the first and second detection bits to determine whether the difference of two numbers is less than two. The apparatus and method is used in determining to bypass normalization in floating point calculation.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.

Abstract: In a renormalization processing device of MQ-CODER, the value of an augend register A is calculated by a shift quantity calculating unit without performing loop processing, and the number of left shifts SHIFT_A of A up to the end of renormalization processing is calculated. The renormalization processing device judges whether byteout processing or bytein processing occurs or not, on the basis of the positive or negative sign of (SHIFT_A-CT) and the value of CT. When byteout/bytein processing occurs, the values of a code register C and a free byte counter CT that are immediately before the occurrence of processing are found. When byteout/bytein processing does not occur, the values of C and CT that are after the end of normalization processing are found. If the value of (SHIFT_A-CT) is a positive value after byteout/bytein processing, this value is substituted in SHIFT_A and renormalization processing is performed again.

Abstract: A method and system that include a first measurement signal and a second measurement signal that can be input to first and second filters. The filters can be subject to a first constraint to minimize the energy difference between the first and second measurement signals on a per frequency basis, and subject to a second constraint that includes a model frequency and phase response. By adapting the filters subject to the two constraints, coherent differences between the two measurement signals can be identified. In one embodiment, the system can be applied to Synthetic Aperture Radar (SAR) data.

Abstract: A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference, a first bit inverter, an adder, a leading-zero anticipation circuit for anticipating the consecutiveness of leading zeros from the significands, a leading-zero counter for counting the anticipated number of leading zeros, a left shifter for shifting an output value from the adder, a second bit inverter for taking two's complement of an output value from the left shifter, an incrementer for incrementing an output value from the second bit inverter by one, a compensation shifter for shifting an output value from the incrementer, an exponent subtracter for subtracting the number counted by the leading-zero counter from the larger exponent, and a decrementer for decrementing an output exponent from the exponent subtracter by one.

Abstract: An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.

Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.

Abstract: An apparatus and method for determining whether two operands are less than two are disclosed. A first module generates first detection bits from a first operand and a second operand, where the first detection bits indicate a difference of zero. A second module generates second detection bits from the first and second operands, where the second detection bits indicate a difference of one. A combiner combines the first and second detection bits to determine whether the difference of two numbers is less than two. The apparatus and method is used in determining to bypass normalization in floating point calculation.

Abstract: A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

Abstract: A method and circuit for adjusting an exponent of an unnormalized floating-point number to generate an exponent of a normalized floating-point number. The method includes the steps of: (1) generating a shift count indicating the number of bit positions, if any, a mantissa of an unnormalized floating-point number is to be left shifted to normalize the unnormalized floating-point number, (2) generating a right shift indicator indicating the number of bit positions, if any, the mantissa is to be right shifted to normalize the unnormalized floating-point number, (3) incrementing the value of an exponent of the unnormalized floating-point number, (4) concurrently with the incrementing step, complementing a plurality of bits of the shift count and (5) adding the exponent, the shift count and the right shift indicator to generate an exponent of a normalized floating-point number. The method and circuit may be implemented in a floating-point adder.

Abstract: An shift circuit is used in an arithmetic unit, for shifting m-bit input data to left or in right, m being a positive integer. The shift circuit includes a latch for temporarily storing the m-bit input data and additional 2n-bit, wherein n is a positive integer; a shift logic block, receiving (m+2n)-bit data from the latch means, for providing (2n+1) number of m-bit shifted data; a sensor for generating a selection signal based on a predetermined shift condition; and a multiplexer, in response to the selection signal, for selecting one of the (2n+1) number of m-bit shifted data as an output signal of the apparatus.

Abstract: A vector normalizing apparatus in which information concerning the norm of the original vector is not lost by normalization, and which needs no device that divides vector components by norm. The apparatus includes a vector input device (1) for entering a vector. An additional component calculating device (2) receives the vector entered through the vector input device (1) and calculates an additional component to be added to the vector such that norm of the vector after the addition of the component becomes constant. A vector component adding device (3) adds an output from the additional component calculating device (2) as a component of the entered vector. A normalized vector output device (4) outputs the vector having the component added thereto.

Abstract: The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for shifting of the intermediate result prior to normalization or rounding. The exponent is pre-incremented prior to normalization. During normalization, the most significant bit of the intermediate fraction is shifted into the carry bit and the exponent is decremented accordingly. Selection logic then selects one of six possible formatting procedures to generate a mathematically correct output fraction in proper ANSI/IEEE 754-1985 floating point format, and formatting logic generates the output fraction according to the selected formatting procedure.

Abstract: A method for anticipating leading zeros/ones in a floating-point processor is disclosed. A leading zeros string and a leading ones string is generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is calculated directly and concurrently from the leading zeros string and the leading ones strings prior to a determination of a sign of an output of the positive sum and the negative sum.

Abstract: The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is pre-incremented by one prior to normalization. During normalizaion, the most significant binary “1” of the fraction is shifted left until it resides in the carry bit. For each left shift performed, the incremented exponent is decremented once.

Abstract: The present invention describes an apparatus and method to select the format of the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The C bit and the L bit and the most significant bit of the intermediate fraction are examined, along with the Gin bit, Rin bit, and round control bit. Based on these inputs, the output fraction is formatted by performing zero or more manipulations of either the output of the rounder circuit or the output from the normalizer circuit.

Abstract: A method and circuit for determining the position of a leading logical one or a trailing logical one in a first n bit operand is disclosed. The method and circuit generates an n bit operand from the first n bit operand. One bit of the n bit operand represents a first logical value while the remaining bits of the n bit operand represent a second logical value. Thereafter, the method and circuit generates a k bit operand relating to the position of the leading or trailing logical one in the first n bit operand. The k bit operand is generated from the n bit operand.

Abstract: The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.

Abstract: A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each segment. Each segment undergoes all zeros detection, all ones detection, modified zeros detection, and modified ones detection. The modified zeros detection and modified ones detection are both done based on the control field. Each detection for each segment generates a response. Then, a pair of the four responses, or a clear responses signal, is selected for each of the segments based on the control field. From the selected responses, the method determines if the normalized data field is all zeros or all ones.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: With the use of outputs of priority encoders serving as selection signals, final carry signals at respective bits in an adder can be selected as signals indicating whether or not prediction error is present. Accordingly, it is possible to detect earlier whether or not prediction error in a cancelling bit prediction circuit is present.

Abstract: An optimized multimedia execution unit configured to perform vectored floating point and integer instructions. In one embodiment, the execution unit includes an add/subtract pipeline having far and close data paths. The far data path is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path, conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The execution unit may also include a plurality of add/subtract pipelines, allowing vectored add, subtract, and integer/floating point conversion instructions to be performed. The execution unit may also be expanded to handle additional arithmetic instructions (such as reverse subtract and accumulate functions) by appropriate input multiplexing.

Abstract: An apparatus for data normalization includes a FIFO buffer for receiving input data words, an input register for receiving a first data word from the FIFO buffer, and a combinatorial circuit for transforming the first data word in the input register and a subsequent data word from the FIFO buffer into a normalized output data word. The apparatus utilizes two or more independent instruction streams to increase the processing speed of the apparatus.

Abstract: If the exponents of a floating-point-processor addition pipeline's input operands are equal, a signal (INVERT) that determines whether the pipeline's sole full-width carry-propagate mantissa adder (34) will invert one of its inputs results from an inversion-determination circuit (FIG. 11) that determines whether the sole set bit in a decoded normalization-shift signal (NORM.sub.-- SHIFT) occupies the same position as a set bit in a signal (FRAC.sub.-- A.sub.-- GT.sub.-- B) representing what the possible normalization amounts will be if a first of the mantissas is greater than the other, second mantissa. Consequently, a bit-comparison operation (56) that employs no full-width carry-propagate addition can determine the amount of normalization shifting to be performed by bit shifters (30 and 32) disposed in respective processing trains that generate mantissa inputs to the mantissa adder (34).