Abstract: An integrated circuit including a plurality of processing components to process image data of a plurality of image frames, wherein each image frame includes a plurality of stages. Each processing component includes a plurality of execution pipelines, wherein each pipeline includes a plurality of multiplier-accumulator circuits configurable to perform multiply and accumulate operations using image data and filter weights, wherein: (i) a first processing component is configurable to process all of the data associated with a first plurality of stages of each image frame, and (ii) a second processing component of the plurality of processing components is configurable to process all of the data associated with a second plurality of stages of each image frame. The first and second processing component processes data associated with the first and second plurality of stages, respectively, of a first image frame concurrently.

Abstract: A filter device includes: delay units serially connected to delay an input signal and output a delayed signal; multiplication units multiplying the delayed signal by a filter coefficient based on a predetermined value and a multiplying factor adjustment value; a coefficient adjustment unit that, when a multiplication result obtained by multiplying the predetermined value by the multiplying factor adjustment value exceeds a maximum value of a filter-coefficient representation range, divides the multiplication result exceeding the maximum value by the maximum value, and outputs a quotient of division as a coefficient adjustment value; a signal conversion unit outputting a signal obtained by adding after-filter-coefficient-multiplication signals outputted by the multiplication units and an adjusted signal obtained by adjusting a corresponding delayed signal using the coefficient adjustment value; and a division unit generating an output signal by dividing the signal outputted by the signal conversion unit by the

Abstract: A filter circuit includes multiple registers, a switch circuit, multiple multipliers and a summation circuit. Each register is configured to store an input. The switch circuit is coupled to the registers and configured to receive the inputs from the registers as a series of registered inputs and adjust arrangement of the inputs of the series of registered inputs to generate a series of rearranged inputs according to a count value. The count value is accumulated in response to reception of a new input of the filter circuit. The multipliers are coupled to the switch circuit. The inputs of the series of rearranged inputs are sequentially provided to the multipliers. Each multiplier is configured to generate a multiplication result according to the received input and a coefficient. The summation circuit is coupled to the multipliers and configured to sum up the multiplication results to generate an output.

Abstract: An arithmetic device includes an arithmetic circuit configured to perform an arithmetic operation to output arithmetic result data and a data output unit configured to feedback bias data to the arithmetic circuit prior to the arithmetic operation.

Abstract: A method, a system, and a device for transmitting data through an earphone and a computer storage medium are provided. A first data type of to-be-transmitted data is acquired, a second data type set for an FIR filter coefficient is acquired, and a sum of the number of decimal places indicated by the first data type and the number of decimal places indicated by the second data type is determined. A data type which indicates a number of decimal places that is at least two orders more than the sum is determined among preset data types as a third data type of an FIR filtering result, and FIR filtering is performed on the to-be-transmitted data to obtain a target filtering result and transmit the target filtering result.

Abstract: Provided are a programmable device for processing a data set, and a method for processing a data set. The programmable device includes a plurality of accumulation circuits, wherein each of the accumulation circuits includes a pipeline adder and a cache unit for storing a computation result of the pipeline adder; and a multiplexer for receiving in sequence data in a data set, dynamically determining a correlation between a plurality of features included in the data and the plurality of accumulation circuits, and respectively sending, according to the correlation, feature values of the plurality of features in the received data to corresponding accumulation circuits.

Abstract: An apparatus and method for performing multiply-accumulate (MAC) operations on complex numbers to generate real results.

Abstract: A filter is disclosed. The filter includes at least one first multiplication approximation unit, for approximating at least one first multiplication operation corresponding to at least one first coefficient with at least one first bit-wise shift operation; and at least one second multiplication approximation unit, for approximating at least one second multiplication operation corresponding to at least one second coefficient with a plurality of second bit-wise shift operations and at least one addition operation.

Abstract: A receiver circuit is disclosed. The receiver circuit includes a multi-PAM input circuit to receive a multi-PAM input symbol. The input symbol exhibits one of multiple threshold levels during a sampling period. The threshold levels correspond to a set of M-bit two's-complement values within a defined set of threshold values. An adaptive filtering circuit includes a first transcoder to transcode the set of M-bit two's-complement values to a set of N-bit values, where N<M. An adaptive filter operates to filter the set of N-bit values to generate a filtered set of data values. A second transcoder transforms the filtered set of data values to a second set of data values that corresponds to a set of filtered M-bit two's-complement values.

Abstract: Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices is disclosed. In this regard, a matrix-processor-based device provides a central processing unit (CPU) and a matrix processor. The matrix processor reorganizes a plurality of weight matrices and a plurality of input matrices into swizzled weight matrices and swizzled input matrices, respectively, that have regular dimensions natively supported by the matrix processor. The matrix-processor-based device then performs a convolution operation using the matrix processor to perform matrix multiplication/accumulation operations for the regular dimensions of the weight matrices and the input matrices, and further uses the CPU to execute instructions for handling the irregular dimensions of the weight matrices and the input matrices (e.g., by executing a series of nested loops, as a non-limiting example).

Abstract: Systems and methods are described for performing interference-resistant calibration and compensation of radio-frequency (RF) and analog front-end electronics of antenna-array based receivers during active operation. Examples of systems and methods are described herein that may provide interference-resistant calibration maintenance and ongoing compensation for changing gain and phase in receiver front-end electronic components, due to manufacturing tolerances and operational and environmental factors such as variations in temperature, humidity, supply voltage, component aging, connector oxidation, mechanical stresses and vibration, and/or maintenance operations such as sparing and swapping of cables, front-end electronics modules, and/or associated circuitry.

Abstract: To reduce a hardware circuit scale and a memory capacity in a communication system reducing a PAPR. A transmitter includes a transmission processing feedback type FIR filter configured to feed back data outputted from the last stage delay element of a plurality of delay elements included in an FIR filter to the first stage delay element and configured to set an initial value to a delay element in a predetermined position, of the delay elements, and performs transmission processing by using the transmission processing feedback type FIR filter. A receiver includes a reception processing feedback type FIR filter configured similarly to the transmission processing feedback type FIR filter and performs reception processing by using the reception processing feedback type FIR filter.

Abstract: Techniques are disclosed relating to performing arithmetic operations to generate values for different related threads. In some embodiments, the threads are graphics threads and the values are operand locations. In some embodiments, an apparatus includes circuitry configured to generate results for multiple threads by performing a plurality of arithmetic operations indicated by an instruction. In some embodiments, the instruction specifies: an input value that is common to the multiple threads and, for at least one of the multiple threads, a type value that indicates whether to generate a result for the thread by performing an arithmetic operation based on a first input that is a result of an arithmetic operation from another thread of the multiple threads or to generate a result for the thread using the input value that is common to the multiple threads.

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

Abstract: A reconfigurable discrete time analog signal processor includes a finite impulse response (FIR) filter configured to receive a portion of an RF transmit signal, to receive FIR coefficients, and to generate a leakage cancellation signal based on the portion of the RF transmit signal and the FIR coefficients, the FIR filter including sample and hold (SH) circuits configured to receive the portion of the RF transmit signal, to sample the portion of the RF transmit signal at successive sample times according to a sample clock, and to generate sampled analog voltage signals, and analog multipliers coupled to the SH circuits and configured to multiply the sampled analog voltage signals by binary multiplication factors to generate the leakage cancellation signal.

Abstract: A system and method for performing sample rate conversion by an execution unit, including receiving an instruction, where the instruction comprises an irregular shifting pattern of data elements stored in a vector register, and shifting the data elements in the vector register according to the irregular shifting pattern. In case of upsampling the irregular shifting pattern includes an indication stating whether a memory element loads a data element from an immediate next memory element or from a second next memory element. In case of downsampling the irregular shifting pattern includes an indication stating whether a memory element in the input vector register loads a data element from an immediate next memory element, or whether the memory element loads a data element previously stored in a shadow vector register and the data element stored in the immediate next memory element is loaded into the shadow vector register.

Abstract: A system includes an integrated circuit coupled to the memory. The integrated circuit is configured to receive first and second complex numbers at one or more data inputs. A first value is determined using a first set of product arrays of a first real number multiplier. A second value is determined using a second set of product arrays of the first real number multiplier and a third set of product arrays of a second real number multiplier. A third value is determined using a fourth set of product arrays of the second real number multiplier. A real value of a first product of the first complex number times a second complex number is determined using the first value and the second value. An imaginary value of the first product is determined using the second value and the third value.

Abstract: A particular computer-implemented method includes receiving sensed data from sensors of a sensor array, where data from each sensor is descriptive of waveform phenomena detected at the sensor. The method also includes determining an estimated spatial spectrum of the waveform phenomena based at least partially on the sensed data. The method further includes determining an estimated covariance matrix of the waveform phenomena based on the estimated spatial spectrum. The method includes determining adaptive beamforming weights using the estimated covariance matrix.

Abstract: Device for vibration compensation of weighing sensor weight signals, with a weighing signal branch having an analog/digital converter unit to which a weighing sensor analog weighing signal is fed, and that generates a digital weighing signal that contains discrete sample values of the sampled analog weighing signal of the weighing sensor. At least one compensation signal branch has an analog/digital converter unit to which an acceleration sensor analog noise quantity is fed for detecting a specified acceleration noise quantity, and that generates a digital noise quantity signal containing discrete sample values of the acceleration sensor analog noise quantity signal. The digital noise quantity signal is fed to an adaptive digital filter unit. An addition unit sums the signal values of the digital weighing signal and the signal values (carrying a negative sign) for the digital noise quantity signals fed to it.

Abstract: A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract: The invention addresses the problem of parameter optimization for best filter performance and, in particular, the influence from the requirements on radio or fiber to radio repeaters utilizing those filters, that often proves to be conflicting for an FIR filter. The FIR filters are implemented in a programmable circuit and are not thereby restricted for use in communication repeaters although this particular usage may put the most serious restrictions on the filter performance. Within the imposed constraints, this disclosure illustrates a method to strike a middle ground while minimizing the trade-offs. The advantage of the concept presented allows the choice of a suitable filter pertaining to a particular traffic configuration, meaning a particular choice of individually filtered frequency bands set at different gain and intended to support a diversity of traffic formats. The disclosed approach banks on the reconfigurable variable length FIR filter architectures.

Abstract: A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.

Abstract: A filter and method for finite impulse response filtering an input signal is described. In one embodiment, the filter includes an input circuit configured to receive input samples in parallel, where the parallel input samples correspond to sequential samples of the input signal. In another embodiment, the filter includes a coefficient memory configured to store filter response coefficients and output a subset of those coefficients corresponding to a selected decimation factor.

Abstract: An integrated circuit configured to perform finite impulse response filtering on a signal transmitted via a communication channel, the integrated circuit including an encoder and a plurality of filter stages. The encoder is configured to generate a logic signal corresponding to the signal transmitted via the communication channel. The plurality of filter stages is configured to filter the logic signal. Each of the plurality of filter stages includes a respective delay element. Each of the respective delay elements is configured to delay a corresponding portion of the logic signal. Two or more first delay elements of the plurality of delay elements are configured to apply a fixed delay. A second delay element of the plurality of delay elements is configured to apply a variable delay that is based on a signal strength of the corresponding portion of the logic signal.

Abstract: A finite impulse response (FIR) extractor includes at least one controller. The controller injects specified FIR tap values into a first captured waveform that results from transmitting a raw waveform through a transmitter circuit including a FIR filter having pre and post cursor tap values set to zero to create an expected waveform, and injects the specified FIR tap values into the raw waveform to create an ideal waveform. The controller further projects the expected and ideal waveforms onto a second captured waveform that results from transmitting the ideal waveform through the transmitter circuit with the pre and post cursor tap values set to the specified FIR tap values to create a compensated waveform, and extracts FIR tap values from the compensated waveform.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter.

Abstract: Provided is an FIR filter capable of obtaining predetermined characteristics with a small number of input taps, delay circuits, and multipliers and achieving an improved response and low cost. In a low-pass filter, a band-pass filter, and a high-pass filter based on an FIR filter, a basic filter is configured that gives a basic impulse response function and has a filter coefficient determined from the impulse response function. Filters having different frequency characteristics are configured by changing the time scale or frequency scale of the basic filter. These filters having different frequency characteristics are combined in a cascade form or a step form, thereby constructing an FIR filter having a small number of taps.

Abstract: New hybrid filters are presented based on time and transform domain structures. The hybrid filters have a combined benefit from the advantages obtained by the time and transform domain structures. The overall efficiencies are drawn from combining the pre- and post-processing of the time domain and block based transform domain structures. Further improvements are obtained by interchanging block construction and transforms with linear operations in the pre- and post-processors. The hybrid structures apply to single input, single output, multiple input, and multiple output structures. For the multi input and multi output structures further improvements are obtained by having common processing blocks for the input(s) and common processing blocks for the output(s). They hybrid filters are also efficient in topologies where filter outputs are combined via linear operation(s) generating combined results.

Abstract: A filter can include a first channel and a second channel. The first channel can be configured to process a first term and a second term of an input vector using a first coefficient and a second coefficient of the filter. The first channel can be configured to generate a first term of an output vector. The second channel can be configured to process the first term and the second term of the input vector using the first coefficient and the second coefficient of the filter. The second channel can be configured to generate a second term of the output vector. The first and second channels can be configured to operate in parallel.

Abstract: A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution.

Abstract: An adaptive filter configured to filter an input signal comprises Fourier transforming unit configured to transform the input signal into a frequency domain signal upon the basis of the Fourier transform, weighting unit configured to weight at least a portion of the frequency domain signal with a filter coefficient of the dispersion filter in frequency domain to obtain a filtered signal in frequency domain, correlating unit configured to correlate the filtered signal in frequency domain to obtain a correlation value, and adaptation unit configured to adapt the filter coefficient upon the basis of the correlation value.

Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.

Abstract: A smoothing apparatus for peak windowing includes an operator for generating a first input signal for smoothing using an input signal for peak windowing and a predetermined clipping threshold level. The apparatus also includes a subtractor for subtracting a feedback signal from the first input signal, and a maximum operator for generating a second input signal. The apparatus also includes a feedback path for generating a feedback signal for a next smoothed input signal by multiplying samples of the second input signal by window coefficients in a first window coefficient combination and a predetermined gain and summing up the multiplication results. The apparatus further includes a convolutional operator for generating a smoothed signal by multiplying samples of the second input signal by window coefficients in a second window coefficient combination for low pass filtering and summing up the multiplication results.

Abstract: The present invention relates to a method for processing a digital input signal by a Finite Impulse Response, FIR, filtering means, comprising partitioning the digital input signal at least partly in the time domain to obtain at least two partitions of the digital input signal; partitioning the FIR filtering means in the time domain to obtain at least two partitions of the FIR filtering means; Fourier transforming each of the at least two partitions of the digital input signal to obtain Fourier transformed signal partitions; Fourier transforming each of the at least two partitions of the FIR filtering means to obtain Fourier transformed filter partitions; performing a convolution of the Fourier transformed signal partitions and the corresponding Fourier transformed filter partitions to obtain spectral partitions; combining the spectral partitions to obtain a total spectrum; and inverse Fourier transforming the total spectrum to obtain a digital output signal.

Abstract: According to some embodiments, a device is configured to perform a dual multiply-accumulate operation. In one embodiment, the device includes a functional unit configured to calculate, in parallel, a first multiplication product of a first coefficient and a first sample; and a second multiplication product of the first coefficient and a second sample. The first sample is an (n)th sample and the second sample is an (n+2)th sample in a plurality of sequential samples. The functional unit outputs and stores the first multiplication product and the second multiplication product in different storage locations in at least one storage device.

Abstract: A method and system for the design and implementation of an inverse-sinc function that can efficiently process signals produced by high-speed systems is presented. An integrated inverse-sinc module accepts multiple data streams that may result from parallel sub-systems and creates multiple outputs that can be interleaved to produce a sequence that has been filtered by an inverse-sinc function. The multiple-input, multiple-output system may be beneficially operated at a low data rate, such as the data rate used by each of the sub-systems.

Abstract: A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block.

Abstract: A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients.

Abstract: A digital optimal filter having an especially sinusoidal pulse response uses a filter structure with a recursive and a transversal portion. The transversal portion comprises filter coefficients for the representation of scan results of half a period of the sinusoidal pulse response signal. The recursive filter structure is used to change the sign after generation of the scan results for half a period and to mark the start and the end of the pulse response. A plurality of periods can lie in between the start and the end of the pulse response, this is why the digital optimal filter can be used to extract especially sinusoidal burst signals from an original signal, namely in digital technology, which is advantageous for the implementation of IC's.

Abstract: Aspects of a method and system for efficient full resolution correlation may include correlating a first signal with a second signal at a rate corresponding to a first discrete signal, wherein each sample of the first signal may be generated by summing a plurality of consecutive samples from the first discrete signal, and the second signal may be generated by summing the plurality of consecutive samples from a second discrete signal. The correlating may be performed by a matched filter and/or a correlator. The first signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the first discrete signal comprising N*L samples. The second signal comprising N samples may be generated by summing L consecutive samples for each of the N samples from the second discrete signal comprising N*L samples.

Abstract: A signal processing circuit has two types of filters: an IIR filter 11 and an FIR filter 12 having an equivalent transfer function at all times. In an adjustment mode in which the signal processing circuit is adjusted to have an arbitrary transfer function, the signal processing circuit makes a configuration setting to use the IIR filter 11. When completing the adjustment or in a signal processing mode, the signal processing circuit makes a configuration setting change to switch to the FIR filter 12 having the equivalent transfer function.

Abstract: Provided is a signal processing apparatus for compensating for a non-linear distortion of a digital signal, including: an analysis signal generating section that converts the digital signal into a analysis signal of a complex number, using a digital filter; and a compensation section that compensates for the analysis signal, using a compensation coefficient of a complex number corresponding to the non-linear distortion, where the digital filter divides data of the digital signal into “n” data sequences, assigns (n*L+k)th data of the digital signal to a k-th data sequence, performs filtering on each of the data sequences using a same filter coefficient, and combines each of the data sequences after the filtering, thereby generating an imaginary number portion of the analysis signal, where “n” is an integer equal to or greater than 2, L=0, 1, . . . , and k=1, 2, . . . , n.

Abstract: An equalization filter is provided for solving the problem in which there is a limited range in which compensated for distortion of a transmission signal can be made. Measuring instrument 104 measures a distortion quantity which characterizes distortion of the transmission signal. Comparator 105a generates a differential signal which indicates the difference between the transmission signal and a compensation signal. Delay device 105b delays the differential signal based on the distortion quantity measured by measurement instrument 104 and generates the compensation signal.

Abstract: An embodiment of a method for control of signal level is disclosed. In such an embodiment, a number for a pre-cursor set, a number for a cursor set, and a number for a post-cursor set are set corresponding to a weighted contribution of a pre-cursor symbol, a weighted contribution of a cursor symbol, and a weighted contribution of a post-cursor symbol, respectively, for the signal level. A number associated with a high-impedance set is determined. The number associated with the high-impedance set is determined by subtracting the number for the pre-cursor set, the number for the cursor set, and the number for the post-cursor set from a total available amount of units. The high-impedance set provides no weighted contribution to the signal level. Data is transmitted using the signal level set responsive to the pre-cursor set, the cursor set, and the post-cursor set.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity function. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal. At least one ISC vector may be generated by buffering samples of the phase adjusted ISC signal.

Abstract: A digital equalizer with a reduced number of multipliers for correction of the frequency responses of an interleaved ADC is disclosed. An exemplary interleaved analog to digital converter with digital equalization includes a composite ADC including M time interleaved sub-ADC, a demultiplexer, samples repositioning unit, a first PreFIRs transformer, a second PreFIRs transformer, K double buffer FIR filters, a PostFIRs transformer, a samples sequence restoration unit, and a multiplexer, coupled in series and providing an equalized, frequency response-corrected output.