Abstract: A digital filter function requires many coefficient multiplications. Instead of implementing the multiplications individually as multipliers, they may be implemented using traverse or shift operations. This approach uses the relation among the coefficients of the digital filter to reduce required hardware. A disclosed digital filter uses scalers and sample combiners for processing samples of a digital input stream. Each scaler scales a respective input sample from one of the combiners, preferably by a different power of 2. The combining circuits combine sets of samples, from the digital input stream and from the digital output of the filter, to form the input samples for processing by the scalers. An adder totals the respective scaled values, to form the digital output stream of the filter. The digital filter may be used in a variety of digital signal processing applications, but is particularly useful in low-power portable devices, such as wireless spread-spectrum receivers.

Abstract: A method and an apparatus for a channel estimator comprising a plurality of distinct filters each of which has a set of different coefficients and each of which is selectively coupled to the input and output of the channel estimator. The channel estimator further comprises a switching circuit that receives an error signal and switches to one of the plurality of filters based on the value of the error signal relative to an established threshold. The error signal is from a decoder coupled to a communication channel whose response is being estimated by the apparatus and method of the present invention.

Abstract: A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: A filter (50) with interconnected modular basic units (10) and with a delay line (51), equipped with takeoff points, to furnish delayed sampling values (x1, . . . , xN; xi) of a digital signal (x). Each basic unit (10) contains a programmable weighting device (11, 12), a linkage device (13, 14), and a delay device (15), which delays the data conducted to it by a single period (T) of the sampling clock pulse or by a simple integer multiple thereof. The filter (50) further contains a programmable control device (52), which switches over or switches off a part of the data inputs (16, 17) of the basic unit (10) to achieve forward and/or backward filtering and/or sign inversion and/or a change of the active filter length.

Abstract: An efficient, multichannel filter for CDMA modems permits multiple serial, digital bit streams to be filtered by digital signal processing techniques including sample weighting and summing functions. Each individual channel may have custom weighting coefficients or weighting coefficients common for all channels. If the weighting coefficients are by adaption, the same approach may be taken. The multichannel FIR filter is implemented with no multipliers and a reduction in the number of adders. To increase the speed of operation, the filter structure utilizes look-up tables storing the weighting coefficients. The invention can be embodied as either as a field programmable gate array or an application specific integrated circuit. The use of look-up tables saves significant chip resources.

Abstract: A system is provided for processing digital data from an array of receiver elements. The system includes an input assembly interface and a processing element. The input assembly interface is capable of providing the digital data from the array of receiver elements. The processing element, in turn, is capable of providing an impulse response, and representing the digital data and impulse response vectorized receiver matrices and vectorized response matrices, respectively. The processing element can then signal condition the digital data, without corner turning, based upon the vectorized receiver matrices and the vectorized response matrices. Once the signal conditioning output has been computed, the digital data may be further processed by a beamformer and matched filter.

Abstract: A method and apparatus is disclosed for performing blind source separation using convolutive signal decorrelation. For a first embodiment, the method accumulates a length of input signal (mixed signal) that includes a plurality of independent signals from independent signal sources. The invention then divides the length of input signal into a plurality of T-length periods (windows) and performs a discrete Fourier transform (DFT) on the, signal within each T-length period. Thereafter, estimated cross-correlation values are computed using a plurality of the averaged DFT values. A total number of K cross-correlation values are computed, where each of the K values is averaged over N of the T-length periods. Using the cross-correlation values, a gradient descent process computes the coefficients of a finite impulse response (FIR) filter that will effectively separate the source signals within the input signal. A second embodiment of the invention is directed to on-line processing of the input signal—i.e.

Abstract: This invention provides a digital filter which permits input data to be little canceled. Based on an input signal, a coefficient is calculated through delay units 10, 11, coefficient multiplier units 20, 21, 22, adder units 30, 31, 32 and an offset constant unit 40, and the thus obtained coefficient is multiplied by the input signal through coefficient multiplier unit 23.

Abstract: Data other than inserted “0”s are selected by first selectors from among a plurality of data included in input data to which zero value interpolation is carried out at an interpolation circuit. Besides, coefficients by which the data selected by the first selectors should be multiplied are selected by second selectors. The data selected by the first selectors are multiplied by the coefficients selected by second selectors in multiplication circuits. Then, an adding circuit adds all of the multiplied results and outputs the added result as the desired filter characteristic.

Abstract: Implementations of a two-dimensional pyramid filter are disclosed including a two-dimensional pyramid filter architecture of an order 2N?1, where N is a positive integer greater than three. The two-dimensional pyramid filter architecture of order 2N?1 may include one-dimensional pyramid filters of order 2N?1, a first summer circuit; and a second summer circuit. The two dimensional pyramid filter architecture of order 2N?1 may produce, in operation on respective clock cycles, at least a pyramid filtered output signal corresponding to the summation by the first summer circuit of output signals produced by four one-dimensional pyramid filters of order 2N?1, and a pyramid filtered output signal corresponding to an output signal produced by summing signal sample matrices of order [2(N?1)?1] in the second summer circuit. The respective pyramid filtered output signals of the two dimensional pyramid filter architecture may be summed by the third summer circuit on respective clock cycles.

Abstract: Parallel adaptive filters and filtering methods that enable processing of an input signal in a circuit that has an clock speed many times slower than the input rate of the input signal that is processed. A polyphase decimator structure processes a data stream requiring a low pass filtered bandlimited (low-rate) output that is used for high-rate output structures. The filters and methods break an input data stream into parallel paths that efficiently produce a bandlimited (decimated, low-rate) filtered output. Each of the parallel paths is processed at a decimated rate to provide a filtered output signals corresponding to a filtered version of the input signal.

Abstract: A method of reducing the amount of computer memory utilized in calculating a formula on a collection of a plurality of series of data values, the method including the steps of: (a) for each data value member of at least one series of the collection, determining the size of a window of data values required to calculate the formula; (b) obtaining the size of the window required for the at least one series on the basis of the determination, and (c) utilizing the window having the predetermined size to determine data values to be stored in computer memory when calculating the formula when applied to other series of data values in the collection.

Abstract: A novel Finite Impulse Response (“FIR”) filter (100) is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (104). At least two slave sample and hold circuits (114, 118) connect to the master output. The slave sample and hold circuits (114, 118) operate at 1/k times the clock rate of the master sample and hold circuit (104), where k equals the number of slave sample and hold circuits (114, 118). A first multiplexer (126) multiplexes the slave outputs together. At least one tap block (129, 179, 207) is coupled to the first multiplexer (126) includes a multiplier (132, 180, 210), a summer (142, 142, 216), at least two slave sample and hold circuits (152, 154, 188, 190, 224, 226) and a second multiplexer (164, 200, 236). The slave sample and hold circuits (152, 154, 188, 190, 224, 226) run at 1/k times the clock speed of the master sample and hold circuit (126).

Abstract: A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Abstract: A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.

Abstract: An area-efficient finite impulse response filter having permuted bit-order functional elements that provide substantially straight and direct interconnects with minimized length between adjacent elements. A functional element is coupled with an input data path and an output data path, at least one of which has a permuted bit-order data path exhibiting bit-order ordinal discontinuity. The permuted bit-order data path also can be a transposed permuted bit-order data path in which the placement of at least part of a data path is transposed, relative to prior art placements. The bit-order ordinal discontinuity fosters short, straight element interconnects which leads to increased spatial efficiency and improved performance.

Abstract: Multiported register files used for storing coefficients in adaptive FIR are improved upon by implementing a split memory architecture that has the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called “burst mode” updating, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample.

Abstract: The motivation for this invention evolved from a realization that a critical component was excluded from the information flow through a conventional digital filter, whether static or adaptive. Inputs can typically include the current input sample, previous samples, a priori knowledge Response and reference data. But the A/D sampler is not directly incorporated into the actual filter. Thus, standard filter design typically begins with a vector of uniformly sampled input data Fundamentally, non-uniform sampling of volatile signal can glean more information about a signal than uniform sampling at the Nyquist rate (if indeed that rate is known a-priori). Additional information might be gleaned from simultaneous pseudo-random non-uniform sampling, along with trend or volatility non-uniform sampling. In contrast to judicious non-uniform sampling, uniform sampling can be sub-optimal in extracting information per unit of effort expended.

Abstract: A digital data system (100) provides 1-D, 2-D and 3-D capability and multi-band channel capability. Improved filter banks are created by generating a filter bank having an analysis portion and synthesis portion and obtaining wavelet coefficients (302) for each portion. The wavelet coefficients are expressed in a format capable of canonical signed digit (CSD) representation, such as integers (302). The canonical signed digit (CSD) representation is controlled by a value, N, selected to control resolution of the CSD coding. Optimized CSD-coded wavelet coefficients are used as filters for data signals (318).

Abstract: An increasing nonlinear-filter represented as a plurality of basis elements along with the filter values at those basis elements by finding, for each output value k of the filter, all possible observations X that result in an output value k or greater. The set of all values that map to an output value k or greater have at least one minimal element at these are known in the art as basis elements. These basis elements are arranged in a list, numbered 1 through M. Constructing a table in which basis element number corresponds to the filter output value at that basis element. Thereafter, each of the N samples (X1, . . . , XN) is inspected in turn. For each sample X1, testing each of its possible values with its respective interval components wherein, if the M basis elements are A1, . . . , AM and if basis element number j is being inspected, then each value of X1 is tested against Aij. For each value of X1=t1, . . .

Abstract: A signal-processing apparatus has a digital filter for processing input data from a knock-sensor. The digital filter is designed as an FIR filter characterized by filter coefficients that are equal to values of mince points 0 to 16 obtained based on a reference waveform. The reference waveform is created by concatenating half waves of a first sinusoidal waveform with half waves of a second sinusoidal waveform with peak values equal to half the peak value of the first sinusoidal waveform. The values of mince points 4, 8 and 12 are 0. Each value of mince points 1, 3, 13 and 15 is equal to corresponding value of mince points 5, 7, 9 and 11. The digital filter effectively reduces a filter-processing load.

Abstract: A decimation filter includes a first circuit block for respectively delaying by one clock an input signal synchronized with a clock signal and for producing a plurality of delayed signals, adders for adding or merging by confluence buffers the delayed signals to obtain total signals and for feeding the total signals to one signal line, and a second circuit block for counting pulses of the total signals. The filter provides an analog-to-digital converter which processes signals at a high speed and which is resistive against overflow.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: A digital FIR filter is provided that inputs a series of data samples x[0] . . . x[n] and generates a partial sum output PS[i], where i≦n. The partial sum output is a weighted version of the a difference between a partial sum of the previous i−1 data samples, PS[i−1], and the current data sample x[n] added to the current data sample x[n]. The filter includes a plurality of weighting stages. Each weighting stage includes a first adder for subtracting the current data sample x[n] from the previous partial sum PS[i−1], a multiplier that multiplies the difference by a weighting coefficient, and a second adder that sums the weighted difference with the current data sample. The filter also includes a plurality of delay elements, each of which inputs a partial sum and imposes a unit delay on the partial sum before supplying it to a weighting stage.

Abstract: A method and apparatus for compression/decompression and filtering of a signal in which the apparatus has an input register (704) which receives the received signal, an output register (712) which transmits a processed signal and a distributed arithmetic processor (708) having a plurality of operational modes. The distributed arithmetic processor is coupled to the input register by an input path and is coupled to the output register by an output path. The apparatus also has a DCT butterfly processor (706) selectively switched into the input path in response to selection of a predetermined operational mode from the plurality of operational modes. An IDCT butterfly processor (710) is also selectively switched into the output path in response to the selection of one of the predetermined operational modes. Additionally, the apparatus selectively functions as a FIR filter with both the DCT butterfly processor (706) and IDCT butterfly processor (710) removed from the input and output paths.

Abstract: A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder.

Abstract: An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, 60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (yn−1, yn−2), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (xn) and signal output (yn). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

Abstract: There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

Abstract: A delayed adaptive least-mean-square (LMS) filter, which has one filter coefficient per tap and acquires a new data sample each frame, calculates a finite impulse response (FIR) filter output and updates the filter coefficients using an error term based on the FIR filter output calculated during the preceding frame. The calculations for each tap are performed in a single clock cycle. The filter can be implemented using a general purpose, programmable digital signal processor (DSP) architecture having two multiply and accumulate circuits (MACs), with or without an arithmetic logic unit (ALU), and preferably implements its memory buffers as dual-access or dual-port RAM or banked memory.

Abstract: Embodiments of a multiplierless pyramid filter are described.

Abstract: A system and a method for implementing a feedback control signal by employing parallel paths (105 and 106) for processing separate parts of the signal. The method effectively doubles operating speed of the feedback circuit by providing two processing paths (101 and 102). Where two paths are used, each operates at approximately one-half of the data rate of the incoming data signal (516). The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (513) of a disk drive (500), three modes are desired: FIR-bypass (201), acquisition (202), and data-tracking (203). Being able to switch easily among the three modes of the system (200) provided for in a read channel of a disk drive (500) demonstrates the adaptability of the method and supporting structure to a broad class of feedback circuits used in systems employing high throughput rates.

Abstract: A filter is implemented in software on a general purpose processor in a manner which reduces the number of memory accesses as compared to conventional methods. In some realizations, both application code and filter code are executed on a same general purpose processor. The filter code incrementally loads respective portions of input and coefficient vector data from addressable storage into respective registers of the processor and performs successive operations thereupon to accumulate output vector data into other respective registers of the processor. The filter code typically exhibits an execution ratio of less than two input and coefficient data loads per operation to accumulate. In some realizations, the filter code is callable from the application code and provides the application code with a signal processing facility without use of a digital signal processor (DSP).

Abstract: Systems and methods for determining coefficients of an FIR filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to &pgr;. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.

Abstract: A digital filter includes a plurality of filter cells, each of which includes circuitry to determine a coefficient for the filter cell, to adjust the coefficient in accordance with a gain that is used by each of the plurality of filter cells, and to multiply input data by the adjusted coefficient in order to generate a filter cell output. An adder circuit generates a filter output by adding filter cell outputs from each of the plurality of filter cells, and an inverse gain circuit adjusts the filter output in accordance with an inverse of the gain used to adjust the coefficients of the plurality of filter cells.

Abstract: A filter, in particular, a finite impulse response (FIR) filter having a variable data input and output rate is disclosed. The FIR filter includes a first-in first-out (FIFO) architectural buffer, an address generator for circularly generating respective addresses for FIFO of data items and providing the addresses to the buffer, a filter for performing filtering on data items having different rates, which are input from the buffer, and outputting one or more data, and a controller for controlling address generation of the address generator and controlling transfer paths of data items for filtering of the filter. It is possible to variably control the input and output rate of filtering data by the FIR filter.

Abstract: This invention describes a novel method and system that implements wavelet packet trees and inverse wavelet packet trees. A modified Recursive Pyramid Algorithm (RPA) is advanced by this invention. The algorithm uses a filter that changes its size at each given octave of the wavelet packet tree. This filter may also be used in the reconstruction, synthesis, or inverse wavelet packet tree using RPA. The invention reduces the cost of implementing wavelet packet trees by using the same hardware for each octave and thereby offers superior products at attractive prices.

Abstract: A method for implementing a low power and high-speed digital filter having reduced number of adders is disclosed. The method comprises the steps of determining vertical common CSD (Canonical Signed Digit) code words between corresponding CSD code words of adjacent filter coefficients, wherein a vertical common CSD code word in a highest level bit is set as a vertical common subexpression, expressing the vertical common CSD code words out of the CSD code words of each filter coefficient with the vertical common subexpression by shifting and delaying the vertical common subexpression, and synthesizing the expressed vertical common CSD code words of the filter coefficients.

Abstract: A convolution method and apparatus of time domain convolving an input signal with a second signal is disclosed comprising the steps of; dividing the second signal into a series of segments; determining a magnitude envelope for each of the segments; scaling the signal values within each segments relative to the envelope to produce corresponding segment scaled signal values; multiplying the segment scaled values by a corresponding input signal value to produce corresponding segment output values; scaling the segment output values by a segment scale factor to produce corresponding scaled segment outputs; and adding the scaled segment output to produce a time domain output.

Abstract: An analog FIR filter that processes multiple output samples in parallel is disclosed. The simultaneous parallel processing of multiple samples permits improved sampling rate and improved accuracy as compared to prior art filters.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A digital filter realization is proposed that consists of only one multiplier, i. e. which operates with a higher clock rate and changes coefficient at the multiplier each clock cycle, but in which the clock rate of the multiplier is reduced in comparison to prior art filters by considering equal filter coefficients, e. g. based on the symmetry of FIR filter coefficients. According to the present invention preferably the samples belonging to equal filter coefficients are added in advance in order to reduce the number of multiplications, which concludes in a reduced clock rate for the filter, a reduced needed calculation power, and therefore a reduced power consumption.

Abstract: A filter for filtering n data trains by time division multiplexing includes data channels for receiving data train values, registers subdivided into n groups for buffer storage of the data train values or derived values, and adders each having inputs. Each of the n groups is connected to one of the data channels. The adders and the registers alternatively connect to form a chain. The first input of respective adders connected upstream of a respective register of an ith group (0≦i≦n−1) has a connection to respective data channels assigned to the ith group, and the second input is connected to a respective register of a group having a number (i−1)mod n without an intervening register of another group. The filter is used to parallelly decimate data trains by a common factor. A filter configuration includes the filter and two multipliers. A method is also provided.

Abstract: An analog discrete-time filter that processes multiple output samples in parallel is disclosed. The simultaneous parallel processing of multiple samples permits improved sampling rate and improved accuracy as compared to prior art filters.

Abstract: An amplitude detecting circuit (1) includes a simple digital filter (2) having a structure corresponding to a part where the energy is concentrated in the full impulse response of a signal processing digital filter (3). Concretely, for example, the amplitude detecting circuit (1) (simple digital filter (2)) includes only four central taps having coefficients of large absolute values and considerably affecting on the output amplitude among sixteen taps of the signal processing digital filter (3). By the amplitude detecting circuit (1), the amplitude of an output signal of the signal processing digital filter (3) can approximately be detected.

Abstract: A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f+n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n≧k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f+n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame.

Abstract: A digital filter is provided with a plurality of selectors. Switchover from one selector to another switches the digital filter operation between a separation filter function and a synthesis filter function. When the digital filter functions as either separation filter or synthesis filter, it switches over between the functions of multiplying data by a filter coefficient and multiplying data by an attenuation coefficient. The entire digital filter circuit size can thus be reduced.

Abstract: A circuit arrangement and method utilize a programmable shifter coupled downstream of a multiplier to shift the product of an input value and a pre-scaled filter coefficient that implements a predetermined filter function. Through the judicious selection of an appropriate pre-scaled filter coefficient and a shift distance to shift the product, truncation errors associated with a digital implementation of a filter may be minimized, offering improved filter response compared to other discrete filter implementations with like coefficient resolution, or in the alternative, permitting acceptable filter response to be maintained with reduced coefficient resolution. Moreover, where the coefficient resolution is reduced, a filter may be implemented using relatively less space, less power consumption and less delay than in comparable conventional designs.

Abstract: Embodiments of a two-dimensional pyramid filter architecture are described.