Galois Field Patents (Class 708/492)
  • Patent number: 11012089
    Abstract: A system and method to encrypt a block of data is disclosed. A block of original data is retrieved from a data store, block of original data including a N number of words, each word including one or more bits of data. A multiplier matrix is provided, the multiplier matrix having N×N words, a plurality of sub matrices arranged diagonally within the N×N matrix, with each of the sub matrix arranged as a binomial matrix. All the words in the multiplier matrix not part of the sub matrix are set to zero. The block of original data is multiplied with the multiplier matrix to generate a block of modified original data with N number of words.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 18, 2021
    Inventor: Geoffrey Arthur Boyd
  • Patent number: 11012094
    Abstract: A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are “m” mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: ATI Technologies ULC
    Inventor: Wing-Chi Chow
  • Patent number: 10990626
    Abstract: A data storage and retrieval system employs online supervised hashing for indexing a data set and retrieving data items therefrom. A hash-based mapping is used to generate hash codes for indexing content items. Data items may be retrieved based on either/both a query label (using corresponding codewords) and the content item itself (using the hash codes). The hash-based mapping is updated using an objective function of distance between the hash codes and respective codewords for labels of labelled content items, preserving semantic similarities of content items. The codewords may be error-correcting codes. Techniques for efficiently updating the index include (1) cycle-based updating and ternary codewords, and (2) reservoir sample-based method of determining when to trigger an update.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 27, 2021
    Assignee: Trustees of Boston University
    Inventors: Stanley Sclaroff, Fatih Cakir, Kun He
  • Patent number: 10877753
    Abstract: A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jonathan D. Bradbury
  • Patent number: 10797858
    Abstract: Modifications to Advanced Encryption Standard (AES) hardware acceleration circuitry are described to allow hardware acceleration of the key operations of any non-AES block cipher, such as SMT and Camellia. In some embodiments the GF(28) inverse computation circuit in the AES S-box is used to compute X?1 (where X is the input plaintext or ciphertext byte), and hardware support is added to compute parallel GF(28) matrix multiplications. The embodiments described herein have minimal hardware overhead while achieving greater speed than software implementations.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Vikram B Suresh, Sanu K. Mathew, Sudhir K Satpathy, Vinodh Gopal
  • Patent number: 10630426
    Abstract: Implementations described herein utilize redundancy information for packet data portions. For instance, a first packet includes multiple data portions. A second packet is generated that includes redundancy information for one or more of the multiple data portions of the first packet. In at least some implementations, the redundancy information can be used to determine whether an error condition occurs related to the first packet, such as data errors and/or a dropped data portion.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: April 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Lionel Koenig
  • Patent number: 10581593
    Abstract: Systems, methods, and computer-readable media are disclosed for performing message padding of input messages in a manner that preserves the integrity of the input data regardless of whether the input message is in a bit-oriented format or a bit-reversed format. Each byte of a partial input message block of an input message may be converted from a bit-reversed format to a bit-oriented format prior to performing message padding in order to ensure that input data bits are not lost during the message padding. Subsequent to the message padding that generates one or more padded message blocks, the padded message block(s) may be converted from a bit-oriented format to a bit-reversed format to enable further processing of the input message to be performed to obtain a message digest.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Louis P. Gomes
  • Patent number: 10530523
    Abstract: Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Patrick J. Meaney, Gary Van Huben
  • Patent number: 10521296
    Abstract: A data block may be identified. A first decoding operation may be performed on the data block. An unsuccessful correction of an error of the data block associated with the first decoding operation may be determined. A set of bits of the data block that caused the unsuccessful correction of the error of the data block may be identified. In response to identifying the set of bits of the data block that is associated with the unsuccessful correction of the error, a second decoding operation on the set of bits of the data block may be performed. The second decoding operation may be different than the first decoding operation.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 31, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yingquan Wu, Eyal En Gad
  • Patent number: 10515567
    Abstract: N-state switching tables are transformed by a Lab-transform into a Lab-transformed n-state switching table. Memory devices, processors and combinational circuits with inputs and an output are characterized by the Lab-transformed n-state switching table and perform switching operations between physical states in accordance with a Lab-transformed n-state switching table. The devices characterized by Lab-transformed n-state switching tables are applied in cryptographic devices. The cryptographic devices perform standard cryptographic operations that are modified in accordance with a Lab-transform.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 10496373
    Abstract: In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Vikram B. Suresh, Sanu K. Mathew, Sudhir K. Satpathy, Vinodh Gopal
  • Patent number: 10404278
    Abstract: CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive that bit of the M-bit data frame and a different bit of a N-bit CRC value from the lookup-table corresponding to a position of the bit in the M-bit data frame. N exclusive-OR gates each receive output from one of the N AND gates for each bit of the M-bit data frame. The N exclusive-OR gates generate a final N-bit CRC value for the M-bit data frame. The CRC value is therefore generated with a purely combinational circuit, without clock cycle latency. Area consumption is small due to the small lookup-table, which itself permits use of any generator polynomial, and is independent of the width of the received data frame. This device can also generate a combined CRC for multiple frames.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Rakesh Malik
  • Patent number: 10120837
    Abstract: To reduce the processing amount of a field multiplication. A matrix application apparatus computes a vector b by multiplying a vector a and a matrix A, provided that a denotes a k-th order vector having elements a0, . . . , ak?1 (a0, . . . , ak?1?GF(xq)), b denotes an m-th order vector having elements b0, . . . , bm?1 (b0, . . . , bm?1?GF(xq)), and A denotes a m-by-k Vandennonde matrix. A polynomial multiplication part computes a value bi. An order reduction part designates gi?hif? as the value bi by using a polynomial hi obtained by dividing a part of the value bi having an order equal to or higher than q by Xq and a polynomial gi formed by a part of the value bi having an order lower than q.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 6, 2018
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventor: Dai Ikarashi
  • Patent number: 9990179
    Abstract: Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, David Raymond Lutz
  • Patent number: 9935653
    Abstract: Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Sivakumar Radhakrishnan, Sin S. Tan, Kenneth C. Haren, Mark A. Schmisseur
  • Patent number: 9928037
    Abstract: Hardware logic arranged to perform modulo calculation with respect to a constant value b is described. The modulo calculation is based on a finite polynomial ring with polynomial coefficients in GF(2). This ring is generated using a generator polynomial which has a repeat period (or cycle length) which is a multiple of b. The hardware logic comprises an encoding block which maps an input number into a plurality of encoded values within the ring and a decoding block which maps an output number back from the ring into binary. A multiplication block which comprises a tree of multipliers (e.g. a binary tree) takes the encoded values and multiplies groups (e.g. pairs) of them together within the ring to generate intermediate values. Groups (e.g. pairs) of these intermediate values are then iteratively multiplied together within the ring until there is only one intermediate value generated which is the output number.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 27, 2018
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 9923580
    Abstract: The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kijun Lee, Myungkyu Lee, Sejin Lim, Junjin Kong
  • Patent number: 9906359
    Abstract: Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventor: Shay Gueron
  • Patent number: 9906240
    Abstract: A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yi-Min Lin, Aman Bhatia, Naveen Kumar, Chung-Li Wang, Lingqi Zeng
  • Patent number: 9900147
    Abstract: The techniques and/or systems described herein are directed to improvements in homomorphic operations within a homomorphic encryption scheme. The homomorphic operations may be performed on encrypted data received from a client device without decrypting the data at a remote computing device, thereby maintaining the confidentiality of the data. In addition to the operations of addition, subtraction, and multiplication, the homomorphic operations may include an approximate division, a sign testing, a comparison testing, and an equality testing. By combining these operations, a user may perform optimized operations with improved processor and memory requirements.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kim Laine, Nathan P. Dowlin, Ran Gilad-Bachrach, Michael Naehrig, John Wernsing, Kristin E. Lauter
  • Patent number: 9875377
    Abstract: A device of the Substitution-Box (S-Box) type, which is suitable for operating in a symmetric-key encryption apparatus, in particular an AES (Advanced Encryption Standard) encryption apparatus, and includes at least one module configured for carrying out a non-linear operation in a finite field (GF(28)) of an encryption method implemented by the above encryption apparatus, the module including at least one reprogrammable look-up table to, for example, implement countermeasures against side-channel attacks. When no countermeasures are employed, the tables may be set to fixed values, instead of being reprogrammable. The above module includes a plurality of composite look-up tables that implement the non-linear operation in a composite field of finite subfields (GF(24)2; GF((22)2)2) deriving from the finite field (GF(28)), each of the above composite look-up tables being smaller than a look-up table that is able to implement autonomously the non-linear operation in a finite field (GF(28)).
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: January 23, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Filippo Melzani
  • Patent number: 9841950
    Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ki Lee, Jonghoon Shin, KyoungMoon Ahn, Ji-Su Kang, Sun-Soo Shin
  • Patent number: 9811318
    Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jonghoon Shin, Sun-Soo Shin, Kyoungmoon Ahn, Yong Ki Lee
  • Patent number: 9804828
    Abstract: A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm?1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p?1 is output as at least one root of the first element.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: October 31, 2017
    Assignee: APPLE INC.
    Inventors: Micha Anholt, Moti Teitel
  • Patent number: 9804840
    Abstract: A Vector Galois Field Multiply Sum and Accumulate instruction. Each element of a second operand of the instruction is multiplied in a Galois field with the corresponding element of the third operand to provide one or more products. The one or more products are exclusively ORed with each other and exclusively ORed with a corresponding element of a fourth operand of the instruction. The results are placed in a selected operand.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: October 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jonathan D. Bradbury
  • Patent number: 9619207
    Abstract: Galois-field reduction circuitry for reducing a Galois-field expansion value using an irreducible polynomial includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective expansion bit position. Gates select ones of said the plurality of memories corresponding to ones of the respective expansion bit positions that contain ‘1’, and an exclusive-OR gate combines outputs of the gates that select. A specialized processing block includes a multiplier stage, and an input stage upstream of the multiplier stage, with such Galois-field reduction circuitry in the input stage with its output selectably connectable to the multiplier stage and selectably connectable to an output of the specialized processing block. A programmable integrated circuit device includes a plurality of such specialized processing blocks, and additional multiplier and additional exclusive OR gates for concatenating a plurality of specialized processing blocks.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: April 11, 2017
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 9569771
    Abstract: A method and system for storage and retrieval of blockchains with Galois Fields. One or more blocks for a blockchain are securely stored and retrieved with a modified Galois Fields on a cloud or peer-to-peer (P2P) communications network. The modified Galois Field provides at least additional layers for security and privacy for blockchains. The blocks and blockchains are securely stored and retrieved for cryptocurrency transactions including, but not limited to, BITCOIN transactions and other cryptocurrency transactions.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 14, 2017
    Inventors: Stephen Lesavich, Zachary C. Lesavich
  • Patent number: 9473296
    Abstract: A processor includes an input-circuit and a Simon block cipher. The Simon block cipher includes a data transformation circuit, a constant generator, and a key expansion circuit. The data transformation circuit includes logic to shift content of data storage registers. The key expansion circuit includes logic to determine a round key based upon an input symmetric key and data input, a previous round key, and a value from the constant generator. The constant generator includes logic to output a successive one of a list of constants each clock cycle, and to store the outputted constants in storage units. The number of storage units is less than the size of the list of constants.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Himanshu Kaul, Mark A. Anders
  • Patent number: 9459832
    Abstract: A pipelined multiply-scan circuit that may be used for high-performance computing. The pipelined multiply-scan circuit may comprise dedicated hardware configured to execute one or more sub-calculations associated with a pipelined multiply-scan process utilizing one or more serially-connected left-shift modules, and one or more serially-connected adder.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 4, 2016
    Assignee: Bank of America Corporation
    Inventor: Steven A. Guccione
  • Patent number: 9459958
    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: October 4, 2016
    Inventors: Ron Diamant, Nafea Bshara, Yaniv Shapira, Guy Nakibly
  • Patent number: 9448768
    Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Ki Lee, Jonghoon Shin, KyoungMoon Ahn, Ji-Su Kang, Sun-Soo Shin
  • Patent number: 9413391
    Abstract: According to one embodiment, a chien search device includes n operation units configured to perform exclusive-OR operations, for each of the coefficients. Further, the chien search device includes first register configured to hold operation results of a highest order operation unit, for each of the coefficients. Furthermore, the chien search device includes exclusive-OR operation unit configured to perform exclusive-OR operations of the results of the first exclusive-OR operations of the highest order operation unit, for each of the coefficients. Moreover, the chien search device includes second register configured to hold operation results of the exclusive-OR operation unit, for each of the coefficients. The respective operation units reduce the number of stages of exclusive-OR operations by using the second register values.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kondo, Kenji Yoshida, Hidetoshi Tsuneda
  • Patent number: 9361479
    Abstract: A method and system for electronic content storage and retrieval using Galois Fields and geometric shapes on cloud computing networks. Plaintext electronic content is divided into plural portions and stored in plural cloud storage objects based on a created Xth dimensional geometric shape and a path through selected components of the geometric shape. Storage locations for the plural cloud storage objects are selected using a Galois field and the geometric shape. The plural cloud storage objects are distributed across the cloud network. When the electronic content is requested, the plural portions are retrieved and transparently combined back into the original electronic content.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 7, 2016
    Inventors: Stephen Lesavich, Zachary C. Lesavich
  • Patent number: 9317253
    Abstract: In one embodiment, a shift register is provided. The LFSR includes a plurality of processing stages coupled in series, each configured to implement N taps of the LFSR. N single-tap circuits are coupled together in series and arranged to implement the last N taps of the LFSR. Each coefficient(s) of a feedback polynomial of the LFSR is implemented by one of the taps of the plurality of processing stages or the N single-tap circuits. A feedback generation circuit is configured to provide, for each of the plurality of processing stages, a respective feedback signal as a function of polynomial coefficients implemented by the processing stage and output from one or more of the N single tap circuits.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: April 19, 2016
    Assignee: XILNIX, INC.
    Inventor: Robert E. Payne
  • Patent number: 9311052
    Abstract: In a method of performing a multiplication operation in a binary extension finite field, a polynomial defined by ? n = 0 W - 1 ? C n · z n is produced by expanding polynomial basis multiplication for multiplication of two polynomials a(z) and b(z) in a binary extension finite field. A mapping table is generated in which bit values having pieces of information about respective terms of the produced polynomial are mapped to respective rows. A code for calculating the polynomial, produced by expanding the polynomial basis multiplication for the multiplication of the two polynomials, with reference to the mapping table is generated.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 12, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dongsoo Kim, Junyoung Son, Sangwoon Yang
  • Patent number: 9280518
    Abstract: According to an embodiment, a computing device includes a receiving unit, a calculating unit, a solving unit, a selecting unit, and a determining unit. The receiving unit is configured to receive pieces of input data indicative of elements of a subgroup of a multiplicative group in a finite field and pieces of first additional data for identifying conjugates of the respective pieces of input data. The elements are represented by traces. The calculating unit is configured to calculate a coefficient of an equation based on the pieces of input data. The solving unit is configured to obtain solutions of the equation. The selecting unit is configured to select one of the solutions as a result of computation, based on the first additional data. The determining unit is configured to determine second additional data for identifying a conjugate of the selected result of computation based on the first additional data.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 8, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Yonemura, Hirofumi Muratani, Yoshikazu Hanatani
  • Patent number: 9262159
    Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank L. Berry, Mlchael E. Kounavis
  • Patent number: 9250862
    Abstract: Embodiments of an improved Galois multiplication route are described. In some embodiments, the Galois multiplication routine looks up and retrieves a first value corresponding to an address in the Galois table, exclusive ORs the retrieved value with a data value from a data set to generate an intermediate address for the Galois table, wherein the data value is at a location associated with an index, and looks up and retrieves a second value in the Galois table by the intermediate address.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 2, 2016
    Assignee: Echelon Corporation
    Inventor: Walter J. Downey
  • Patent number: 9201847
    Abstract: A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n) look-up table multiplier; the controller is connected respectively to the input port, the output port, the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier; the GF((2n)2) multiplier is connected respectively to the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier. By using the GF((2n)2) multiplier, the GF(2n) standard basis multiplier and the GF(2n) look-up table multiplier, the multiplication of three operands is realized. Compared with the existing multiplier, the multiplier of the present invention has significant advantages in the speed of multiplying three operands over GF((2n)m).
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 1, 2015
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Shaohua Tang, Haibo Yi
  • Patent number: 9195607
    Abstract: A memory interface device comprising an address match table. The address match table includes a content entry input and a plurality of hash functions numbered from 1 through N, where N is an integer greater than 1. The address match table includes a first table comprising a plurality of lists numbered from 1 through N, each hash function (i) corresponds to a list (i), where (i) is a number in a set from 1 through N, and a second table coupled to the first table, the second table comprising a plurality of entries, each of the entries point to a different entry within the second table or a null entry in the second table. The interface device includes an index from list N in the first table points to the second table.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 24, 2015
    Assignee: Inphi Corporation
    Inventors: Nirmal Saxena, Javier Villagomez
  • Patent number: 9164924
    Abstract: Security of information—both code and data—stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache. Memory writes from the CPU are encrypted by the agent before writing and reads into the CPU are decrypted by the agent before they reach the CPU. The cache-resident agent also optionally validates the encrypted information stored in the system memory. Support for I/O devices and cache protection from unsafe DMA of the cache by devices is also provided.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 20, 2015
    Assignee: FACEBOOK, INC.
    Inventors: Oded Horovitz, Stephen A. Weis, Carl A. Waldspurger, Sahil Rihan
  • Patent number: 9146708
    Abstract: A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: September 29, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Mayan Moudgill
  • Patent number: 9137250
    Abstract: A method and system for electronic content storage and retrieval using Galois Fields and information entropy on cloud computing networks. Electronic content is divided into plural portions and stored in plural cloud storage objects based on determined information entropy of the electronic content thereby reducing location guessing of the electronic content using information gain and mutual information. Storage locations for the plural cloud storage objects are selected using a Galois field. The plural cloud storage objects are distributed across the cloud network. The Galois filed and information entropy providing various levels of security and privacy for the electronic content.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 15, 2015
    Inventors: Stephen Lesavich, Zachary C. Lesavich
  • Patent number: 9128806
    Abstract: Methods and systems for squaring a binary finite field element are described. In some aspects, a data processing apparatus includes registers and processor logic. A first register stores a sequence of binary values that define a binary finite field element input. The processor logic accesses input components from the first register according to intervals in the sequence. Each input component includes a binary value from each interval in the sequence. In some cases, the intervals are periodic and the binary finite field element corresponds to a sum of phase-shifted input components. The processor logic generates output components based on the input components. The processor logic generates a square of the binary finite field element in the second register based on the output components. The number of input components can be selected, for example, to balance costs of additional processing time against benefits associated with reduced processing hardware.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 8, 2015
    Assignee: Certicom Corp.
    Inventor: Robert John Lambert
  • Patent number: 9077536
    Abstract: A method and apparatus for computing a discrete logarithm using a pre-computation table are provided. The method includes previously generating the pre-computation table consisting of chains of function values obtained by applying an iterating function to a predetermined number of initial values having a generator of the cyclic group as a base and having different exponents; and if a function value obtained by applying the iterating function to a value having a target element as a base and having an exponent is identical to a function value stored in the pre-computation table, computing the discrete logarithm of the target element by using exponent information of the two function values.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 7, 2015
    Assignees: SAMSUNG SDS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Jung Hee Cheon, Hyung Tae Lee, Jin Hong
  • Patent number: 9065632
    Abstract: A method for authenticating a message by a wireless device is described. The wireless device obtains the input message. The wireless device generates a keystream. The wireless device computes a message authentication code using the keystream and a universal hash function. The universal hash function is computed using carryless multiplication.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: June 23, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Billy B. Brumley, Alexander W. Dent
  • Publication number: 20150067011
    Abstract: A finite field inverter is disclosed, wherein the finite field inverter includes an input port, an output port and a search tree inverse circuit configured to perform an inverse operation of the operand ?(x) in the finite field GF (2n) based on a search tree structure. The search tree inverse circuit is provided with a left search tree and a right search tree. The left search tree and the right search tree each includes tree nodes for processing inverse operations over the finite field GF (2n) and connecting wires connected between the tree nodes. The tree nodes include a root node, internal nodes and leaf nodes. Each path from the root node to a leaf node represents an element in the finite field GF (2n). The connecting wires between the tree nodes connect the path representing the operand ?(x) with the path representing the inversion result b(x) .
    Type: Application
    Filed: December 5, 2012
    Publication date: March 5, 2015
    Applicant: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Shaohua Tang, Haibo Yi
  • Patent number: 8958555
    Abstract: In one exemplary embodiment of the invention, a method for computing a resultant and a free term of a scaled inverse of a first polynomial v(x) modulo a second polynomial fn(x), including: receiving the first polynomial v(x) modulo the second polynomial fn(x), where the second polynomial is of a form fn(x)=xn±1, where n=2k and k is an integer greater than 0; computing lowest two coefficients of a third polynomial g(z) that is a function of the first polynomial and the second polynomial, where g(z)?i=0n?1(v(?i)?z), where ?0, ?1, . . . , ?n?1 are roots of the second polynomial fn(x) over a field; outputting the lowest coefficient of g(z) as the resultant; and outputting the second lowest coefficient of g(z) divided by n as the free term of the scaled inverse of the first polynomial v(x) modulo the second polynomial fn(x).
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Craig B. Gentry, Shai Halevi
  • Patent number: 8949697
    Abstract: Systems, methods, apparatus, and techniques are provided for decoding a codeword. A plurality of syndrome values is received corresponding to a received codeword and a value of an error locator polynomial corresponding to the received codeword is initialized. The value of the error locator polynomial is iteratively updated by processing the plurality of syndrome values, where each iterative update includes determining a current degree of the error locator polynomial and terminating the iterative updating in response to a determination that the current degree of the error locator polynomial exceeds a threshold value.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 3, 2015
    Assignee: Marvell International Ltd.
    Inventor: Yuan-Mao Chang
  • Patent number: 8943118
    Abstract: A lookup table receives an n-bit input value and returns an output value that would be obtained by performance of a predetermined operation on the input value. The number of entries in the lookup table is less than 2n. An n-bit input data value is received, a modification condition is detected if any of a predetermined number of significant bits of the input data value are logic zeroes, and a shift operation is performed on the input data value if the modification condition is detected, prior to providing the input to the lookup table. If the modification condition is detected, an output value derivation operation is performed on the output value received from the lookup table to modify it prior to returning it to for processing. The derivation operation accounts for the shift operation. This approach can lead to a significant reduction in the lookup table size.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: January 27, 2015
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz