Abstract: Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions.

Abstract: Methods, apparatus and media for performing polynomial arithmetic operations over a Galois field having characteristic 2 and size 1 are disclosed. Such methods, apparatus and media include generating a binary representation of a polynomial over a Galois field having characteristic 2 and size 1, generating a plurality of right shifted binary representations of the first polynomial, and generating a binary representation of the polynomial reciprocal based upon a bitwise exclusive-OR of the binary representation of the polynomial and one or more right shifted binary representations selected from the plurality of right shifted binary representations.

Abstract: A method and a system for protecting a static digital datum contained in a first element of an electronic circuit, intended to be exploited by a second element of this circuit, in which: on the side of the first element, the static datum is converted into a dynamic data flow by at least one first linear shift feedback register representing a different polynomial according to the value of the static datum; the dynamic flow is transmitted to the second element; and on the side of the second element, the received dynamic flow is decoded by at least one second shift register representing at least one of the polynomials that has been used by the first element.

Abstract: A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of numerical data.

Abstract: An authentication method of a first module by a second module includes the steps of generating a first random datum by the second module to be sent to the first module, generating a first number by the first module starting from the first datum and by way of a private key, and generating a second number by the second module to be compared with the first number, so as to authenticate the first module. The step of generating the second number is performed starting from public parameters and is independent of the step of generating the first number.

Abstract: The invention is a method of calculating a key equation polynomial. The key equation comprises an errata locator polynomial and an errata evaluator polynomial. The errata locator polynomial decomposes to a plurality of coefficients. Some or all of the plurality of coefficients are formed by adding up decomposed data. The method comprises a coefficient calculation procedure for the errata locator polynomial of updating at least two coefficients, or two decomposed data of the coefficient calculation procedure, or a combination of the above in a single clock cycle simultaneously to get the errata locator polynomial.

Abstract: Methods and systems for squaring a binary finite field element are described. In some aspects, a data processing apparatus includes registers and processor logic. A first register stores a sequence of binary values that define a binary finite field element input. The processor logic accesses input components from the first register according to intervals in the sequence. Each input component includes a binary value from each interval in the sequence. In some cases, the intervals are periodic and the binary finite field element corresponds to a sum of phase-shifted input components. The processor logic generates output components based on the input components. The processor logic generates a square of the binary finite field element in the second register based on the output components. The number of input components can be selected, for example, to balance costs of additional processing time against benefits associated with reduced processing hardware.

Abstract: An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.

Abstract: Systems and methods efficiently process digests, hashes or other results by performing multiplicative functions in parallel with each other. In various embodiments, successive processing stages are provided, with each stage performing parallel multiplicative functions and also combining input terms to reduce the total number of terms that remain to be processed. By progressively combining the active terms into a smaller number of terms for subsequent processing, the time needed to process a result can be significantly reduced.

Abstract: A device for determining an inverse of an initial value related to a modulus, comprising a unit configured to process an iterative algorithm in a plurality of iterations, wherein an iteration includes two modular reductions and has, as an iteration loop result, values obtained by an iteration loop of an extended Euclidean algorithm.

Abstract: A computer hardware implemented cryptography method computes a modular exponentiation, M :=Cd (mod p·q), upon a message data value C using a Chinese Remainder Theorem (CRT) based technique. To secure against cryptanalysis, the private key moduli p and q are transformed by multiplication with a generated random value s, so that p?: =p·s and q? :=q·s, as shown in an exemplary embodiment in FIG. 2. The CRT steps of the modular exponentiation are applied using the transformed moduli p? and q? to obtain a random intermediate message data value M?. A final reduction of M? modulo p·q yields the final message data value M. Values needed for the computation are loaded into data storage and accessed as needed by electronic processing hardware.

Abstract: Disclosed are a semi-sequential Galois field GF(2n) multiplier and the method thereof. The GF(2n) multiplier comprises two ground field multipliers over GF(2m), at least a constant multiplier, and multiple GF(2m) adders. The high-order and low-order elements from a composite field GF((2m)2) for one operand of one GF(2n) multiplication are inputted in parallel into the two ground GF(2m) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2n) multiplication are sequentially inputted into the two ground GF(2m) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2m) adders. This generates a high-order element and a low-order element of the composite field GF((2m)2). After mapping these two elements of GF((2m)2) back to GF(2n), the GF(2n) multiplication is done.

Abstract: A connection information generating apparatus that generates connection information that indicates connections between a plurality of first transferring devices and a plurality of second transferring devices. The connection information generating apparatus includes a creating unit that creates an addition table and a multiplication table in a Galois field that has a characteristic of a value based on a number of the second transferring devices that are connected to each of the first transferring devices. The connection information generating apparatus includes a generating unit that generates connection information defining groups of first transferring devices to be connected to each of the second transferring devices, in accordance with the multiplication table and the addition table created by the creating unit.

Abstract: A unified integer/Galois-Field 2m multiplier performs multiply operations for public-key systems such as Rivert, Shamir, Aldeman (RSA), Diffie-Hellman key exchange (DH) and Elliptic Curve Cryptosystem (ECC). The multiply operations may be performed on prime fields and different composite binary fields in independent multipliers in an interleaved fashion.

Abstract: A multiplier circuit is disclosed including a Wallace tree block and a carry propagation adder. The Wallace tree block includes a sum calculation block adding partial products for each digit and a carry calculation block adding carries obtained in the addition by the sum calculation block. In the case of multiplication over an extension field (finite field GF(2n)) of two, a result of calculation by the sum calculation block is outputted. The carry propagation adder adds the result of calculation by the sum calculation block and a result of calculation by the carry calculation block. In the case of multiplication for integers (finite field GF(p)), a result of calculation by the carry propagation adder is outputted.

Abstract: The invention relates to a cryptographic method involving an integer division of type q=a div b and r=a mod b, wherein a is a number of m bits, b is a number of n bits, with n being less than or equal to m, and bn?1 being non-null and the most significant bit of b. In addition, each iteration of a loop subscripted by i, which varies between 1 and m?n+1, involves a partial division of a word A of n bits of number a by number b in order to obtain one bit of quotient q. According to the invention, the same operations are performed with each iteration, regardless of the value of the quotient bit obtained. In different embodiments of the invention, one of the following is also performed with each iteration: the addition and subtraction of number b to/from word A; the addition of number b or a complementary number /b of b to word A; or a complement operation at 2n of an updated datum (b or /b) or a dummy datum (c or /c) followed by the addition of the datum updated with word A.

Abstract: Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic device, includes a first logic for outputting a signed multiplicand by selectively performing a one's complementary operation on a multiplicand according to a Booth conversion result of a multiplier in modular multiplication; a second logic for outputting a modulus which is signed in the modular multiplication based on a carry input value Carry-in of a current clock, determined from a carry value cin for correction of a previous clock, and on a sign bit of the multiplicand; and a third logic for receiving the signed multiplicand and the signed modulus, and calculating a result value of the modular multiplication by iteratively performing a full addition operation on a carry value C and a sum value S of the full addition operation, found at the previous clock.

Abstract: Computing the Q and the P syndromes, which is needed in RAID 6 systems is effected through use of a single ROM lookup table for the necessary finite field multiplication. In one embodiment, the P and Q syndromes for data that normally arrives with 8-bit words are created by using Galois Field GF(24) arithmetic rather than the conventional GF(28) arithmetic, thereby very significantly reducing the requires size of the lookup table.

Abstract: Techniques for single function stage Galois field (GF) computations are described. Such a single function stage GF multiplication technique may utilize only m-bits per internal logic stage, a savings of m?1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach. Also, a common design GF multiplication cell is described that may be suitably used to construct an m-by-m GF multiplication array for the calculation of GF[2m]/g[x]. In addition, these techniques are further described in the context of packed data form computation, very long instruction word (VLIW) processing, and processing on multiple processing elements in parallel.

Abstract: The hash functions with elliptic polynomial hopping are based upon an elliptic polynomial discrete logarithm problem. Security using hash functions is dependent upon the implementation of a computationally hard problem, and the elliptic polynomial discrete logarithm problem provides enough relative difficulty in computation to ensure that the produced hash functions, as applied to message bit strings, are optimally secure. The hash functions are produced as functions of both the elliptic polynomial as well as the twist of the elliptic polynomial, particularly using a method of polynomial hopping.

Abstract: The hash functions using elliptic curve cryptography are hash functions that are produced using both an elliptic curve and a twist of the elliptic curve. Hash points are assigned values that either correspond to points on the elliptic curve or to points on the twist, depending upon whether the scalar value of the corresponding message block produces a quadratic residue or a quadratic non-residue when substituted as the x-value into the elliptic curve equation. The corresponding hash point x-coordinates are concatenated to form the hash bit string. The hash points may be doubled, and the hash functions may be applied to multimedia data by applying a media compression method to the message data before computing the hash points.

Abstract: Generating a remainder from a division of a first polynomial by a second polynomial having a variable width. One or more embodiments include a first sub-circuit, a first adder, a second sub-circuit, and a second adder. The first sub-circuit is adapted to generate a first partial remainder, which has a fixed width greater than or equal to the width of the second polynomial, from the first polynomial excepting a least significant portion. The first adder is adapted to generate a sum of the least significant portion of the first polynomial and a most significant portion of the first partial remainder. The second sub-circuit is adapted to generate a second partial remainder from the sum. The second adder is adapted to generate the remainder from the second partial remainder and the first partial remainder excepting the most significant portion.

Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.

Abstract: Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Abstract: The message authentication code with elliptic polynomial hopping provides methods for the generation of message authentication codes (MACs) utilizing elliptic curves, which are based on the elliptic curve discrete logarithm problem. The elliptic curve discrete logarithm problem is well known to be a computationally “difficult” or “hard” problem, thus providing enhanced security for the MACs. Different elliptic polynomials are used for different blocks of the same plaintext, each elliptic polynomial for each message block being selected at random using an initial secret key and a random number generator.

Abstract: The cryptographic hash functions using of elliptic polynomial polynomials are based on the elliptic polynomial discrete logarithm problem, which is well known as a computationally hard problem. The hash functions are based on the elliptic polynomial equation in their generation, where different elliptic polynomials are used for different blocks of the same plain text. Particularly, the hash functions use an elliptic polynomial with more than one independent x-coordinate. More specifically, a set of elliptic polynomial points are used that satisfy an elliptic polynomial equation with more than one independent x-coordinate which is defined over a finite field F.

Abstract: A method for generating an accelerated and/or decelerated chaotic sequence. The method involves selecting a plurality of polynomial equations constructed from an acc-dec variable v. The method also involves selecting a value for the acc-dec variable v for advancing or stepping back a chaotic sequence generation by at least one cycle at a given time. The method further involves using residue number system (RNS) arithmetic operations to respectively determine solutions for the polynomial equations using the acc-dec variable v. The solutions iteratively computed and expressed as RNS residue values. The method involves determining a series of digits in a weighted number system based on the RNS residue values.

Abstract: This invention describes a method for evaluating a polynomial in an extension field Fqm, wherein the method comprises the steps of partitioning the polynomial into a plurality of parts, each part is comprised of smaller polynomials using a q-th power operation in a field of characteristic q; and computing for each part components of qth powers from components of smaller powers. A further embodiment of the invention provides for a method of converting a field element represented in terms of a first basis to its representation in a second basis, comprising the steps of partitioning a polynomial, being a polynomial in the second basis, into a plurality of parts, wherein each part is comprised of smaller polynomials using a qth power operation in a field of characteristic q; evaluating the polynomial at a root thereof by computing for each part components of qth powers from components of smaller powers; and evaluating the field element at the root of the polynomial.

Abstract: A cryptographic system (CS) comprised of generators (502), (504), (510), an encryption device (ED), and a decryption device (DD). The generator (502) generates a data sequence (DS) including payload data. The generator (504) generates an encryption sequence (ES) including random numbers. The ED (506) is configured to perform a CGFC arithmetic process. As such, the ED is comprised of a mapping device (MD) and an encryptor. The MD is configured to map the DS and ES from Galois field GF[pk] to Galois extension field GF[pk+1]. The encryptor is configured to generate an encrypted data sequence (EDS) by combining the DS and ES utilizing a Galois field multiplication operation in Galois extension field GF[pk+1]. The generator (510) is configured to generate a decryption sequence (DS). The DD (508) is configured to generate a decrypted data sequence by performing an inverse of the CGFC arithmetic process utilizing the EDS and DS.

Abstract: The elliptic-polynomial based Message Authentication Code (MAC) provides MAC generation methods based on the elliptic polynomial discrete logarithm problem. It is well known that an elliptic polynomial discrete logarithm problem is a computationally “difficult” or “hard” problem. The methods use both an elliptic polynomial and its twist, even if the polynomial and its twist are not isomorphic. Since both the polynomial and its twist are used, multiple x- and y-coordinates can be used to embed bit strings into a point that satisfies the elliptic polynomial, and the embedding process is non-iterative, so that the time required to embed the bit string is independent of the bit string content.

Abstract: Described is an apparatus for performing a Galois field product computation on data. A first symbol data includes a plurality of symbols each being a bit sequence on which a product operation by a factor ? is to be performed in a Galois field, where ? is a primitive element of the Galois field, is acquired. A factor ? computation is performed on the first symbol data by performing a bit shift operation on the first symbol data toward high-order bit position, generating first mask data from the first symbol data, generating first correction data by computing a logical AND of the first mask data and a first symbol correction value, generating a factor ? computation result by computing a XOR of the second symbol data and the first correction data.

Abstract: A method of performing cell search includes receiving a primary synchronization signal (PSS) comprising a primary synchronization code (PSC), and receiving a secondary synchronization signal (SSS) comprising a first secondary synchronization code (SSC) and a second SSC. The first SSC and the second SSC are respectively scrambled by using a first scrambling code and a second scrambling code, and the first scrambling code and the second scrambling code are associated with the PSC. Detection performance on synchronization signals can be improved, and cell search can be performed more reliably.

Abstract: This invention describes a method for evaluating a polynomial in an extension field FqM, wherein the method comprises the steps of partitioning the polynomial into a plurality of parts, each part is comprised of smaller polynomials using a q?th power operation in a field of characteristic q; and computing for each part components of q?th powers from components of smaller powers. A further embodiment of the invention provides for a method of converting a field element represented in terms of a first basis to its representation in a second basis, comprising the steps of partitioning a polynomial, being a polynomial in the second basis, into a plurality of parts, wherein each part is comprised of smaller polynomials using a q?th power operation in a field of characteristic q; evaluating the polynomial at a root thereof by computing for each part components of q?th powers from components of smaller powers; and evaluating the field element at the root of the polynomial.

Abstract: The computing device calculates an equivalence H0?2m*k+1 (mod n) relating to a divisor n of 2m*k+1 (step A), computes an equivalence H?2E(p, m, k) (mod n) of 2E(p, m, k) (mod n) from H0 by an REDC operation (step B), and performs a correction operation by H=REDC (H, G)n for g=2k*G(p, m, k) when 2p>m×k (step C).

Abstract: Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.

Abstract: The disclosure provides a hardware architecture for encryption and decryption device. The hardware architecture can improve the encryption and decryption data rate by using parallel processing, and pipeline operation. Further, the hardware architecture can save footprint by sharing hardware components. Additionally, the hardware architecture can be associated with a memory to protect the information stored at the memory.

Abstract: A sequential Galois field (GF) multiplication architecture based on Mastrovito's multiplication and composite field has a two-tier architecture for performing GF(2k) multiplication. The tier one prepares related data of an operand A at one time, and proceeds another operand B by sequentially inputting m n-bit data, where k=m×n. The tier two sequentially receives the m inputted n-bit data, and directly performs GF((2n)m) multiplication with m n-bit multipliers. Before the data processing of the first architecture, operands A and B are transformed from a field GF(2k) into a composite field GF((2n)m) While a multiplication result from the tier two is transformed from the composite field GF((2n)m) back to the field GF(2k) for completing the GF(2k) multiplication.

Abstract: A modular multiplication method implemented in an electronic digital processing system takes advantage of the case where one of the operands W is known in advance or used multiple times with different second operands V to speed calculation. The operands V and W and the modulus M may be integers or polynomials over a variable X. A possible choice for the type of polynomials can be polynomials of the binary finite field GF(2N). Once operand W is loaded into a data storage location, a value P=?W·Xn+?/M? is pre-computed by the processing system. Then when a second operand V is loaded, the quotient q^ for the product V·W being reduced modulo M is quickly estimated, q^=?V·P/Xn+??, optionally randomized, q?=q^?E, and can be used to obtain the remainder r?=V·W?q?·M, which is congruent to (V·M) mod M. A final reduction can be carried out, and the later steps repeated with other second operands V.

Abstract: The invention relates to a method in creating a two-dimensional symbol pattern which may be utilized to determine a position in a large area covered by the pattern, for example for recording handwritten information by means of a pen-like instrument. The invention is useful for creating a symbol pattern having desired properties, namely that any sufficiently large observed part of the pattern is unique, enabling an unambiguous determination of position. The symbol pattern is based on a non-repeating sequence of symbol values Sk that each corresponds to a fixed linear combination of the coefficients of the monomials in xk mod P(x), where P(x) is any polynomial of degree n in the field Fq. The symbol pattern is generated by folding the sequence according to a wrapping scheme. The invention also relates to methods and systems for finding the position of a group of observed symbol values in this symbol pattern and computer program products performing the methods.

Abstract: Modulus scaling applied a reduction techniques decreases time to perform modular arithmetic operations by avoiding shifting and multiplication operations. Modulus scaling may be applied to both integer and binary fields and the scaling multiplier factor is chosen based on a selected reduction technique for the modular arithmetic operation.

Abstract: A system and method for processing data utilizes a matrix of processing units using an array of commands stored in memory to process input data words to generate output data words, which can be used in various applications.

Abstract: A method and apparatus for accelerating scalar multiplication in an elliptic curve cryptosystem (ECC) over prime fields is provided. Multiplication operations within an ECC point operation are identified and modified utilizing an equivalent point representation that inserts multiples of two. Algebraic substitutions of the multiplication operations with squaring operations and other cheaper field operations are performed. Scalar multiplication can also be protected against simple side-channel attacks balancing the number of multiplication operations and squaring operations and providing novel atomic structures to implement the ECC operation. In addition, a new coordinate system is defined to enable more effective operation of ECC to multiprocessor environments.

Abstract: Time to perform scalar point multiplication used for ECC is reduced by minimizing the number of shifting operations. These operations are minimized by applying modulus scaling by performing selective comparisons of points at intermediate computations based on primality of the order of an ECC group.

Abstract: The optical line terminal has a PON transceiver including an error correction code decoder. The error correction decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table. Also the optical network terminal has a PON transceiver including an error correction code decoder. The error code decoder includes: a shortening compensation parameter table; and a syndrome calculator for calculating a syndrome by referring to the shortening compensation parameter table, or an error search part for calculating an error position or an error value by referring to the shortening compensation parameter table.

Abstract: The computation time to perform scalar point multiplication in an Elliptic Curve Group is reduced by modifying the Barrett Reduction technique. Computations are performed using an N-bit scaled modulus based a modulus m having k-bits to provide a scaled result, with N being greater than k. The N-bit scaled result is reduced to a k-bit result using a pre-computed N-bit scaled reduction parameter in an optimal manner avoiding shifting/aligning operations for any arbitrary values of k, N.

Abstract: A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.

Abstract: A content delivery system, enabling a ciphertext to be reduced in size when using the ElGamal cipher, includes a content delivery device performing elliptic curve encryption on a content key, generating an encrypted content key that includes an x coordinate of an elliptic curve point obtained by the elliptic curve encryption, and outputting the encrypted content key. Further, the content delivery system includes content reception device receiving the encrypted content key, calculating a y coordinate of the elliptic curve point using the x coordinate included in the encrypted content key, and performing elliptic curve decryption using the elliptic curve point and other information included in the encrypted content key, to generate a decrypted content key.

Abstract: A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am?1tm?1+am?2tm?2+ . . . +a1t+a0, where the coefficients ai are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing a result of the arithmetic operation on the two binary polynomials to produce a congruent polynomial of degree less than a chosen integer n, with m?n. The partial reduction includes using a polynomial M?=(Mm(t)?tm)*tn?m, or a polynomial M?=Mm(t)*tn?m as part of reducing the result to the degree less than n and greater than or equal to m. The integer n can be the data path width of an arithmetic unit performing the arithmetic operation, a multiple of a digit size of a multiplier performing the arithmetic operation, a word size of a storage location, such as a register, or a maximum operand size of a functional unit in which the arithmetic operation is performed.

Abstract: A method of performing cell search includes receiving a primary synchronization signal (PSS) comprising a primary synchronization code (PSC), and receiving a secondary synchronization signal (SSS) comprising a first secondary synchronization code (SSC) and a second SSC. The first SSC and the second SSC are respectively scrambled by using a first scrambling code and a second scrambling code, and the first scrambling code and the second scrambling code are associated with the PSC. Detection performance on synchronization signals can be improved, and cell search can be performed more reliably.

Abstract: A method of performing cell search includes receiving a primary synchronization signal (PSS) comprising a primary synchronization code (PSC), acquiring an unique identity from the PSS, receiving a secondary synchronization signal (SSS) which is associated with a cell identity group, the SSS comprising two secondary synchronization codes (SSCs) and acquiring a cell identity which is defined by the unique identity within the cell identity group, wherein the two SSCs are respectively scrambled by using two different scrambling codes. Detection performance on synchronization signals can be improved, and cell search can be performed more reliably.