Abstract: An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n?1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n?1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n?1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles.

Abstract: An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.

Abstract: A method and apparatus for the generation of discrete power series values (PSVs) and associated PSV addresses. Repeated evaluations of a discrete power series are performed by a reduced complexity PSV generator, such that the need for multiplication operations is obviated. Each evaluation cycle performed by the reduced complexity PSV generator is modified by each primitive root of the desired discrete power series. For each PSV generated, a corresponding address is calculated to indicate the correct placement of the PSV generated.

Abstract: A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in the Galois field reciprocal generator the first Galois field element by the output of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m?2 times to obtain the reciprocal of the first Galois field element, and multiplies the reciprocal element by a second Galois field element for predicting the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform.

Abstract: A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).

Abstract: Methods and apparatus reducing the number of multipliers in Galois Field arithmetic are disclosed. Methods and apparatus for implementing n-valued Linear Feedback Shift Register (LFSR) based applications with a reduced number of multipliers are also disclosed. N-valued LFSRs with reduced numbers of multipliers in Fibonacci and in Galois configuration are demonstrated. Multiplier reduction methods are extended to n-valued functions with more than 2 inputs. Methods to create multiplier reduced multi-input n-valued function truth tables are disclosed. Methods and apparatus to implement these truth tables with a limited number of n-valued inverters are also disclosed. Scrambler/descrambler combinations with adders and multipliers over GF(2p) are provided. Communication, data storage and digital rights management systems using multiplier reduction methods and apparatus or the disclosed scrambler/descrambler combination are also provided.

Abstract: A method for dealing with Galois Field computation includes: providing an operating circuit which has at least a multiplicative inverse unit; and using the multiplicative inverse unit to execute at least a plurality of isomorphism maps for deriving a multiplicative inverse at a specific Galois Field corresponding to an input data, wherein the plurality of isomorphism maps include at least a change of basis.

Abstract: A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.

Abstract: An exponentiation circuit for computing an exponential power of a finite field element includes combinatory logic circuits that map input digits of a multi-digit field element P to output digits of an output multi-digit field element ?2m. The exponentiation circuit is capable of computing a power of a field element without performing any multiplication operations and requires only exclusive-OR logic operations to generate the output exponential field element. A circuit for generating a multiplicative inverse of a finite field element can be constructed from a set of parallel exponentiation circuits, with each of the parallel exponentiation circuits generating a different multi-digit field element ?2m directly from the input field element ?. Multiplier circuits multiply together the outputs of the parallel exponentiation circuits to generate the multiplicative inverse of the field element ?.

Abstract: Values X and N of n bits and a parameter t are input, then Y=X2?t mod N is calculated, then an extended binary GCD algorithm is executed for Y to obtain S=y?12k mod N and k, and R=S2?(k+t=2n) is calculated for S, thereby obtaining a Montgomery inverse R=X?122n mod N of X on a residue class ring Z/NZ.

Abstract: A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.

Abstract: A method for performing Montgomery multiplication on n bit numbers includes computing look-ahead partial sum values to generate a Montgomery result after n/2+1 iterations of intermediate result computations. According to one embodiment of the present invention, Montgomery multiplication is performed to compute A*B mod M where A, B, and M are n-bit numbers.

Abstract: A method for calculating a conversion parameter of the Montgomery modular multiplication to improve the efficiency of software installation, comprising a first step for calculating H0=2v×R (mod n) (where v is an integer, v?1, and (m×k)/v is an integer), a second step for calculating Hp=2v×2^p×R (mod n) from H0=2v×R (mod n) by repeating Hi=REDC(Hi?1, Hi?1)n with respect to i=1, 2, . . . , p (where p represents an integer satisfying the condition 2p?(m×k)/v>2p?1, REDC represents the Montgomery modular multiplication REDC(a, b)n=a×b×R?1 (mod n), and x^i represents exponential computation xi); and a third step for calculating Hp=R2 (mod n) by calculating Hp=REDC(Hp, g)n with respect to Hp obtained in the second step when 2p>(m×k)/v (where g=2k×E(p,m,k), E(p, m, k)=2×m?(v×2p)/k) and finally outputting Hp as R2 (mod n).

Abstract: A processor-executed computational method especially for use in cryptographic systems quickly determines a polynomial quotient under specific conditions. For a polynomial modulus f(x), a maximum degree for a polynomial i(x) to be reduced by this method is defined as the sum of the degree of f(x) and the difference d between the degrees of the two highest degree coefficients of f(x). Polynomials i(x) with degree less than this maximum can be divided by a^[deg(f(x))] instead of the full f(x) to quickly obtain the quotient value. With this quotient a residue value can be obtained, or optionally a random congruent value.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to a first quadratic extension GF(26), and GF(26) is extended to a second quadratic extension GF(212). In the 10-bit embodiment, the base field GF(2) is first extended to GF(25), and GF(25) is extended to a quadratic extension GF(210). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x2+x+K, where K is an element of the ground field whose absolute trace equals 1.

Abstract: Methods and apparati are provided for use in cryptographically processing information based on elliptic and other like curves. The methods and apparati allow pairings, such as, for example, Weil pairings, Tate Pairings, Squared Weil pairings, Squared Tate pairings, and/or other like pairings to be determined based on algorithms that utilize a parabola. The methods and apparati represent an improvement over conventional algorithms since they tend to me more computationally efficient.

Abstract: The cryptographic method is used in transactions for which a first entity generates, by use of a private RSA key, a proof verifiable by a second entity by use of a public RSA key associated with said private key. The public key includes an exponent and a modulus. The first entity generates a first element of proof by a calculation that can be performed independently of the transaction, and a second element of proof related to the first element of proof and which depends on a common number shared by the first and the second entities specifically for the transaction. The second entity verifies that the first element of proof is related, modulo the modulus of the public key, to a power of a generic number, with an exponent equal to a linear combination of the common number and of a product of the exponent of the public key by the second element of proof.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A method for determining, for use in ciphers, all of the prime numbers within the large numeric series: 5, 6, 7, 8, 9, 10, 11, 12, . . . , n, the method including steps of setting n?=?n/6?; establishing the small numeric series, 6(1)?1, 6(1)+1, 6(2)?1, 6(2)+1, 6(3)?1, 6(3)+1, . . .

Abstract: Provided are a key establishment method and system using commutative linear functions. In the method, a server defines a set of linear functions that use elements of a first finite field as coefficients and satisfy a commutative rule, selects a first linear function from the set, and selects a predetermined element from a second finite field. Next, the server selects a second linear function corresponding to each of nodes from the set, generates a predetermined combination function based on the first and second linear functions, generates a value of the second linear function using the selected element as a factor, and transmits the combination function and the value of the second linear function to a corresponding node. Each node receives the value of the second linear function from a server, exchanges the received values with the other nodes, computes a value using the exchanged value as a factor of the combination function, and establishes the computed value as a shared key between the nodes.

Abstract: Disclosed are a semi-sequential Galois field GF(2n) multiplier and the method thereof. The GF(2n) multiplier comprises two ground field multipliers over GF(2m), at least a constant multiplier, and multiple GF(2m) adders. The high-order and low-order elements from a composite field GF((2m)2) for one operand of one GF(2n) multiplication are inputted in parallel into the two ground GF(2m) multipliers, respectively. The high-order and low-order elements from the composite field of another operand of the GF(2n) multiplication are sequentially inputted into the two ground GF(2m) multipliers. As such, multiple partial products are generated. The constant multiplication and additions are performed on the multiple partial products through the constant multiplier and the GF(2m) adders. This generates a high-order element and a low-order element of the composite field GF((2m)2). After mapping these two elements of GF((2m)2) back to GF(2n), the GF(2n) multiplication is done.

Abstract: Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.

Abstract: A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.

Abstract: Embodiments of the present invention relate to a data processing system comprising a first arithmetic unit comprising at least one finite field multiplier and at least one finite field adder for selectively performing at least two finite field arithmetic calculations; the data processing system comprising means to use a previous finite field arithmetic calculation result in a current finite field arithmetic calculation to determine at least part of a polynomial.

Abstract: A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.

Abstract: Methods, apparatus and media for performing polynomial arithmetic operations over a Galois field having characteristic 2 and size 1 are disclosed. Such methods, apparatus and media include generating a binary representation of a polynomial over a Galois field having characteristic 2 and size 1, generating a plurality of right shifted binary representations of the first polynomial, and generating a binary representation of the polynomial reciprocal based upon a bitwise exclusive-OR of the binary representation of the polynomial and one or more right shifted binary representations selected from the plurality of right shifted binary representations.

Abstract: An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value.

Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.

Abstract: A method and device for computing the multiplicative inverse of element x in Galois field GF(p2m) is proposed. In particular, when p is a prime number and m is an integer, the inverse may be constructed based on the observation that xpm+1 is en element in sub-field GF(pm) and the inverse of xpm+1 can be carried out in the sub-field. The inverse of X may be obtained by multiplying x?1=(xpm+1)?1 by xpm.

Abstract: A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks.

Abstract: Systems and methods for computing modular polynomials modulo large primes are described. In one aspect, the systems and methods generate l-isogenous elliptic curves. A modular polynomial modulo a large prime p is then computed as a function of l-isogenous elliptic curves modulo p.

Abstract: A cryptographic system (1000) is provided. The cryptographic system includes a data stream receiving means (DSRM), a number generator (NG), a mixed radix accumulator (MRA) and an encryptor. The DSRM (1002) receives a data stream (DS). The NG (702) generates a first number sequence (FNS) contained within a Galois Field GF[M]. The MRA (750) is configured to perform a first modification to a first number (FN) in FNS. The first modification involves summing the FN with a result of a modulo P operation performed on a second number in FNS that proceeds FN. The MRA is also configured to perform a second modification to FN utilizing a modulo P operation. The MRA is further configured to repeat the first and second modification for numbers in FNS to generate a second number sequence (SNS). The encryptor (1004) is configured to generate a modified data stream by combining SNS and DS.

Abstract: An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided.

Abstract: Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data streams from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data streams via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data streams.

Abstract: A cryptographic system (CS) is provided. The CS (800) comprises a data stream receiving means (DSRM), a generator (702), a mixed radix converter (MRC) and an encryptor (908). The DSRM (902) is configured to receive a data stream (DS). The generator is configured to selectively generate a random number sequence (RNS) utilizing a punctured ring structure. The MRC (704) is coupled to the generator and configured to perform a mixed radix conversion to convert the RNS from a first number base to a second number base. The encryptor is coupled to the DSRM and MRC. The encryptor is configured to generate an altered data stream by combining the RNS in the second number base with the DS. The punctured ring structure and the MRC are configured in combination to produce an RNS in the second number base which contains a priori defined statistical artifacts after the mixed radix conversion.

Abstract: The essence of the invention is an effective method for generating the multiplicative inverse in a finite field GF(p) where p is prime, i.e. for generating the modular inverse. This method is derived from the Extended Euclidean Algorithm (EEA). The method is for binary execution of operations during the process of generating the modular inverse, with respect to the lowest number of addition, subtraction and shift operations possible. The proposed method avoids redundant operations for converting odd and negative values, which are performed in methods currently in use. To achieve that, negative numbers are represented in the two's complement code, values in the control part of the EEA are shifted to the left, and a new definition of the boundary and control conditions is utilized in the procedure. Minimizing the number of additions and subtractions is desirable for calculations with large numbers often encountered in cryptography.

Abstract: Apparatus for calculating a result of a modular multiplication of a first operand and a second operand with regard to a modulus, each having a length of 2 n bits, the operands and the modulus are split into sub-operands of half the length and are fed to controller controlling MMD unit for performing a MultModDiv operation in accordance with a predetermined step sequence with corresponding input operands and MMD moduli to obtain integer quotient values and residual values with regard to the MMD modulus at an output. The combiner is operable to combine integer quotient values and residual values from predetermined steps of the step sequence to obtain the result.

Abstract: This embodiment teaches a variation of GCD-based sieving, building tables of prime products, but intentionally restricting the size of table entries to fit within a single machine word. This combination allows one to mix advantages of the two most popular sieves, while retaining the simple and straightforward structure of the simpler one. Divisor length restriction can provide significant savings in the number of long divisions, but may be implemented with only two very specific primitives. The two primitives offer better optimization capabilities than a fully generic multiword arithmetic library.

Abstract: A method for power reduction and increasing computation speed for a Montgomery modulus multiplication module for performing modulus multiplication. A coding scheme reduces the hamming distance for partial product and multiple modulus selection, reducing MUX operations and power consumption. Synchronization registers synchronize partial product and multiple modulus values input to an accumulator reducing glitch and/or increase computation speed. Registers provide storage of previous values and reduce the need to obtain the values from a MUX, reducing MUX operations and/or reducing power consumption.

Abstract: A method and apparatus to square an element A when a defining polynomial of a finite field GF(2n) is expressed as f ? ( x ) = x n + ? i = 1 t ? ? x k i + 1 , and the element A contained in the finite field is expressed as A=(a0,a1,a2, . . . ,an?1)?GF(2n).

Abstract: A method of obtaining C=(c0, . . . , cn?1) of a product of two elements A and B of a finite field GF(2n). The method includes permuting the last d coefficients (an?1, . . . , an?d) of a multiplier A with predetermined variables (sn?1, . . . , sn?d); operating C:C=?(bi+j?A) for (I+j)th coefficient of a multiplicand B to update coefficients of C, where i and j are integers, and A:=(s, . . . ,?x?2)?(0,xn?1?j?f1, . . . ,sx?1?j?fx?d,0, . . . ,0) repeatedly for j=0 to (d?1) to update coefficients of A, where ? represents an XOR operation and ? represents an AND operation; and repeatedly performing the permuting and operating by increasing i from 0 to (n?1) by d.

Abstract: A present invention Galois field multiplier system and method utilize lookup tables to generate one partial product term and one feedback term in one clock cycle. In one embodiment, a Galois field multiplier system includes a plurality of shift registers, a plurality of exclusive OR components, a partial product lookup table, and a feedback table lookup table. The plurality of shift registers perform shift multiplication operation and are coupled to the plurality of shift registers that perform addition operations. The partial product lookup table and feedback lookup tables are selectively coupled to the exclusive OR components and values from the partial product lookup table and feedback lookup tables are fed into the selectively coupled exclusive OR components. Coefficients of the partial product term and feedback term are utilized as indexes to the partial product lookup table and feedback lookup table respectively.

Abstract: A device for determining an inverse of an initial value related to a modulus, comprising a unit configured to process an iterative algorithm in a plurality of iterations, wherein an iteration includes two modular reductions and has, as an iteration loop result, values obtained by an iteration loop of an extended Euclidean algorithm.

Abstract: A method or cryptographic system for communicating securely over an insecure communication channel of the type which communicates a message from a transmitter to a receiver includes the step of providing a finite filed serial-serial multiplication/reduction structure wherein an initial delay and clock-cycle are inherently independent of word length and wherein input operands are serially entered one digit at a time and the output result is computed serially one digit at a time, wherein the digit size can be one bit or more. As disclosed, the multiplication structure is scalable and a serial transfer reduces the bus width needed to transfer data back and forth between memory and a multiplication/reduction step. A finite field multiplication structure in which an operand multiplication and a finite field reduction are formulated as a serial-serial computation is also disclosed.

Abstract: A condensed Galois field computing system including a multiplier circuit for multiplying first and second polynomials with coefficients over a Galois field to obtain their product; and a Galois field linear transformer circuit for applying an irreducible polynomial of power n to the product including a partial result generator responsive to terms of power n and greater in the product for providing a folded partial result and a Galois field adder for condensing the folded partial result and the terms less than power n in the product to obtain Galois field transformer of power n of the product.

Abstract: Methods and systems relating to Weil-based spreading codes are described herein. In an embodiment, a method includes generating a set of Weil sequences, adapting a plurality of sequences of the set of Weil sequences to form a first plurality of codes, and selecting a second plurality of codes from the first plurality of codes. A code of the first plurality of codes is selected based at least on a correlation associated with the code. Each code of the first plurality of codes has a predetermined length.

Abstract: A data converter (1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (28) as a coefficient and respectively outputs data with 32 bits.