Abstract: Some embodiments are directed to a neural network training device for training a neural network. At least one layer of the neural network layers is a projection layer. The projection layer projects a layer input vector (x) of the projection layer to a layer output vector (y). The output vector (y) sums to the summing parameter (k).

Abstract: An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.

Abstract: A calculation processor for determining a digital output value from a digital input value based on an exponent value a, the processor comprising a first calculation block, a second calculation block and a final calculation block. The first calculation block initializes an intermediate value and an error value depending on a position of a Most Significant Bit of a significant part of the input value. The second calculation block is configured to perform repeatedly, until an exit criterion is fulfilled, the incrementation of a counter value, the determination of a power error value based on the error value and, if the power error value is larger than or equal to an error threshold, adjustment of the intermediate value y by multiplying the intermediate value with an adaptation value and setting the error value to the power error value divided by the base value. If the power error value is smaller than the error threshold, the error value is set to the power error value.

Abstract: Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.

Abstract: The present disclosure proposes an overcurrent protective circuit and a display panel. The overcurrent protective circuit includes a power supply circuit, a logic algorithm circuit, and an overcurrent protective circuit. The logic algorithm circuit is additionally arranged in the overcurrent protective circuit. The logic algorithm circuit set different threshold currents of overcurrent protection for the display panel according on different driving frequencies. The overcurrent protective circuit adjusts the protective components inside the overcurrent protective circuit in accordance with the set threshold currents. Therefore, the display panel is protected by the overcurrent protective circuit at different frequencies.

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

Abstract: Compression techniques can reduce the fronthaul throughput in split radio access network (RAN) architectures for next generation designs. Adaptive fixed-point mapping can reduce the throughput requirements between a baseband unit (DU) and a remote radio unit (RU). Thus, a bit or plurality of bits can indicate the type of data being passed over the fronthaul. Consequently, adaptive mapping between precoded downlink data and non-precoded downlink data suited to the type of data passed over the fronthaul can achieve high compression ratios.

Abstract: A nonlinear function operation device and method are provided. The device may include a table looking-up module and a linear fitting module. The table looking-up module may be configured to acquire a first address of a slope value k and a second address of an intercept value b based on a floating-point number. The linear fitting module may be configured to obtain a linear function expressed as y=k×x+b based on the slope value k and the intercept value b, and substitute the floating-point number into the linear function to calculate a function value of the linear function, wherein the calculated function value is determined as the function value of a nonlinear function corresponding to the floating-point number.

Abstract: Implementations of the disclosure provide logarithm and anti-logarithm operations on a hardware processor based on linear piecewise approximation. An example processor includes a piece wise linear log approximation circuit that receives an input of a floating-point number comprising a sign, an exponent and a mantissa. The piece wise linear log approximation circuit approximates a fractional portion of a fixed point number using a linear approximation of the mantissa of the floating-point number. The piece wise linear log approximation circuit also derives an integer from the exponent.

Abstract: Minimizing information leakage during modular exponentiation using random masks is disclosed Minimizing information leakage during elliptic curve point multiplication is disclosed with windowing by using point randomization is disclosed. Elliptic curve point multiplication with windowing calculates and stores multiple points based on the point being multiplied and then processes multiple bits of the multiplier at a time is also disclosed.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptic Curve Cryptography point addition algorithm for mixed Affine-Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Abstract: Methods for implementing fixed-point functions with user-defined input/output ranges and formats on a programmable integrated circuit are provided. A particular function may include one or more input intrusion intervals where generic fixed-point approximation methods are not sufficiently precise. Output values for these intrusion intervals may be pre-computed during function generation time using a mathematical library running on a computer-aided design tool and stored in a lookup table. During normal operation of the integrated circuit, a multiplexing network may be used to select among values generated by generic approximation methods and values obtained from one or more lookup tables depending on the current input to the function.

Abstract: Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A computer-implemented method to square a number x may include storing a t-digit vector representation of x in t b-bit registers of a processor. A 2t-digit intermediate vector may be generated and stored in 2t b-bit registers of the processor, using x stored in said t b-bit registers. A value stored in at least one of the t b-bit or 2t b-bit registers may be shifted to the left by n. n may be an integer at least equal to 1. At some point after the shifting, w, square of the number x, may be represented by the 2t-digit result vector stored in the 2t b-bit registers. Other embodiments may be described and/or claimed.

Abstract: An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation.

Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.

Abstract: A method for determining bit boundary of a navigation bit of a satellite signal received by a receiver is disclosed. The method includes dividing an assumed navigation bit equally into a plurality of power units, calculating unit powers of each of the plurality of power units, and determining a plurality of phases. Each of the plurality of phases is associated with an estimated bit boundary. The method further includes adding unit powers of the plurality of power units to obtain a plurality of bit powers. Each of the plurality of bit powers corresponds to the estimated bit boundary associated with one of the plurality of phases. The bit boundary of the navigation bit is determined based on the plurality of bit powers.

Abstract: According to an embodiment, a computing device includes an input unit and a power computing unit. The input unit is configured to input, in a form of vector representation, an element of an algebraic torus selected from elements of an M-th (M is an integer of 2 or greater) degree extension field obtained by extending a finite filed by an M-th order polynomial. The power computing unit is configured to compute an N-th (N is an integer of 2 or greater) power of the input element of the algebraic torus, computing the N-th power being performed on the basis of an arithmetic expression for computing the N-th power of an element of the M-th degree extension field expressed in the form of vector representation, and the arithmetic expression being satisfied when the element of the M-th degree extension field satisfies a condition for an element of the algebraic torus.

Abstract: The present invention relates to a method for performing an iterative calculation of exponentiation of a large datum, the method being implemented in an electronic device (DV1) and comprising calculations of squaring and multiplying large variables performed in parallel, by squaring (SB1) and multiplication (SM1) blocks, the method comprising steps of: while a temporary storage buffer memory is not full of unused squares, triggering a calculation by the squaring block for a bit of the exponent, when the squaring block is inactive, storing each square provided by the squaring block in the buffer memory, if the bit of the corresponding exponent is on 1, and while the buffer memory contains an unused square, triggering a calculation by the multiplication block concerning the unused square, when the multiplication block is inactive.

Abstract: Processing a neural signal sequence occurs in accordance with a neural signal spiking model that includes an exponential component (EC) and a polynomial component (PC). The exponential component is correlated with the presence of signal sequence noise, and the polynomial component is correlated with the presence of detectable signal sequence spikes distinguishable from the noise. A neural interface includes a frequency shaping amplifier (FSA) configured for receiving input signals; an amplifier gain stage and an analog-to-digital conversion (ADC) stage; a Hilbert transformer configured for performing a Hilbert transform upon neural signal data received from the ADC stage; a linear regression engine configured for estimating EC parameters and PC parameters corresponding to Hilbert transformed neural signal data; and a neural spike probability estimator configured for generating a neural spike probability map based upon the EC parameters and the PC parameters.

Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

Abstract: A multimeter with filtered measurement mode is disclosed. The multimeter includes a signal conditioning circuit, a low-pass filter, a microprocessor, a measurement circuit, a root-mean-square (RMS) converter, a display unit, and an external rotary switch. The signal conditioning circuit receives a control signal to select an operation mode of the multimeter. The low-pass filter is electrically connected to the signal conditioning circuit. The microprocessor is electrically connected to the signal conditioning circuit. The measurement circuit is electrically connected to the microprocessor and the RMS converter to measure a signal outputted from the RMS converter. The display unit is electrically connected to the microprocessor and the measurement circuit. Also, the external rotary switch is optionally connected to the microprocessor. Whereby rotating the external rotary switch to generate the control signal and perform a low-pass filtering mode to communicate the low-pass filter with the RMS converter.

Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

Abstract: Embodiments of the present invention provide systems, devices and methods for efficiently calculating a true RMS values (either voltage or current) of an AC signal. The RMS value is generated from both high and low frequency components of the AC signal without a high speed ADC being integrated within the system. The high frequency component is processed by calculating an average current waveform of the high frequency component and approximating a corresponding RMS value using a waveform factor. The waveform factor is effectively a scalar that relates the average current waveform of the high frequency component to an appropriate RMS value.

Abstract: A system and method are provided for use in an electronic device configured to process data to perform a method of generating a fixed point approximation of a number x by first locating the most significant bit of a given number, then retrieving predetermined values from electronic data storage, where the first value is based on a first index value generated from the most significant bit and contains fixed-point representation located in a table in storage. Then, output values are generated from look-up tables that correspond to index values generated from a number of bits that immediately following the most significant bit. Finally, the final mathematic result is computed using fixed-point arithmetic logic to generate a fixed point approximation.

Abstract: A method and apparatus for computing a discrete logarithm using a pre-computation table are provided. The method includes previously generating the pre-computation table consisting of chains of function values obtained by applying an iterating function to a predetermined number of initial values having a generator of the cyclic group as a base and having different exponents; and if a function value obtained by applying the iterating function to a value having a target element as a base and having an exponent is identical to a function value stored in the pre-computation table, computing the discrete logarithm of the target element by using exponent information of the two function values.

Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

Abstract: Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.

Abstract: In an arithmetic operation method and an arithmetic operation device arithmetic operations such as exponentiation or scalar multiplication can be performed at high speed. In the case where there exists a plurality of different elements Y and each element Y is represented by tuples in which a plurality of different elements X are combined with an operator, an arithmetic operation method for calculating each element Y by using an electronic computer, associates each element Y with the element X by setting each element X, sets temporary data having an index indicating whether or not each element Y has an identical element X for each element X, and represents each element Y by the temporary data combined with the operator. When there is a combination of temporary data which is common in plurality of elements Y in temporary data contained in each element Y, new temporary data is set by combining the common temporary data and each element Y consisting of each tuple is calculated using the new temporary data.

Abstract: Method and apparatus for data security using exponentiation. This is suitable for public key cryptography authentication and other data security applications using a one-way function. A type of exponentiation is disclosed here where the bits of an exponent value expressed in binary form correspond to a course (path) in a given graph defining the one-way function. This uses an approach called here F sequences. Each value is in a ladder of a sequence of values, as defined from its predecessor values. This ladder satisfies certain algebraic identities and is readily calculated by a computer program or logic circuitry.

Abstract: There are provided a computation method for scalar multiplication or exponentiation and a scalar multiplication program or an exponentiation program which can compute at high speed. In the computation method for scalar multiplication and the scalar multiplication program for computing scalar multiplication by n of a rational point Q in G with respect to a non-negative integer n using an electronic computer, since ?q(Q)=[q]Q=[t?1]Q holds true with respect to the rational point Q in G, (t?1)-adic expansion of a scalar n is performed and a Frobenius endomorphism ?q with respect to a rational point is used in place of t?1.

Abstract: A system for enabling a device to compute an outcome of an exponentiation Cx having a base C and/or an exponent x, the system comprising means for establishing a plurality of values ?i; means for establishing a plurality of values ?i satisfying ?i=C?i; means for establishing a plurality of values ?i satisfying that the sum of the values ?i?i equals x; and an output for providing the device with the plurality of values ?i. A device computes an outcome of the exponentiation Cx. The device comprises means for computing a product of the values ?i to the power of ?i. The device is arranged for using the product as a result of the exponentiation Cx.

Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.

Abstract: A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry 100 analyses the exponents of the input operands A and B as well as counting the leading zeros in the fractional portions of these operands to determine an amount of left shift or right shift to be applied by shifting circuitry 200, 202 within the multiplier data path. This shift amount is applied so as to align the partial products so that when they are added they will produce the result C without requiring this to be further shifted. Furthermore, shifting the partial products to the correct alignment in this way in advance of adding these partial products permits injection rounding combined with the adding of the partial products to be employed for cases including subnormal values.

Abstract: A multimeter with filtered measurement mode is disclosed. The multimeter includes a signal conditioning circuit, a low-pass filter, a microprocessor, a measurement circuit, a root-mean-square (RMS) converter, a display unit, and an external rotary switch. The signal conditioning circuit receives a control signal to select an operation mode of the multimeter. The low-pass filter is electrically connected to the signal conditioning circuit. The microprocessor is electrically connected to the signal conditioning circuit. The measurement circuit is electrically connected to the microprocessor and the RMS converter to measure a signal outputted from the RMS converter. The display unit is electrically connected to the microprocessor and the measurement circuit. Also, the external rotary switch is optionally connected to the microprocessor. Whereby rotating the external rotary switch to generate the control signal and perform a low-pass filtering mode to communicate the low-pass filter with the RMS converter.

Abstract: In general, techniques are described that provide for 4×4 transforms for media coding. A number of different 4×4 transforms are described that adhere to these techniques. As one example, an apparatus includes a 4×4 discrete cosine transform (DCT) hardware unit. The DCT hardware unit implements an orthogonal 4×4 DCT having an odd portion that applies first and second internal factors (C, S) that are related to a scaled factor (?) such that the scaled factor equals a square root of a sum of a square of the first internal factor (C) plus a square of the second internal factor (S). The 4×4 DCT hardware unit applies the 4×4 DCT implementation to media data to transform the media data from a spatial domain to a frequency domain. As another example, an apparatus implements a non-orthogonal 4×4 DCT to improve coding gain.

Abstract: Method of cryptography in a smart card comprising a central processing unit, said method implementing precomputation operations, characterized in that said precomputation operations are performed by the smart card and in that the precomputation operations are carried out at a session during the waiting periods of the inputs/outputs of the central processing unit.

Abstract: An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(?1k), (?2k), (?3k), . . . } falls within a maximum period (2m-1), the group being produced as an element (?k) obtained by raising a root ? of a polynomial to a specified power value k (k?2), which have the terms in polynomials of a Galois field GF(2m). In a multiplying unit including the gates, pieces of bit data is fed into one end of the multiplying unit in response to the clock while the element (?k) is fed into the other end. The multiplying unit performs Galois field multiplication between each piece of bit data and the element (?k), the gate supplies the multiplication result as feedback bit data to the respective registers.

Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.

Abstract: A function that represents data points is derived by creating a matrix (e.g., a Hankel matrix) of an initial rank, where the matrix contains the data points. Singular values are derived based on the matrix, and it is determined whether a particular one of the singular values satisfies an error criterion. In response to determining that the particular singular value does not satisfy the error criterion, the rank of the matrix is increased and the deriving and determining tasks are repeated. In response to determining that the particular singular value satisfies the error criterion, values of parameters that approximate the function are computed.

Abstract: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.

Abstract: The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number.

Abstract: A method of calculating a transport block size in an HSPA receiver of a communication system is provided. After decomposing an exponential function Pk into a plurality of constant vectors, the invention needs only little memory space and executes few continued multiplication operations to obtain a correct transport block size, thereby increasing efficiency and reducing calculation complexity.

Abstract: Methods (200, 300) for determining a reference signal (Vref). The methods involve (202, 204, 302, 304) sensing at a first location along the transmission media (108, 502) a first signal (Vf) propagated thereover in a forward direction and a second signal (Vr) propagated thereover in a reverse direction opposed from the forward direction. The second signal being a reflected version of the first signal. A sum signal (S) is determined (206, 306) by adding the first and second signals together. A difference signal (D) is determined (208, 308) by subtracting the second signal from the first signal. Thereafter, a first exponentiation signal (ES) is determined (210, 310) using S. A second exponentiation signal (ED) is determined (212, 312) using D. The first exponentiation signal is subtracted (214, 314) from the second exponentiation signal to obtain a reference signal (Vref). Vref can be determined at any location along the transmission media.

Abstract: A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.

Abstract: Certain embodiments described herein are directed to chromatography systems that include a microfluidic device. The microfluidic device can be fluidically coupled to a switching valve to provide for selective control of fluid flow in the chromatography system. In some examples, the microfluidic device may include a charging chamber, a bypass restrictor or other features that can provide for added control of the fluid flow in the system. Methods of using the devices and methods of calculating lengths and diameters to provide a desired flow rate are also described.

Abstract: Embodiments of the present invention provide systems, devices and methods for efficiently calculating a true RMS values (either voltage or current) of an AC signal. The RMS value is generated from both high and low frequency components of the AC signal without a high speed ADC being integrated within the system. The high frequency component is processed by calculating an average current waveform of the high frequency component and approximating a corresponding RMS value using a waveform factor. The waveform factor is effectively a scalar that relates the average current waveform of the high frequency component to an appropriate RMS value.

Abstract: In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result.

Abstract: A system and method are provided for use in an electronic device configured to process data to perform a method of generating a fixed point approximation of a number x by first locating the most significant bit of a given number, then retrieving predetermined values from electronic data storage, where the first value is based on a first index value generated from the most significant bit and contains fixed-point representation located in a table in storage. Then, output values are generated from look-up tables that correspond to index values generated from a number of bits that immediately following the most significant bit. Finally, the final mathematic result is computed using fixed-point arithmetic logic to generate a fixed point approximation.

Abstract: A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn?i·yi], wherein the initial matrix [Eni=xn?i·yi] is transformed into a matrix [Eni=(xn?i?yi)·(yi?1?yi)=(xn?i?y1)·Yi] with Yi=yi?1?yi or [Eni=eni·Yi] with eni=xn?i?yi. A first approximation Un0 and Rn?1i?1 is formed of the sum and carry of the first two rows y0 and y1 of this matrix, and this is used as an input for the following estimation step which is repeated for all the following rows, successively carrying out the addition of the following Yi+1 rows up to the last non-zero row, according to a first given series of propagation equations, and then the propagation of the carries Rni?1 is carried out over the zero Yi+1 rows according to a second given series of propagation equations, in order to obtain the final result of the product P.

Abstract: A power-residue calculating unit according to one embodiment of the present invention includes a multiplication residue calculating unit performing a multiplication calculation and a residue calculation based on a multiplicand, a multiplier, and a divisor, a power storing portion separately storing value of each bit when a power is shown by a binary number, a first selecting circuit outputting one of an output of the multiplication residue calculating unit and the multiplicand depending on the value of the bit that is referred, and a result storing register storing an output value of the first selecting circuit as a calculation result.