Abstract: A method and apparatus receiving number and using instruction to create resulting number approximating one of square root, reciprocal, or reciprocal square root of number. The resulting number as a product of that process. Using resulting number in a graphics accelerator. Apparatus preferably includes log-calculator, log-arithmetic-unit, and exponential-calculator. At least one of log-calculator and exponential-calculator include implementation non-linear calculator. The non-linear calculators may use at least one of mid-band-filter, outlier-removal-circuit. The invention includes making arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator. The arithmetic circuit, log-calculator, log-arithmetic-unit and exponential-calculator as products of manufacture. The arithmetic circuit may further include at least one of a floating-point-to-log-converter and/or a second of log-calculators.

Abstract: Method and apparatus for data security using exponentiation. This is suitable for public key cryptography authentication and other data security applications using a one-way function. A type of exponentiation is disclosed here where the bits of an exponent value expressed in binary form correspond to a course (path) in a given graph defining the one-way function. This uses an approach called here F sequences. Each value is in a ladder of a sequence of values, as defined from its predecessor values. This ladder satisfies certain algebraic identities and is readily calculated by a computer program or logic circuitry.

Abstract: Methods are provided for the classification of search engine queries and associated documents based on search engine query click logs. One or more seed documents or queries are provided that contain content that is representative of a category. A query click log containing information regarding queries entered by at least one user into the search engine and documents subsequently clicked in search engine results corresponding with the queries is analyzed to determine which one or more queries resulted in clicks on the seed documents. Information is stored associating the one or more queries with the category if they resulted in clicks on the seed documents.

Abstract: In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256).

Abstract: After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing strategy may be shown to be more efficient than a bit-by-bit reducing strategy.

Abstract: A method, system, and apparatus for performing computations. In a method, arguments X and K are loaded into session memory, and X mod P and X mod Q are computed to give, respectively, XP and XQ. XP and XQ are exponentiated to compute, respectively, CP and CQ. CP and CQ are merged to compute C, which is then retrieved from the session memory. A system includes a computing device and at least one computational apparatus, wherein the computing device is configured to use the computational apparatus to perform accelerated computations. An apparatus includes a chaining controller and a plurality of computational devices. A first chaining subset of the plurality of computational devices includes at least two of the plurality of computational devices, and the chaining controller is configured to instruct the first chaining subset to operate as a first computational chain.

Abstract: After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing strategy may be shown to be more efficient than a bit-by-bit reducing strategy.

Abstract: The present invention provides a method and system for computing a matrix power series according to one embodiment of the present invention. Memory structures for storing a partial sum, current and previous series terms are allocated. First and second pointers are assigned to refer to a memory location storing a current series term and a previous series term respectively. During each phase of a process to compute a current partial sum, the pointers are exchanged.

Abstract: A circuit for performing an arithmetic function on a number performs the function using successive approximation. Each approximation produces an estimate of the result. A determination of the utility of this estimate is made by comparing the inverse function of a given estimate to the number. The current estimate is updated based on this comparison and the inverse function of the current estimate is stored. The next estimate is an incremental change from the previous estimate and there is a corresponding incremental change in the inverse function from the current estimate to the next estimate. Rather than calculating the whole inverse function, which would typically require a multiplier, only the incremental change in the inverse function is provided simply. The incremental change in the inverse function is then added to the inverse function of the current estimate and compared to the number for determining the utility of the next estimate.

Abstract: A 0.75-power computation apparatus and method are provided in which the range of an input value X is divided into a predetermined number areas, a 0.75 power of the input value X is represented as a predetermined approximation polynomial, coefficients for the approximation polynomial representing the input value X are preset for each of the areas, predetermined coefficients of the approximation polynomial are checked according to an actual input value X, and a 0.75-power of the actual input value X is computed using the approximation polynomial.

Abstract: An extendable squarer for processing digital signals, suitable for processing a square operation for n-bit data is disclosed. The extendable squarer comprise a bit expanding circuit and a plurality of operating units. The bit expanding circuit comprises n?1 bit expanding output terminals for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes of the n-bit data corresponding thereto according to the binary weight. In addition, except for bit code of the most-significant bit, the other operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention generates the square operation value of the n-bit data based on the corresponding bit expanding data and bit codes.

Abstract: An exponent calculation apparatus calculates xe based on input two integers x and e. A pre-calculation module pre-calculates x^{l_i} for each of candidate exponents {l_i} (0?i?L?1) stored in a candidate exponents storing unit, the number of the candidate exponents being L, and stores the obtained values x^{l_i} in a pre-calculated values storing unit. A dividing module divides the integer e into a plurality of values {f_i} (0?i?F?1) so that each of the values {f_i} corresponds to one of the candidate exponents {l_i}. A sequential processing module sequentially updates a calculation result c, which is stored in a calculation result storing unit, for each of the values {f_i} by using each of the values x^{l_i}. The updated calculation result c for each of the values {f_i} is output as xe. Accordingly, the amount of pre-calculation and table size can be reduced and thus the number of calculations can be reduced.

Abstract: A system and method for accurately calculating a mathematical power function in an electronic device may include an application program that is configured to calculate a direct estimate of power function value for the mathematical power function during a direct linear interpolations procedure. The application program may also calculate an indirect estimate of power function value for a complement power function during an indirect linear interpolation procedure. The application program may then perform a final function-estimate calculation procedure to accurately produce a final estimated power function value from the foregoing direct estimate of power function value and indirect estimate of power function value.

Abstract: A power of a square matrix is determined in a time approximately proportional to the upper integer of the base-2 logarithm of the order of the matrix. A preferred embodiment uses two types of look-up tables and two multipliers for a matrix of 15×15, and is applied to a pseudorandom noise (PN) sequence phase correlation or state jumping circuit. An exact state of a PN code can be determined or calculated from applying an appropriate offset value into a control circuit. The control circuit can produce a PN sequence state from the offset value and typically does so within one system clock period regardless of the amount of the offset. Once the exact state is determined, it is loaded into a state generator or linear sequence shift register (LSSR) for generating a subsequent stream of bits or symbols of the PN code. The PN generator system may include state computing logic, a maximum length PN generator, a zero insertion circuit and a zero insertion skipping circuit.

Abstract: For calculating the result of an exponentiation Bd, B being a base and d being an exponent which can be described by a binary number from a plurality of bits, a first auxiliary quantity X is at first initialized to a value of 1. Then a second auxiliary quantity Y is initialized to the base B. Then, the bits of the exponent are sequentially processed by updating the first auxiliary quantity X by X2 or by a value derived from X2 and by updating the second auxiliary quantity Y by X*Y or by a value derived from X*Y, if a bit of the exponent equals 0. If a bit of the exponent equals 1, the first auxiliary quantity X is updated by X*Y or by a value derived from X*Y and the second auxiliary quantity Y is updated by Y2 or by a value derived from Y2. After sequentially processing all the bits of the exponent, the value of the first auxiliary quantity X is used as the result of the exponentiation. Thus a higher degree of security is obtained by homogenizing the time and current profiles.

Abstract: To provide an audio signal quantization device in which an amount of arithmetical operation can be reduced. A 0.75-power computing apparatus includes: an inverse number computing unit; a first ?0.5-power computing unit; a multiplication unit; a second ?0.5-power computing unit; and a program storage medium that is connected to an outside, whereby a program stored in the program storage medium is executed to compute the 0.75-power in a quantization computing expression. The inverse number computing unit, the first ?0.5-power computing unit, the multiplication unit, and the second ?0.5-power computing unit operate in such a manner that a multiplication between an infinity and zero which leads its operation result to an indefinite value is inhibited.

Abstract: A squaring circuit for signed binary numbers includes a signed binary number modification unit that generates a modified signed binary number. The squaring circuit includes a partial product generation unit that generates partial products that make up a squared value of the modified signed binary number. The squaring circuit includes a correction value generation unit that generates a correction value for the signed binary number. The squaring circuit includes a summing unit that sums the partial products with the correction value to generate a squared value for the signed binary number.

Abstract: An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square root unit (130) extracts the square root of the sum (120) of these squares, which is absolute value of the complex number. Each squaring unit includes one unsigned multipliers for respective least significant and two signed multipliers for respective most significant bits and a cross term. The products are aligned by shifting and summed. The square root unit employs identical processing elements, each considering two bits of the input and forming one root bit and a remainder. Each processing element compares two intermediate test variables, and selects a “1” or “0” for the root bit and the next remainder based upon this comparison. A chain of processing elements enables computation of the root to the desired precision. Alternatively, the same processing elements may be used in a recirculating manner.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.

Abstract: An apparatus for calculating an exponential calculating result for a base 2 floating-point number comprises a transforming device, K exponential tables and a multiplier. The transforming device receives the floating-point number, transforms the floating-point number to an integer part and a fractional part and outputs the integer part and the fractional part. The fractional part is an N-bit number and divided into K parts which have N1, N2, . . . , NK bits respectively, wherein N=N1+N2+ . . . +NK. Each of the exponential tables receives one of the K parts divided from the fractional part and outputs a result. The multiplier receives all results from the exponential tables and outputs a mantissa. The integer part outputted form the transforming device is an exponent.

Abstract: An exponent part extraction section extracts a bit series from the exponent part of an inputted floating point data. A mantissa part extraction section extracts the uppermost K bits from the mantissa part of the floating point data. A first conversion section inputs the output e from the exponent part extraction section and outputs the value of a function X(e) thereof. A second conversion section inputs the output f from the mantissa part extraction section and outputs the value of a function Y(f) thereof. A multiplier section multiplies together these values. By setting suitable tables in advance in the first and the second conversion sections, the calculation of the v^p for an item v of floating point data can be performed.

Abstract: For calculating the result of an exponentiation Bd, B being a base and d being an exponent which can be described by a binary number from a plurality of bits, a first auxiliary quantity X is at first initialized to a value of 1. Then a second auxiliary quantity Y is initialized to the base B. Then, the bits of the exponent are sequentially processed by updating the first auxiliary quantity X by X2 or by a value derived from X2 and by updating the second auxiliary quantity Y by X*Y or by a value derived from X*Y, if a bit of the exponent equals 0. If a bit of the exponent equals 1, the first auxiliary quantity X is updated by X*Y or by a value derived from X*Y and the second auxiliary quantity Y is updated by Y2 or by a value derived from Y2. After sequentially processing all the bits of the exponent, the value of the first auxiliary quantity X is used as the result of the exponentiation. Thus a higher degree of security is obtained by homogenizing the time and current profiles.

Abstract: An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Zn) into a first part (msb(Zn)) that is the power of 2 immediately lower than or equal to the input signal and a second part (Zn−msb(Zn)) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.

Abstract: A method for calculating the power of an integer raised to a constant real number. The method may be used to process digital signals, which are encoded in such a fashion as to require such processing. An embodiment of the present invention first receives a segment of a bitstream. Next, the process determines whether an integer value of the segment is within a look-up table. The look-up table contains a list of integers and a corresponding list of the integers raised to the power of a real number. If the integer value is within the look-up table, the process indexes the look-up table with the integer value to determine substantially the value of the integer raised to the real power. If, however, the integer value is not within the look-up table, the process indexes the table with a plurality of integers which are within the table to approximate the value of the segment from the bitstream raised to the real power. The process repeats these steps for each segment in the signal bitstream.

Abstract: An apparatus and method for generating the square of a non-linear encoded signal having a value and a segment number includes an offset generator, a multiplier and a shifter. The offset generator receives the value of the encoded signal and adds an offset value to it thereby to generate a multiplicand. The multiplicand is squared by the multiplier and the output of the multiplier is conveyed to the shifter. The shifter shifts the output of the multiplier in accordance with the segment number thereby to generate the square of the encoded signal. The offset, multiplying and shifting steps can be performed in a single clock cycle.

Abstract: A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method including the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segments each having a length of the predetermined operand size; multiplying a first segment value by a second segment value to generate a first product value; the second at least one of the segment values to derive a second product value; halving the second product value to generate a halved second product value; accumulating the first product value with the halved second product value to generate an accumulated value; and doubling the accumulated value to generate the intermediate result.

Abstract: An exponent calculation apparatus calculates xe based on input two integers x and e. A pre-calculation module pre-calculates x{circumflex over ( )}{l_i} for each of candidate exponents {l_i} (0≦i≦L−1) stored in a candidate exponents storing unit, the number of the candidate exponents being L, and stores the obtained values x{circumflex over ( )}{l_i} in a pre-calculated values storing unit. A dividing module divides the integer e into a plurality of values {f_i} (0≦i≦F−1) so that each of the values {f_i} corresponds to one of the candidate exponents {l_i}. A sequential processing module sequentially updates a calculation result c, which is stored in a calculation result storing unit, for each of the values {f_i} by using each of the values x{circumflex over ( )}{l_i}. The updated calculation result c for each of the values {f_i} is output as xe.

Abstract: A system and method for accurately calculating a mathematical power function in an electronic device may include an application program that is configured to calculate a direct estimate of power function value for the mathematical power function during a direct linear interpolations procedure. The application program may also calculate an indirect estimate of power function value for a complement power function during an indirect linear interpolation procedure. The application program may then perform a final function-estimate calculation procedure to accurately produce a final estimated power function value from the foregoing direct estimate of power function value and indirect estimate of power function value.

Abstract: Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.

Abstract: An encryption/decryption method performs an exponentiation operation on a base number where both the base number and the exponent may be large numbers (i.e., anywhere from 100 to several thousand bits long). The exponent is expressed as a bit string. The bit string is then re-coded utilizing the signed digit algorithm. Predetermined substring patterns are then extracted from the exponent utilizing a string replacement method and compared to a previously constructed look-up table containing exponent values for only a relatively small number of predetermined substrings. The value returned from the look-up table is the base value raised to the power represented by the substring. A pointer for each matching substring in the exponent is stored. The remaining bits in the exponent and intermediate values and are then processed with the base value using a multiply chain algorithm to determine the value of the base raised to the exponent.

Abstract: A floating point exponentiation circuit suitable for calculating the value BE is disclosed where B and E are floating point values. The floating point exponentiation circuit includes circuitry for producing a value P, where P is approximately equal to E*((BEXP−127)+log2(1.BMAN), BEXP is an exponent field of the base B, and 1.BMAN is a 24-bit mantissa field of the base B. The floating point exponentiation circuit further includes circuitry for adjusting the value P wherein the floating point representation of the adjusted value of P includes a mantissa field that indicates an integer portion Pi of P and a fractional portion Pf of P.

Abstract: An image processing apparatus that can reduce a data amount of the image with avoiding a negative effect on the image quality, in which a root-mean-square value of pixel data is calculated by a square circuit, an addition circuit, a register and a shift circuit. Also, a square of a mean of the pixel data is calculated by an addition circuit, a register, a shift circuit and a square circuit. Then, by a subtraction circuit, a difference between the root-mean-square value of the pixel data and the square of a mean of the pixel data is calculated. The value is applied for generation of activity data indicating complexity of the image.

Abstract: A device for controlling the table capacity smaller comprises a table of logarithms and a table of exponents preserving values of a logarithmic function and exponential function with a base of the second power, a multiplier, a shift unit for shifting the input value by a proper integer when the domain of logarithm is not included in the input value range of the table of logarithms, a logarithm addition unit for adding the shift amount to the value referred to in the table of logarithms, an exponent subtraction unit for subtracting a proper integer L from the input value when the domain of the exponential function is not included in the input value range of the table of exponents, and an exponent shift unit for shifting the referred value in the table of exponents the subtraction amount. A high-speed processing unit comprises a converter for converting floating-point data to fixed-point data having a bit of decimal point.

Abstract: A method suitable for calculating an expression having the form (A/B)K by a processor that features separate sets of floating point units which can operate in parallel for greater speed of execution. The processor issues instructions to determine an approximate reciprocal R0 of a first variable B. Further instructions are issued to raise a second variable to the power of a third variable K by a first set of arithmetic units of the processor, where the second variable is a function of the approximate reciprocal R0. Still further instructions are issued to calculate a polynomial q at a fourth variable delta by a second set of arithmetic units of the processor. The fourth variable delta is also a function of the approximate reciprocal R0. Finally, one or more instructions are issued to multiply the calculated polynomial by the second variable, having been raised to the power of the third variable, to yield (A/B)K.

Abstract: A method of the data conversion, a data conversion circuit and a data conversion program are provided which make the memory capacity of the circuit for storing the converted data small and can make the error of the output data small. To comprise a priority encoder 11 outputting bit number of “1” located at the most significant bit in the input data as L data, a bit-extracting portion outputting (L-1) to (L-2) bits in the input data as N data and (L-3) to 0 bits as M data, a table address forming portion 13 outputting a first address obtained by combining the L data with the M data, a conversion-table storing portion 14 storing a conversion table where converted data corresponds to table addresses, a multiplexer 15 selecting 0 or converted data and a linear interpolation portion 20 processing interpolation based on the two converted data.

Abstract: A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable to perform a look ahead operation and establish the location of the MSB (Most Significant Bit) in the calculation results; and combinational circuits for performing the rounding off process and the calculation of the variables by using information concerning a carry, which is generated by the pseudo carry generator and based on the location of the MSB determined by the MSB look ahead circuit.

Abstract: This invention is a method and apparatus which provide a solution to the problem of constructing efficient and secure digital signature schemes. It presents a signature scheme that can be proven to be existentially unforgeable under a chosen message attack, assuming a variant of the RSA conjecture. This scheme is not based on “signature trees”, but instead it uses a “hash-and-sign” paradigm, while maintaining provable security. The security proof is based on well-defined and reasonable assumptions made on the cryptographic hash function in use. In particular, it does not model this function as a random oracle. The signature scheme which is described in this invention is efficient. Further, it is “stateless”, in the sense that the signer does not need to keep any state, other than the secret key, for the purpose of generating signatures.

Abstract: An exponent preprocessing unit preprocesses an n-bit exponent k and exponentiates a base A by the preprocessed exponent k. A bit string storing unit stores a bit string including a sign bit and the exponent k. A reading unit reads a bit pattern composed of the sign bit and a bit sequence made up of a predetermined number of bits. A bit pattern generating unit generates a new bit pattern from the read bit pattern. An operation pattern specifying unit specifies an operation pattern based on the read bit pattern. An operating unit performs an operation according to the specified operation pattern and writes the new bit pattern over the previous bit pattern. The reading unit reads a next bit sequence starting from a different bit in the bit string storing unit. A repeat controlling unit repeats these procedures n+1 times.

Abstract: Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.

Abstract: A power-residue calculating unit includes: a first register group holding a first kind of data; a second register group holding a kind of data to be referred to concurrently with the data held in the first register group; a first internal bus connected to the first register group; a second internal bus connected to the second register group; a Montgomery multiplication residue calculation executing portion connected to the first and second internal buses for concurrently referring to the data held in the first and second register groups and executing a Montgomery multiplication residue calculation; and a power-residue calculation executing portion connected to the first and second internal buses and the Montgomery multiplication residue calculation executing portion for concurrently referring to the data held in the first and second register groups, communicating data with the Montgomery multiplication residue calculation executing portion, and executing a power-residue calculation.

Abstract: A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e.

Abstract: A method of calculating xM/N, x having a range and M and N integers. The range of x is partitioned into a selected number of intervals and a determination is made as to the interval into which x falls. x is normalized with a normalization factor calculated for the interval into which x falls to obtain a normalized value x′ within a normalized range. A value of x′M/N is calculated over the normalized range and a value for xM/N is calculated by multiplying the calculated value of x′M/N by a renormalization factor calculated for the interval in which x falls.

Abstract: The present application relates to a device and method for processing a digital value to thereby determine an estimate of the square of said digital value. This is done by linearly approximating the square function with the help of anchor points that are powers of 2, such that the estimate of the square of a digital value xa is determined on the basis of a first processing value 2i, where 2i≦xa<2i+1, and a second processing value (3xa−2i+1). The present invention is advantageous in that it allows simple processing steps and a simple processing hardware. It is preferably applied to the mean signal power estimation of a digital signal being sent to a transmitter.

Abstract: A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 22k that has a 1 value only if one input bit of weight 2(k−1) has a 0 value while another input bit of weight 2k has a 1 value. Another more significant partial product bit of weight 2(2k+1) receives the same input bits and has a 1 value only if both of the input bits have a 1 value. In this manner, the number of partial product bits in the column of weight 22k is decreased by 1 while the number of bits is the column of weight 2(2k+1) is increased by 1. Therefore, if the column of weight 22k had the greatest number of partial product bits of all columns, and if the column of weight 2(2k+1) had at least two fewer bits than the column of weight 22k, the total maximum number of bits for all the columns is reduced by 1.

Abstract: The present invention relates to a system and method to efficiently approximate the term 2X. The system includes an approximation apparatus to approximate 2X, wherein X is a real number. The system further includes a memory to store a computer program that utilizes the first approximation apparatus. The system also includes a central processing unit (CPU) that is cooperatively connected to the approximation apparatus and the memory, and that executes the computer program.

Abstract: To provide an audio signal quantization device in which an amount of arithmetical operation can be reduced. A 0.75-power computing apparatus includes: an inverse number computing unit; a first −0.5-power computing unit; a multiplication unit; a second −0.5-power computing unit; and a program storage medium that is connected to an outside, whereby a program stored in the program storage medium is executed to compute the 0.75-power in a quantization computing expression. The inverse number computing unit, the first −0.5-power computing unit, the multiplication unit, and the second −0.5-power computing unit operate in such a manner that a multiplication between an infinity and zero which leads its operation result to an indefinite value is inhibited.

Abstract: A new scheme for fast realization of encryption, decryption and authentication which can overcome the problems of the RSA cryptosystem is disclosed. The encryption obtains a ciphertext C from a plaintext M according to C≡Me (mod n) using a first secret key given by N (≧2) prime numbers p1, p2, . . . , pN, a first public key n given by a product p1k1 p2k2 . . . pNkN where k1, k2, . . . , kN are arbitrary positive integers, a second public key e and a second secret key d which satisfy ed≡1 (mod L) where L is a least common multiple of p1−1, p2−1, . . . , pN−1. The decryption recovers the plaintext M by obtaining residues Mp1k1, Mp2k2, . . . , MpNkN modulo p1k1, p2k2, . . . , pNkN, respectively, of the plaintext M using a prescribed loop calculation with respect to the first secret key p1, p2, . . . , pN, and by applying the Chinese remainder theorem to the residues Mp1k1, Mp2k2, . . . , MpNkN. This encryption/decryption scheme can be utilized for realizing the authentication.

Abstract: A circuit for squaring an n-bit value includes a partial product bit generator which logically AND's a bit of the n-bit value having a weight 2k (k is an integer) with the same bit of weight 2k to generate a partial product bit of weight 22k. Another partial product bit generator receives and logically AND's a bit of the n-bit value of weight 2k and a bit of weight 2m (m is an integers) to generate a partial product bit of weight 2(k+m+1). The second partial product bit generator may be the only partial product bit generator in the squaring circuit to logically AND the bit of weight 2m and the bit of weight 2k. The circuit may also include other partial product bit generators. However, the required number of partial product bit generators is significantly reduced by about ½ compared to the conventional squaring circuit. The associated Wallace tree structure is simplified and made smaller because of the reduction in partial product bits.