Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

Abstract: A device of the present invention is an exponential calculation device for calculating x{circumflex over ( )}(a/b) (where a and b are each an integer constant) for a given input value of x. The device includes: an input control section for outputting a value of x′, wherein x′=x when x≦A (where A is a threshold value within a variable range of x) and x′=x/2{circumflex over ( )}b when x>A; a core section for outputting a value of z′=x′{circumflex over ( )}(a/b); and an output control section for outputting a value of z, wherein z=z′ when x≦A and z=z′*2{circumflex over ( )}a when x>A.

Abstract: A device of the present invention is an exponential calculation device for calculating x−(a/b) (where a and b are each an integer constant) for a given input value of x. The device includes: an input control section for outputting a value of x′, wherein x′=x when x≦A (where A is a threshold value within a variable range of x) and x′=x/2ˆ b when x>A: a core section for outputting a value of z′=x′ (a/b); and an output control section for outputting a value of z, wherein z=z′ when x≧A and z=z′*2 a when x>A.

Abstract: An exponent part extraction section extracts a bit series from the exponent part of an inputted floating point data. A mantissa part extraction section extracts the uppermost K bits from the mantissa part of the floating point data. A first conversion section inputs the output e from the exponent part extraction section and outputs the value of a function X(e) thereof. A second conversion section inputs the output f from the mantissa part extraction section and outputs the value of a function Y(f) thereof. A multiplier section multiplies together these values. By setting suitable tables in advance in the first and the second conversion sections, the calculation of the vˆ p for an item v of floating point data can be performed.

Abstract: An apparatus to calculate a remainder of Bc modulo n at high speed with minimum hardware resources, while securing safety of a key comprises: a first circuit to execute a process of calculating B (mod n) and holding the calculation result B1 and to repeat a process of shifting a holding value and calculating a value congruent to the shifted holding value modulo n and holding the calculation result; a first register for storing the B1 as an initial value; a second circuit to cumulate the calculation result of the first circuit when a value of a bit at a predetermined position of the first register is equal to 1; a second register to store 1 as an initial value; a C output circuit to output C; a third circuit to cumulate the calculation result of the first circuit when an output value from said C output circuit is equal to 1 and a value of a bit at a predetermined position of the second register is equal to 1.

Abstract: An exponential function on a base X raised to a power of N is performed in a processor in a manner that maximizes computing efficiency. The exponential function initially positions at a starting node in an exponential tree stored in a memory of the processor, wherein the starting node represents the value of N. A working value W is created in the memory of the processor and the working value W is initially set equal to the base X. The exponential tree is traversed in the memory of the processor from the starting node to an answer node and the working value W is updated in the memory of the processor at each node encountered during the traversal. The working value is squared in the memory of the processor when a next node is above and to the right of the current node. Otherwise, the working value is squared in the memory of the processor and a result thereof is multiplied by X in the memory of the processor when the next node is above and to the left of the current node.

Abstract: A device of the present invention is an exponential calculation device for calculating x{circumflex over ( )}(a/b) (where a and b are each an integer constant) for a given input value of x. The device includes: an input control section for outputting a value of x′, wherein x′=x when x≦A (where A is a threshold value within a variable range of x) and x′=x/2{circumflex over ( )}b when x>A; a core section for outputting a value of z′=x′{circumflex over ( )}(a/b); and an output control section for outputting a value of z, wherein z=z′ when x≦A and z=z′*2{circumflex over ( )}a when x>A.

Abstract: A square estimator computes an estimate of the square of an input number. The input number preferably is provided to combinational logic that logically manipulates the bits of the input number to generate an estimate of the square of the input number. The level of accuracy of the square generator can be programmed or predetermined by including or enabling various term generator logic units. Each term generator logic unit produces an output value that, when added to all of the other output values from the other term generators, provides an estimate of the square of the input number. Additionally, negative correction logic can also be incorporated into the square estimator for producing a negative correction value that when added to the estimate values from the various term generators, permits the square estimator to estimate the square of negative numbers as well as positive numbers.

Abstract: A bit position, M, that determines the accuracy and efficiency of the approximation is selected from an N bit binary number. The multiplicand is generated by removing the Mth bit from the binary number, shifting the bits of lower order than the Mth bit up on position, then filling the lowest order bit with a zero. The multiplier is generated by removing the Mth bit, and all lower order bits from the binary number. Booth's algorithm is then used to multiply the multiplicand and the multiplier except that the Mth bit is used instead of an assumed zero during the first step of the multiplication. In hardware, a partial Booth-encoded multiplier is used to produce and approximate square of a binary number. For an N bit number, and a selected bit in the Mth position, the partial Booth-encoded multiplier has N columns, and N−M rows and N−M booth encoders.

Abstract: A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method comprising the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segments each having a length of the predetermined operand size; multiplying a first segment value by a second segment value to generate a first product value; halving a second product value to generate a halved second product value; accumulating the first product value with the halved second product value to generate an accumulated value; and doubling the accumulated value to generate the intermediate result.

Abstract: A squaring circuit includes an input terminal that carries a k-bit input value. The k-bit input value has left m-bit and right (k−m)-bit portions representing respective left and right hand values. A left hand squaring circuit receives the left hand m-bit portion and generates a first term bit group representing a square of the left hand value. A multiplier multiplies the left hand m-bit portion and the right hand (k−m)-bit portion to generate a second term bit group representing a product of the left and right hand values. A right hand squaring circuit generates a third term bit group representing a square of the right hand value. An adder adds the second term bit group with a concatenation of the first and third term bit groups and generate the square of the k-bit input value.

Abstract: Two related extended precision operand formats provide for efficient multiply/accumulate operations in a SIMD data processing system. Each format utilizes a group of “b” bit elements in a vector register. Each of the elements provides “m” bits of precision, with b>m. The remaining b−m bits in each element accumulate overflows and carries across multiple additions and subtractions. Existing SIMD multiply-sum instructions can be used to efficiently take input operands from the first format and produce output results in the second extended precision format when b2=2b1 and m2=2m1.

Abstract: A hardware implementation solves for the value of X.sup.Y, where X and Y are real (fixed point or floating point) numbers by using the formula X.sup.Y =exp (log.sub.e (X.sup.Y))=exp(ln(X.sup.Y))=exp(Y*ln(X)). A fixed point representation of X, output from a flip-flop, is used to address a floating point data output from an ln(X) ROM lookup table. The floating point data output is output from a second flip-flop and multiplied by Y in a multiplier to yield a product. The product is output from a third flip-flop to address a fixed point data output from an exp(X) ROM lookup table. The fixed point data output is latched by and output from a third flip-flop. The fixed point data output approximates X.sup.Y, using a minimal amount of die area on the semiconductor and minimal amount of processing power. Also, the present invention can be fully pipelined, such that one calculation can be conducted every cycle and operations can occur simultaneously.

Abstract: A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders x.sub.i for every "logical" iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a "physical" iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the y.sub.i 's, which will eventually converge to the desired output.

Abstract: An optimized approach for machine computation of exponential values or functions is disclosed. The determination of the exponential values is performed using a "Big Multiply" approach and a "Big Mod" approach which involve dynamically determining the maximum size of an intermediate value required to determine an encryption key and allocating memory sufficiently large to store the maximum size intermediate value so that no additional memory allocation operations are required during the determination of the encryption keys. In addition, iterative multiplication and shift operations are performed on portions of the intermediate value in a cascade fashion to prevent spilling of the intermediate value. In one context, the computation of the exponential values is used in generating a key for exchange in a public key cryptosystem, such as the Diffie-Hellman public key cryptosystem.

Abstract: In order to enable calculation of the square of a number comprising many digits by means of an arithmetic circuit which is arranged for the parallel processing of numbers having a substantially smaller number of digits, the number to be squared is subdivided into sub-numbers having a number of digits which is compatible with the arithmetic circuit, the individual sub-numbers being successively processed. For faster processing in the case of squaring operations, the multiplier circuit provided in the arithmetic circuit includes a position shift circuit capable of performing a shift of one position to the left in the case of multiplication of given pairs of sub-numbers, which shift corresponds to a multiplication by the factor 2. As a result, squaring can be performed while using fewer technical means. A method operating on the basis thereof so as to form the square of a large number modulo another large number is also disclosed.

Abstract: A squarer generates an array of partial products. A method of squaring a representation of a number includes generating an array of partial products, combining the partial product on one side of a diagonal of the array with partial products on the other side of the diagonal to form a folded array of partial products, and combining each of at least one more than half of the partial products in the diagonal of the array with a corresponding one of the partial products in the folded array to produce a new folded array of partial products. In an alternative embodiment, the present invention is a circuit for squaring an n-bit representation of a number.

Abstract: The present invention relates to an improved method for performing modular exponentiation to a fixed base element. The method includes exponentiating a first digital input signal g by a second digital input signal R, where g is a fixed signal unique to a cryptographic system and R is a randomly generated digital signal, to compute a third digital signal g.sup.R. The exponentiating includes pre-computing and storing a plurality of values depending only upon the fixed signal g in a plurality of memory locations within a computing device and then speeding up the computation of g.sup.R using the stored values. The invented exponentiation method can substantially reduce the amount of computation required to compute the value for g.sup.R. Exponentiation methods according to embodiments of the present invention may be used in a variety of cryptographic systems, e.g., Schnorr identification scheme, Digital Signature Standard (DSS), and Diffie-Hellman key agreement scheme, etc.

Abstract: An execution processor that can carry out power calculation at high speed includes a base data register, an exponent data register, a multiplier, a multiplication input selector for selecting an input to the multiplier, first and second registers for storing a calculation result of the multiplier, a square root calculation unit, a square root calculation input selector for selecting an input to the square root calculation unit, a third register for storing a calculation result of the square root calculation unit, and a power calculation controller.

Abstract: A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The recoded portions of the second operand are used to select what factor of the first operand to use in forming the partial product terms. The partial product terms are added using carry save addition, with the least significant bits being used to form the least significant bits of the final product. The most significant bits of the final product are then formed by adding the carry save data from the partial product summations.

Abstract: A system and method for developing a digital control signal Y for setting a target module (D) according to a digital setpoint signal A, a digital feedback signal C, a difference digital signal X=A-C in an exponential relationship, such that Y=2.sup.X+1 -1. An N bit digital signal X is translated exponentially via a simple, non-complex programmable array logic unit to an expanded N+q digital bit signal providing an exponentially expanded response for the control signal Y to reset the target module D to an optimally desired setting.

Abstract: Apparatus method for calculating the remainder of B.sup.C modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating and storing the calculation result of each cycle and for outputting from a least significant bit. The initial cycle of the calculation includes a step of calculating a remainder of an m-bit input modulo n and a step of holding the result of the calculation. The normal cycle of the calculation includes a step of doubling the result of the calculation, and calculating a remainder of the doubled result of the calculation modulo n and a step of holding the next result of the calculation and for repeatedly executing the normal cycle m-2 times after the first normal cycle. The calculation result of each previous normal cycle is used in each successive normal cycle.