Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to (?B) (2N), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders (49, 51, 53) that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

Abstract: This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier capable of processing digital signals of communication systems such as a timing recovery circuit, a carrier recovery circuit, and a FIR filter, etc. This invention derives a binary compensation vector to compensate for the error caused by the reduction of area without any hardware overhead, and implements the compensation structure of an Array and a Booth multiplier to reduce hardware complexity.

Abstract: A Booth encoding circuit includes a plurality of cells (202a-202d), in which at least one of the cells (202c) includes a plurality of inputs. The cell also includes a first plurality of transistors (203) receiving at least one input and forming a NAND logic stage. The cell further includes a second plurality of transistors (211) receiving at least one input and forming an OR logic stage. The cell also includes a first output inverter (222) connected to at least one of the second plurality of transistors (211), and a first switching (224) connected to at least one of the first plurality of transistors (203). The cell further includes a second switching (226) connected to the first output inverter (222), and a second output inverter (228) connected to the first switching (224) and the second switching (226).

Abstract: A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m/k digit data D (=Dm/k−1Dm/k−2 . . . Di . . . DiDo). A partial product calculator converts each of the digits Di of the number Y converted by the data converter into a combination of the coefficients of a fundamental multiple, multiplies the combination by the number X, and outputs the product as a redundant binary partial product. A redundant binary adder sums the partial products for all of the digits of the converted number Y. A redundant binary (RB)-normal binary (NB) converter converts the redundant binary sum into a normal binary number and outputs the converted normal binary sum as the product of the two numbers. Therefore, even when the radix extends, the burden upon hardware can be minimized.

Abstract: An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with “0”. A Booth decoder divides the multiplier into a plurality of partial bit rows. A plurality of partial product generating circuits, each of which is arranged corresponding to corresponding one of the partial bit rows divided by the Booth decoder, each generates a partial product of a multiplicand and each corresponding one of the partial bit rows. In the case of performing the multiplication operation with low accuracy, the partial product generating circuits generating the partial products corresponding to the partial bit row of the least significant half the bits, generate partial products of each corresponding bit row and the least significant half the bits of the multiplicand, and generate partial products of each corresponding bit row and the most significant half the bits of the multiplicand.

Abstract: The present invention provides an apparatus for booth decoding which stores the most significant bit of the lower half of the number used as the key for booth decoding. By using this stored bit to determine the rightmost booth group corresponding to the upper half of the key, booth decoding may be accomplished more quickly using an apparatus that is simpler and smaller than prior art assemblies.

Abstract: A system of and method for extended Booth encoding of two binary numbers, K and L. A stage of the encoder receives K[2n+1], K[2n], L[2n+1], and C[n−1], N−1≧n≧0, with N being the length of L, and it being assumed L[2n]=0, and forms C[n], S[n], M1[n], and M2[n] according to the following equations: C[n]=K[2n+1]|L[2n+1], S[n]=K[2n+1]{circumflex over ( )}L[2n+1], M1[n]=K[2n]{circumflex over ( )}C[n−1], M2[n]=(S[n]&/K[2n]&/C[n−1])|(/S[n]&K[2n]&C[n−1]), where | refers to the logical OR function, {circumflex over ( )} to the exclusive OR function, & to the logical AND function, and/to the logical inversion function.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: In the multiplier, a partial product circuit generates a partial product based on a multiplicand operand and outputs of a Booth recoder circuit, which operates on a multiplier operand. The partial product circuit ANDs the multiplicand with a zero Booth recoded output, which indicates whether to zero out the multiplicand. An enable circuit selectively enables the multiplier circuit, and more particularly, disables the multiplier circuit by making the zero Booth recoded output indicate to zero out the multiplicand.

Abstract: In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

Abstract: A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While recoding and partial product generation is occurring, a determination is made in parallel whether or not a sign extension adjustment term must be created. When needed, a value equal to N (−B) (2N), where N is equal to a bit width of the multiplicand (A), is formed in parallel with the recoding and partial product generation. The sign extension adjustment term is coupled to a plurality of carry save adders (49, 51, 53) that compress a plurality of partial products to a sum term and a carry term. A final add stage combines the sum term and carry term to provide a product with correct sign extension.

Abstract: A Booth encoder and partial products generator circuit may be provided. The Booth encoder circuit may include a plurality of transistors to receive a plurality of multiplier bits and complements of the plurality of multiplier bits. The Booth encoder circuit may also include a plurality of logic gates (or circuits) coupled to ones of the plurality of transistors to output Booth encoded signals. The partial products generator circuit may include a first multiplexing device having a plurality of first transistors to receive the Booth encoded signals and to provide a first partial products output, and a second multiplexing device having a plurality of second transistors to receive the Booth encoded signals and to provide a second partial products output. The second multiplexing device further to receive multiplexed data from the first multiplexing device when providing the second partial products output.

Abstract: A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. The addition of the rows of the scaled multiplicand input data is performed with adders with two data inputs (plus carryin). These adders are cascaded such that normally invalid data ripples through the adder before the final result is achieved. By controlling the time power is applied to the adders most of the intermediate states are eliminated.

Abstract: A new partial product bit generator is used to generate a partial product bit PPji. In some embodiments, the partial product bit generator generates the partial product bit PPji from intermediate signals that are able to be generated concurrently, for example in two levels of combinatorial logic. The partial product bit PPji is then able to be generated from the intermediate signal, for example in only one level of combinatorial logic. In such embodiments, a long series of combinatorial logic operations is not required.

Abstract: A method and apparatus for improving the efficiency of hardware-based binary multiplication. By using radix-32 and radix-256 multipliers where each radix-32 digit is represented by two radix-7 digits and each radix-256 digit is represented by three radix-11 digits, the digit magnitudes are in power of two, which simplifies the implementation of the partial product generation. The partial products depending on multiples of the radices 7 or 11 can be separately accumulated, with multiplication by the radix a pre- or post-computation option.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: A low power high speed multiply/accumulator (100) utilizes a modified Booth's recoder (120) to identify situations to power down the partial product array (130). The modified Booth's recoder (120) is responsive to a NOP signal (116) and a add/subtract signal (118) that result from instruction decode. The partial product array (130) can be partially or fully shut-down to conserve power in response to the recoder (120) detecting certain operands and NOP instructions. It also allows implementation a multiply-and-subtract instruction. The output of the partial product array (130) is registered in a high order product register (142) and a low order product register (144). The low order product register (144) accumulates partial products for multiply-and-accumulate and multiply-and-subtract instructions.

Abstract: An embodiment of the present invention is a mixed length encoding unit. The mixed length may be a 12/16 bits (12/16-b) encoding algorithm within a multiply-accumulate (MAC). The mixed length encoding unit includes 16-b Booth encoder adapted to produce eight partial product vectors from sixteen bits of data. The 16-b Booth encoder is coupled to a four stage Wallace Tree. During a first cycle of the invention, a multiplex system directs the eight partial products and an accumulation vector to a four stage Wallace Tree. During subsequent cycles, the multiplex system directs six partial product vectors, an accumulation vector, one carry-feedback input vector, and one sum-feedback input vector to the four stage Wallace Tree.

Abstract: An energy saving multiplication device and its method is disclosed. The multiplication device comprises a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Abstract: An arithmetic unit for multiplying a first quantity X by a second quantity Y, said arithmetic unit comprising a Booth coder having a plurality of inputs for receiving a plurality bits of the second quantity and a plurality of outputs for providing Booth coded outputs; and circuitry means connected to at least one of said inputs and said outputs for modifying at least one output of the coder.

Abstract: An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. As disclosed, the selector selects and passes either a standard partial product term or an inverse thereof to the compressor, based on whether signed or unsigned multiplication is being performed, respectively, while the compressor compresses the received partial product terms into a pair of partial product terms.

Abstract: The operands of an N×M bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less significant submultiples is assigned a positive sign. The product of each submultiple pair is sign extended to the width of the product (N+M), and the accumulation of these sign extended submultiple products provides the product of the original twos complement operands, in twos complement form.

Abstract: An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two.

Abstract: A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the multiplier data has n bits, where n denotes a predetermined even number. A 1-bit sign extension of the multiplicand data is executed to generate data having n+1 bits. In the multiplying device, n/2 partial product data pieces are generated on the basis of the data having n+1 bits and the multiplier data according to second-order Booth's algorithm. Each of the n/2 partial product data pieces has n+1 bits. There is a plurality of adders connected and arranged in a tree configuration. The adders operate for adding the n/2 partial product data pieces. The adders include a final-stage adder which outputs multiplication result data representing a product of the multiplicand data and the multiplier data. The multiplication result data has 2n−1 bits.

Abstract: A booth decoder decodes A or −A according to a booth algorithm, depending upon whether A×B or −A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products of A×B or −A×B following to a result of the decoding, and sequentially adds these partial products. Data C, or data made by inverting bits of C, is input to the partial multiplier/partial adder circuit 30, depending upon whether C should be added or −C should be added to the result of multiplication. Also the data C or data made by inverting bits of C are sequentially added by the partial multiplier/partial adder circuit 30. A final adder circuit 50 executes final addition of these partial products, and adds 1 when −C should be added. Thus, Z=±(A×B)±C (the order of signs being variable) can be calculated.

Abstract: A combination has a booth recoder with at least three input lines; two input lines corresponding to two bits of a multiplier and one input line being an increment select line. In one embodiment, signals representing the two bits of the multiplier are provided on the two input lines corresponding to the two bits. A controller selectively asserts a increment select signal on an increment select line, thereby incrementing the multiplier. Therefore, the present invention has the advantage of incrementing a multiplier while performing booth multiplication without requiring an additional adder for incrementing.

Abstract: An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of multiplication techniques, such as bit-pair recoding or the Booth algorithm, to perform multiplication and negate multiplication operations. The multiplier circuit uses an encoder circuit to produce encoded multiplier strings in accordance with such multiplication techniques. The multiplier circuit reorders bits of such encoded multiplier strings to cause a binary multiplier circuit to generate the negate product -B*C rather than the product B*C. The reordering can be accomplished in any manner, such as by a bus coupling the encoder circuit to the binary multiplier circuit. The encoder circuit can be coupled to the binary multiplier circuit using two buses and a multiplexor circuit.

Abstract: A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm.

Abstract: A circuit that performs the function of a bank of multipliers while reducing hardware costs includes shared term generator that generates a set of shared terms in response to an input value. The circuit further includes a set of combining circuits each of which generates a result term by combining one or more of the shared terms so that the result term equals the input value multiplied by a corresponding data value. The circuit generates the share terms once and then reuses the shared terms in differing combining circuits as needed thereby eliminating duplication of terms and associated implementation hardware.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. When a 3X coefficient of the multiplicand input data is to be generated, a -1 coefficient is output by the encoder requiring the 3X coefficient, and a 1 is added to the sum of the next most significant bit pair.

Abstract: A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

Abstract: A multiplier is configured to multiply two signed values to generate sum and carry bit groups representing, in redundant form, a product of the first and second signed values. A sign determining circuit is configured generate a sign bit representing a sign of the product. An extension unit is configured to receive the sum most significant bit, the sign bit, and the carry most significant bit. The extension output terminal configured to carry a replacement bit and an extension bit, the replacement bit having a same weight as the sum most significant bit. The extension unit is structured such that the replacement bit has one binary state only if the sum most significant bit and the carry most significant bit are different. The extension unit is structured such that the extension bit has one binary state only if the sign bit is a binary zero and the sum most significant bit and the carry most significant bit are the same.

Abstract: The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product.

Abstract: A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial product selector groups, each partial product selector group includes a plurality of partial product selector circuits. Each partial product selector circuit receives a portion of a multiplicand as an input and outputs a partial product. The circuit also includes a plurality of Booth encoders. At least one of the Booth encoders is coupled to each partial product selector group. Each Booth encoder receives as an input a portion of a wide multiplier and outputs a Booth encoded value to at least a portion of a partial product selector group. The circuit further includes an override circuit coupled to one or more of the partial product selector circuits.

Abstract: An improved parallel-serial multiplier and accumulator for multiplying a digital multiplicand and a multiplier resulting in a product that is added to an accumulator input. The parallel-serial multiplier and accumulator includes a parallel-serial multiplier and a digit serial adder. The parallel-serial multiplier includes a recoder for receiving the digital multiplier and outputting an ordered sequence of recoded words, a partial product generator for generating partial products that are dependent upon the digital multiplicand and upon each of the ordered sequence of recoded words, and an adder for adding the partial products to provide the product. The adder outputs a digit serial word that contains the least significant bits of an intermediate sum of the partial products as the partial products are being added. The digit serial adder includes a carry save adder that receives the product and the accumulator input to produce the output sum.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.

Abstract: A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The recoded portions of the second operand are used to select what factor of the first operand to use in forming the partial product terms. The partial product terms are added using carry save addition, with the least significant bits being used to form the least significant bits of the final product. The most significant bits of the final product are then formed by adding the carry save data from the partial product summations.

Abstract: In a modified Booth's algorithm only one shift unit is required for multiplication of the partial products. This is based on the known coding prescriptions of the Booth's algorithm, which respectively determines from 3 bits of the multiplier how the partial products are to be produced. From the respective 3 bits of the multiplier of the current iteration and of the preceding iteration, it is determined whether the partial product used for the next iteration has to be multiplied by 1/2, 1/4 or 1/8. For this purpose, a coding table and a multiplier that operates according to this principle are provided.

Abstract: The present invention provides a data processing circuit and method for performing arithmetic processing on data signals input to the circuit, comprising: a plurality of input terminals for receiving a plurality of data signals to be processed; a plurality of interconnected arithmetic processing units, one corresponding to each input terminal, for processing the data signals received at the corresponding input terminal; and a selector for routing the data signals at said input terminals to the corresponding arithmetic processing units in a first mode of operation, or for routing a selected one of said data signals to said plurality of arithmetic processing units in a second mode of operation; whereby, in said first mode of operation, data signals arriving at said input terminals are processed in parallel by said corresponding arithmetic processing units, and, in said second mode of operation, at any point in time, one of said data signals is processed by said plurality of arithmetic processing units.