Abstract: A device is provided. In some examples, the device includes a division logic circuit having input lines including a first least significant input line. The division logic circuit further includes temporary output lines including a second least significant line. The device also includes a first multiplexer having a first data input coupled to the first least significant input line. The first multiplexer further includes a second data input coupled to the second least significant line.

Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells.

Abstract: Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first subset of bytes is read, and an associated first remainder by division is calculated and stored in the memory location from which the subset was read. A second subset of bytes is read, and an associated second remainder by division is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third and fourth subset of bytes is read and associated remainders are calculated.

Abstract: A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.

Abstract: A divider circuit includes: a register which is configured of an even number of bits and in which a dividend data is stored. A shift operation section is configured to acquire a data stored in an upper bit portion of the register when the even number of bits of the register is equally divided to the upper bit portion and a lower bit portion, as a quotient data when the dividend data is divided by a maximum of a divisor data which can be expressed by a half of the even number of bits of the register.

Abstract: A system, method, and computer program product for dividing two binary numbers. The divider implements a fixed point division function using a floating point normalization architecture to yield the closest initial quotient approximation. The divider normalizes the input dividend and divisor to a range of [0.5, 1.0) by scaling each by necessary factors of two. The normalized inputs are submitted to a divider core that may be optimized for dividing inputs of such limited ranges. The divider core output is then rescaled by an appropriate factor of two, appropriately signed, and loaded into saturating registers for output in various formats. The divider core progressively outputs quotient bits in decreasing order of significance until a predetermined level of precision is reached, typically fewer bits than in a complete quotient, for faster output. One embodiment generates the six most significant quotient bits in one clock cycle.

Abstract: The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.

Abstract: A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2n(1+2p). An interim result, which is equal to a reciprocal of 1+2p multiplied by the dividend, is calculated. The interim result is divided by 2n to produce a result of the division operation.

Abstract: A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor value and multiplying the reciprocal value by the dividend value to obtain a reciprocal product, the reciprocal product having an integer part. The method also includes computing an intermediate remainder value by computing a product of the integer part and the divisor value, and subtracting the resulting product from the dividend value and determining the quotient value based upon the intermediate remainder value.

Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.

Abstract: A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2n?1 and n=2), and outputs from a second output circuit, a first bit sequence that is the upper 4 bits of the 8-bit quotient, and a second bit sequence in which i sets of lower 4 bits of the 8-bit quotient are arranged. A quotient addition circuit outputs, as a quotient of 1695 divided by 3, the sum of values each including the first bit sequence at upper bits and the second bit sequence at lower bits.

Abstract: A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2? to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.

Abstract: An integrated circuit comprises divider circuitry configured to perform a division operation. The divider circuitry may be part of an arithmetic logic unit or other computational unit of a microprocessor, digital signal processor, or other type of processor. The divider circuitry iteratively determines bits of a quotient over multiple stages of computation. In determining the quotient in one embodiment, the divider circuitry is configured to estimate a partial remainder for a given one of the stages and to predict one or more of the quotient bits for one or more subsequent stages based on the estimated partial remainder so as to allow one or more computations to be skipped for said one or more subsequent stages, thereby reducing power consumption. The integrated circuit may be incorporated in a computer, a mobile telephone, a storage device or other type of processing device.

Abstract: A modulo N calculating method for an M1*M2-bit binary integer, wherein N, M1 and M2 are integers, includes the steps of dividing the M1*M2-bit binary integer into M1 bits and performing AND operation on each M1 bits and a specific binary integer; and changing a value of an output register depending on the AND operation result and storing the value thereto. A modulo N calculating apparatus includes an input unit for receiving an M1*M2-bit binary integer, wherein N, M1 and M2 are integers; and an AND operation unit for performing AND operation on the M1*M2-bit binary integer and a specific binary integer. Furthermore, when the M1 and the N may be 4 and 3, respectively, the specific binary value may be 1010 or 0101.

Abstract: Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.

Abstract: An integer division circuit with allowable error is described, what a signal processing apparatus includes a pointer, a first left shifter, a second left shifter, a subtractor, a multiplier, and a right shifter. The pointer searches for a most significant non-zero bit of a divisor and outputs a most significant byte value. The first left shifter performs a shift operation according to the most significant byte value, so as to generate a first exponential coefficient. The second left shifter performs a shift operation according to the most significant byte value, so as to generate a second exponential coefficient. The subtractor calculates a multiplier factor according to the divisor, the first exponential coefficient, and the second exponential coefficient and outputs the multiplier factor to the multiplier. The multiplier multiplies an input value with the multiplier factor and outputs a result to the right shifter. The right shifter outputs a calculation result.

Abstract: A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2(n+1).

Abstract: A remainder by division of a sequence of bytes interpreted as a first number by a second number is calculated. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.

Abstract: Division can be performed in a programmable integrated circuit device by computing a relatively small number of bits of the inverse of the divisor, and then programming multipliers in a specialized processing block of the device to perform multiplication of the dividend and the inverted divisor. The specialized processing block is constructed to be able to be programmed to support such asymmetric multiplication by providing programmable shifting of partial products, so that the partial products can be shifted one number of bits for symmetric multiplication and a different number of bits for asymmetric multiplication. The process is performed recursively, by chaining a plurality of the specialized processing blocks, so that the result converges notwithstanding the relatively low precision of the inverted divisor.

Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: Methods, computer systems, and computer program products for calculating a remainder by division of a sequence of bytes interpreted as a first number by a second number are provided. A first remainder by division associated with a first subset of the sequence of bytes is calculated with a first processor. A second remainder by division associated with a second subset of the sequence of bytes is calculated with a second processor. The calculating of the second remainder by division may occur at least partially during the calculating of the first remainder by division. A third remainder by division is calculated based on the calculating of the first remainder by division and the calculating of the second remainder by division.

Abstract: A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system.

Abstract: A method, arithmetic divider unit, and system are disclosed for dividing a dividend DZM . . . Z0 having a most significant bit ZM and a plurality of less significant bits ZM?1 through Z0 by a divisor RZN . . . Z0 having a most significant bit ZN and a plurality of less significant bits ZN?1 through Z0. The method, arithmetic divisor unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN+1, divide the dividend DZM . . . Z0 by the first partial divisor RZN+1 to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN?1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

Abstract: The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, an?1, and n?1 fractional bits, an?2, an?3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ? i = 0 n - 2 ? - a i ? 2 i - n + 1 .

Abstract: A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.

Abstract: The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q.

Abstract: A method divides a number N1 by a number which can be written in the form 2n/k, n and k being whole numbers, and obtains a result N2. The result N2 is calculated by adding terms N1*Ki/2n-i for i ranging from 0 to N, the terms Ki being the constituent bits K0, K1, K2, . . . KN-1 of the number k expressed in binary. The method can be applied particularly to the production of a calibration circuit for calibrating a clock signal in a UHF transponder.

Abstract: A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floating point processor. Remainders are calculated using the floating point numbers divided, the unit of least precision, and the unit of least precision plus one to determine where the infinitely precise result is with respect to the digital representation of the estimated quotient. Evaluating these remainders and the initial floating point numbers and comparing their signs and magnitudes leads to a selection of one of three choices as the most accurate representation of the infinitely precise result as calculated in the inventive rounding method: the intermediate result minus the unit of least precision; the intermediate divide result; or the intermediate divide result plus the unit of least precision.

Abstract: The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: A device for calculating a result or an integer multiple of the result of a division of a numerator by a denominator includes a unit for providing a factor which is selected such that a product of the factor and the denominator is greater than the result. The device further includes a unit for modularly reducing a first product of the numerator and the factor using a modulus equaling a sum of a second product of the denominator and the factor and of an integer to obtain an auxiliary quantity having the result. A unit is used to extract the result or the integer multiple of the result from the auxiliary quantity. A division is thus reduced to a modular reduction and an extraction which is uncomplicated as far as calculation is concerned so that, in particular in long-number division tasks, the speed on the one hand and the safety on the other hand are increased.

Abstract: The invention provides a method, arithmetic divider unit, and system for dividing a dividend DZm . . . Z0 having a most significant bit and a plurality of less significant bits by a divisor having a most significant bit ZN and a plurality of less significant bits ZN?1 through Z0. The method, arithmetic divider unit, and system round the divisor to the next significant bit greater than the divisor's most significant bit ZN to produce a first partial divisor RZN, divide the dividend DZm . . . Z0 by the first partial divisor RZN to produce a first partial quotient QN, calculate one or more additional partial quotients based on one or more divisor bits selected from the plurality of divisor bits ZN?1 through Z0, and add the first partial quotient QN and one or more additional partial quotients to produce an estimated final quotient.

Abstract: A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2(n+1).

Abstract: A fast division method which uses a smaller quotient digit set of {?1, 1} than {?1, 0, 1} that is used by known algorithms, therefore accelerates the speed of calculation. Partial remainders can be computed with the signals of remainders decided independently and in parallel. By taking the absolute values of the remainders, we can successively subtract the remainders without the need of knowing the signs of remainders, while signs of the remainders can be decided in parallel and independently at the same time. The algorithm adopts non-restoring division operation and CSA type of operation for fast subtraction. The algorithm is also an on-line algorithm that facilitates highly pipelined operation while it is much simpler than the existing on-line algorithms.

Abstract: According to an aspect of the present invention, a quotient of a dividend divided by a divisor may be determined after reducing the dividend, divisor, and the remainder by using operations such as add, subtract, multiply, shift, AND which may result in reduced processor cycles (time).

Abstract: A data processing apparatus uses numeric processing. A corrective mechanism enables a method for performing accurate integer divisions to be derived from an approximate division method which does not, of itself, always produce an accurate result but for which the range of errors is known. By applying the corrective mechanism to a suitable approximate division method, a numeric processing mechanism performs the integer division operation efficiently. An approximate division method that uses rapid operations for fast integer division, and thus has a small possible range of errors, is used to enable the correction method to be completed rapidly.

Abstract: A calculation speed of division carried out in a computer is increased. Partitioning means partitions a dividend y that is a 32-bit digital datum at every 8 bits from the least significant bit to generate four bit blocks y(1) to y(4). For the respective bit blocks, table reference means finds solutions z(1) to z(4) obtained by dividing, by a divisor x, values expressed by replacing the bits other than the bits in each bit block with 0, while referring to tables (1) to (4) stored in storage means. Addition means adds all the solutions z(1) to z(4) to find the solution z.

Abstract: A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterative operation type. The pipelined divider has a delay time of 3 cycles in a single precision, and can reduce a chip size by about ? in comparison to the existing pipelined divider.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: A calculation circuit for the division of a fixed-point input signal comprising a sequence of digital data values having a width of n bits by an adjustable division factor 2a for the purpose of generating a divided fixed-point output signal, having a signal input (2) for applying the data value sequence of the fixed-point input signal, a first addition circuit (6), which adds the digital data value present at the signal input (2) to a data value buffer-stored in a register (33) to form a digital first summation data value having a width of max (n, a+1)+1 bits, a shift circuit (11) which shifts the first summation data value present by a data bits toward the right, with the result that the max (n, a+1)?a+1 more significant data bits of the first summation data value are output at an output of the shift circuit (11), a logic circuit (16), which, as a function of the sign of the first summation data value, logically ANDs the a less significant data bits of the first summation data value with a logic combination

Abstract: A microprocessor (10) comprises a compiler (4), which, for a source program including an integer division q=int(a÷b)(int( ) is a function discarding figures below decimal point in parentheses) for dividing integer a, expressed in N bits, by integer constant b, causes a computer to execute a first process for calculating mb=int(m÷b) (where m=2N), and a second process for generating an object code, which stores the mb in a first register (24), calculates qx=int(a×mb÷m), calculates rx=a?qx×b, set a quotient q to q=qx when rx<b, or q=qx+1 when rx>=b; and a microprocessor having an arithmetic circuit (11), which comprises the first register, a multiplier (14), and an adder-subtractor (16), and which executes the object code generated by the compiler.

Abstract: One embodiment of the present invention provides a system that performs a carry-save division operation that divides a numerator, N, by a denominator, D, to produce an approximation of the quotient, Q=N/D. The system approximates Q by iteratively selecting an operation to perform based on higher order bits of a remainder, r, and then performing the operation, wherein the operation can include, subtracting D from r and adding a coefficient c to a quotient calculated thus far q, or adding D to r and subtracting c from q. These subtraction and addition operations maintain r and q in carry-save form, which eliminates the need for carry propagation and thereby speeds up the division operation. Furthermore, the selection logic is simpler than previous SRT division implementations, which provides another important speed up.

Abstract: In accordance with the preferred embodiment of the present invention a gain (A) is determined and utilized to cyclically converge upon a quotient (Q). More particularly, once A is determined, an estimate of QN is multiplied by Y to estimate {circumflex over (X)}N, where Q=X/Y. The value of {circumflex over (X)}N is then subtracted from X to determine an error (eN), which is multiplied by A. The value of AeN(n) is added to AeN(n−1) to produce an estimate of Q. Once convergence has occurred, the value for Q is output from the circuitry.

Abstract: Values X and N of n bits and a parameter t are input, then Y=X2−t mod N is calculated, then an extended binary GCD algorithm is executed for Y to obtain S=y−12k mod N and k, and R=S2−(k+t−2n) is calculated for S, thereby obtaining a Montgomery inverse R=X−I22n mod N of X on a residue class ring Z/NZ.

Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: Apparatus for determining a remainder of a modulo division of a binary number made up of a string of bits, including a first plurality of substantially similar cells coupled in a linear sequence, the first plurality of cells including at least a first cell and a last cell. Each cell of the first plurality includes a second plurality of binary input terminals, the input terminals of the first cell being coupled to receive a pre-determined input, and a second plurality of binary output terminals, each coupled, except for the output terminals of the last cell, to a respective one of the input terminals of a subsequent cell in the sequence. Each cell of the first plurality further includes a control input terminal, coupled to receive one of the bits in the string corresponding to a position of the cell in the sequence. The remainder is generated at the output terminals of the last cell in the sequence.

Abstract: Devices and methods are provided for estimating a high-precision quotient using a smaller-than-conventional lookup table. The devices include a numerator register feeding a numerator value (as a succession of bits or words) into a forward signal path. The forward path includes a partial quotient generator, an accumulator, and a latch. The devices further include a feedback signal path emerging from the latch output, undergoing division by bit-shifting, and terminating as an input to the accumulator. A multiple divide implementation for use in a particular servo control system is also presented.

Abstract: Quotient digit selection logic using a three-bit carry propagate adder is presented. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a four bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fourth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit.