Abstract: A method and apparatus for calculating a quotient from a dividend and a divisor, wherein the divisor can be represented as (2N+2M) where N is greater than M, and wherein the dividend comprises an X-bit binary number divisible by the divisor without a remainder. The values of N and M for the dividend are determined such that the divisor is equal to the value (2N+2M). The M-th through the (N−1)-th bits of the dividend are selected as lower order bits of the quotient. The (N−1)-th and the (2N−M−1)-th bits of the dividend are examined. If the (N−1)-th bit of the dividend is “1” and if the (2N−M−1)-th bit of the dividend is “0”, then one is subtracted from a value represented by the (2N−M)-th through the (X−1)-th bits of the dividend to obtain a result as higher order bits of the quotient. Otherwise, the (2N−M)-th through the (X−1)-th bits of the dividend are selected as higher order bits of the quotient.

Abstract: The present invention provides apparatus, methods, and computer program products for non-iterative division and non-iterative reciprocal generation. In one embodiment, the present invention uses a logic network that determines the bits of the quotient of a divisor and dividend by using a non-iterative, (i.e., non trial and error), method. Further, in another embodiment, the present invention may determine the reciprocal of a number M by separating the number M into at least two numbers X, Y . . . Z so that M=X+Y+ . . . +Z. The reciprocal of M is computed according to an equation 1/M=F(X,Y . . . Z) or an approximation 1/M≈G(X,Y . . . Z), where the approximation gives the correct value of the inverse of M to a predetermined accuracy. In some embodiments, the apparatus uses an equation that exactly describes the reciprocal or instead, it may include one or more memories for storing look-up tables containing pre-calculated parts of the equation.

Abstract: The present invention provides a byte-switching arithmetic unit comprising at least three stages, each of which has a plurality of two-input selectors operable in a predetermined minimum bit width unit, the byte-switching arithmetic unit having two inputs of a predetermined input bit width, wherein a first stage has a first number of first stage two-input selectors where the first number corresponds to a quotient of a division to the predetermined input bit width by the predetermined minimum bit width unit, wherein a second stage has a second number of second stage two-input selectors where the second number corresponds to a half of the first number so that the second stage two-input selectors receive a half of outputs from the first stage two-input selectors, and wherein a third stage has a third number of third stage two-input selectors where the third number also corresponds to the half of the first number so that the third stage two-input selectors receive both a half of outputs from the second stage two-

Abstract: Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond a current most significant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Abstract: A method for dividing a dividend by a divisor and finding a dividing quotient and a dividing remainder is provided. The dividend has a low byte part and a high byte part and the divisor has a low byte part and a maximum digital value whose most significant bit is "1" and other bits are "0". At first, the low byte part of the dividend is divided by the divisor to obtain a low-byte quotient and a low-byte remainder. Secondly, the high byte part of the dividend is divided by the divisor to obtain a high-byte quotient and a high-byte remainder. Then the high-byte remainder is shift-divided by the divisor to update the low-byte quotient, the high-byte quotient, and the high-byte remainder. Then the high-byte remainder is added to the low-byte remainder to obtain a sum. The sum is divided by the divisor to obtain a quotient and the dividing remainder. Finally, the quotient is added to the low-byte quotient to find the dividing quotient.

Abstract: A method and apparatus for fast unsigned integral division, utilized in compositing images, sounds or other data, is provided. Compositing utilizes a division step. The divisor is the value of two to the Nth power minus one. The division comprises the steps of making a copy of the first number, thus producing a third number. The first number is shifted to the right by N. The third number is biased, and is then added to the first number. The resultant number is shifted right by N. This process results in a division by 2.sup.N -1, with short latency instructions, instead of the long latency instructions usually used for division operations.