Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

Abstract: The present invention is related to a decision-support system and method for providing with a score an object represented by a target item from a multidimensional space, said score being representative of the probability that the object satisfies a given binary property. The method and/or decision support-system may be performed in a computer environment comprising processing means connected to memory means.

Abstract: Methods and apparatus provide for a carry generation tree for a carry look-ahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages receives binary outputs from a series of binary adders; a last of the stages produces a carry out signal representing the carry state of the series of binary adders; and any operator in a given stage does not receive signals from more than one operator in a preceding stage.

Abstract: An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.

Abstract: An adder, a processor (such as a microprocessor or digital signal processor), and methods of adding in such adder or processor. In one embodiment, the adder includes: (1) a first and second units in a first logic layer, the first unit receiving first and second addend and augend bits and generating therefrom a first single group-carry-generate bit and first and second carry-propagate bits, the second unit receiving third and fourth addend and augend bits and generating therefrom a second single group-carry-generate bit and third and fourth carry-propagate bits and (2) a third unit in a second logic layer, coupled to the first and second units, that receives the first and second single group-carry-generate bits and the first, second, third and fourth carry-propagate bits and generates therefrom resulting group-carry-generate and group-carry-propagate bits.

Abstract: A double incrementing adder includes an AND gate configured to receive bits of the two input values of a common weight (“first weight”). The AND gate has an output terminal configured to carry the AND'ed bit. A three input XOR gate is configured to receive bits of the two input values of a common weight (“second weight”) one bit more significant than the first weight. The three input XOR gate is configured to XOR these values with the AND'ed bit to generate a three input XOR'ed bit.

Abstract: An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.