Abstract: Provided are a method, an apparatus, and a computer program stored in a computer readable medium for conducting an arithmetic operation efficiently in a database management server.

Abstract: The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.

Abstract: Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.

Abstract: A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.

Abstract: Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first input sections, a first wave transmission medium having a continuous film including a magnetic body connected to the first input sections, and a first wave detector outputting a result of computation by spin waves induced in the first wave transmission medium by the signals corresponding to the two bit values. The threshold wave computing unit includes a plurality of third input sections, a third wave transmission medium having a continuous film including a magnetic body connected to the third input sections, and a third wave detector a result of computation by spin waves induced in the third wave transmission medium.

Abstract: A carry look-ahead adder includes an input stage to produce generate bits and propagate bits from input signals. An output stage produces output sums exclusively from the generate bits, the propagate bits and carry in bits.

Abstract: A carry look-ahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry look-ahead circuit includes a circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output.

Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.

Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Abstract: Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh are arranged in row-major order. Values are accumulated toward the center of the mesh and partial results are propagated outward from the center of the mesh to complete the cyclic segmented prefix operation. This embodiment has been shown to be time-optimal. In another embodiment of the present invention, the prefix nodes are arranged such that the prefix node corresponding to the last element in the array is located at the center of the array. This alternative embodiment is not only time-optimal when accounting for wire-lengths (and therefore propagation delays), but it is also asympotically optimal in terms of minimizing the number of segmented prefix operators.

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: An adder that can detect the generation of overflow at a high speed. Carry signal c14 from the 15th digit to the 16th digit in the result of addition from the 1st digit to the 16th digit of the input data is generated on the basis of bit signals (a0-a15, b0-b15) for the portion from the 1st digit to the 15th digit of the input data, and of carry signal CIN input to the 1st digit, and it is output from CLA 204. Then, carry signal c15 from the 16th digit to the 17th digit is generated based on said generated carry signal c14 and bit signals (a15, b15) of the 16th digit of the input data, and this is output from CIA 205. Exclusive-NOR circuit 206 then operates on said carry signals c14 and c15, and overflow detection signal OVF16 is generated.

Abstract: An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third output operand. In a preparation mode, the three output operands of the apparatus have the same value. The apparatus and method may preferably be employed in a three-operands adder as an interface between a dual-rail three-bits half adder and a sum-carry stage of a two-bits full adder so to achieve the same level of security as a full implementation of the three-operands adder in dual-rail technology, despite the two-bits full adder being implemented in single-rail technology.

Abstract: A carry look-ahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry look-ahead circuit includes a circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output.

Abstract: An address generating circuit includes a first carry look-ahead circuit for performing an operation using an inputted first carry and a first address and outputting a first output address and a first output carry respectively as a first operation result, a second carry look-ahead circuit for performing an operation using a carry fixed to 0 and a second address and outputting a second output address and a second output carry respectively as a second operation result, a third carry look-ahead circuit for performing an operation using a carry fixed to 1 and the second address and outputting a third output address and a third output carry respectively as a third operation result, and a first select circuit for selecting either of the second and third operation results based on the first output carry and outputting the selected operation result.

Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

Abstract: A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.

Abstract: Disclosed is a digital circuit which comprises input signals A[n?1:0], SH[log2n?1:0], and DAT[n?1:0], a barrel shifter for outputting data B[n?1:0] obtained by shifting the signal DAT by the bits of the signal SH, a group G·P·SUM computation stage for dividing each of the digits of the input signals A and B into groups of m bits, and computing Gs, Ps, and addition results SUM0 when carry inputs are high and addition results SUM1 when the carry inputs are low, a carry computation circuit for computing a carry for each of the groups, and a SUM selection stage for selecting a SUM0 or a SUM1 computed for each of the groups according to each carry output by the carry computation circuit.

Abstract: An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same significance, a carry digit propagating signal and diagonal generation signals. The adder further including: an estimating circuit performing a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complement of the corresponding bit of significance of the first number; a second computing circuit, elaborating a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block applying to each estimated value of bit of significance k of the sum, k+1 corrections using the correcting signals, and delivering n bits of the sum.

Abstract: A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage with static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

Abstract: A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates 101, 102, 2-input NOR gate 103, AND-NOR type composite gates 201, 202, OR-NAND type composite gate 251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

Abstract: In a system having stored operands in various locations, addition is performed without having to store the operands in preparation for an add operation. Bitwise propagate and generate terms are efficiently created to speed up additions in the system. Combinational logic circuitry has a plurality of inputs and provides a first operand and a second operand during a first phase of a cycle of a clock signal. A carry look-ahead adder (CLA) has first and second inputs directly connected to the combinational logic circuitry for respectively receiving the first operand and the second operand during the first phase of the cycle of the clock signal and creates generate bits and propagate bits prior to beginning of a second phase of the cycle of the clock signal. The adder uses the generate bits and propagate bits to provide a sum of the first operand and the second operand.

Abstract: An adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. The circuit has the capability to feed back the result of the processing to itself in order to process one input number together with the result of a previous processing instead of the second binary number.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which SHA1 multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. As described in this application, the invention has particular application to the variant of the SHA1 authentication algorithms specified by the IPSec cryptography standard. In accordance with the IPSec standard, the invention may be used in conjunction with data encryption/encryption architecture and protocols. However it is also suitable for use in conjunction with other non-IPSec cryptography algorithms, and for applications in which encryption/decryption is not conducted (in IPSec or not) and where it is purely authentication that is accelerated. Among other advantages, an authentication engine in accordance with the present invention provides improved performance with regard to the processing of short data packets.

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

Abstract: A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

Abstract: A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also includes a second path connecting a second series of logic elements in the logic array block, where one or more of the logic elements in the second series are not in the first series.

Abstract: A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function GI, I+1=GI OR GI+1 AND PI is to be performed. When GI+1=CI+1, GI, I+1=CI, arrival times of generate signals GI and GI+1, are investigated. If GI arrives before GI+1, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function GI, I+1?=GI? AND GI+1? OR PI? is to be performed. If the generate signal GI? arrives before GI+1?, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the combiner units may provide a generate and propagate bit pair in response to receiving respective bits of the first and the second value which correspond to a plurality of the respective columns. The carry creation unit may create an ordered plurality of carry bits each corresponding to one or more of the generate and propagate bit pairs. Each of the summation units may generate a plurality of sum bits in response to receiving the respective bits of the first and the second value which correspond to the plurality of respective columns.

Abstract: A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ?, such that, Y1=X1, Y2=X2?X1, Y3=X3?X2?X1, . . . , and YN=XN?XN?1? . . . ?X2?X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2t horizontal wiring tracks between each logic level. Additionally, l+f+t=L?1, and unlike existing prefix circuits, 1>0,f>0, and t>0.

Abstract: The invention provides a dynamic domino circuit that is robust under noisy condition. The invention also provides a dynamic adder that contains nodes that can produce true dynamic inversion without compromising area or speed. The invention further improves speed of the adders by cutting the latch delay while not requiring complex clocking.

Abstract: A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.

Abstract: The present invention provides an efficient implementation of multiprecision arithmetic, such as for a microprocessor. For example, an implementation of multiprecision arithmetic is provided that eliminates condition codes, such as condition codes for a carry bit and a borrow bit, and eliminates an add-with-carry instruction for multiprecision addition and a subtract-with-borrow instruction for multiprecision subtraction. In one embodiment, a method includes separately performing a first one or more arithmetic operations and a second one or more arithmetic operations. The second arithmetic operations indicate if the first arithmetic operations cause a carry condition or if the first arithmetic operations cause a borrow condition. The one or more results of the first and second arithmetic operations are then provided. The first and second arithmetic operations can be executed in parallel on a microprocessor.

Abstract: In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit adders.

Abstract: In a specialized functional region of a programmable logic device, in which certain components may not be used, those components can be placed in a low-power mode so that they do not switch. For example, in an adder which is not being used but is receiving inputs, the current path for the adding circuitry is interrupted, while the output is forced low. If the adder is a carry/look-ahead adder, the GENERATE and PROPAGATE signals normally used in subsequent stages to predict the value of the carry signal are forced to constant values even if the inputs to the adder are changing.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum additions of the instruction operand's base register value with a displacement value in the instruction. The address generation logic also includes a carry prediction history block associated with the instruction that provides predicted carry-in values to the adders during the partial sum addition operation. In a related embodiment, the carry prediction history block that, in an advantageous embodiment, is appended to the instruction includes a predicted row access select (RAS) carry-in value, a predicted column access select (CAS) carry-in value and a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for the instruction were correct.

Abstract: Embodiments are provided in which the generation of a carry of a sum of two numbers can be implemented by adding only some most significant bits of the two numbers and assuming that the sum of the remaining bits do not generate a carry. Other embodiments are also provided in which the generation of the carry of a sum of the two numbers can be implemented using carry look-ahead techniques wherein generate and propagate terms are generated. By combining the product terms of the carry function and combining pairs of propagate or generate terms, the generation of the carry of the sum of the two numbers can be implemented in an And-Or-Inverter function less complex than that of prior art. Still other embodiments are provided in which one operand of a carry generation circuit comes from a fixed source and the other operand is selected from several forwarding sources.

Abstract: A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculated initial sum is then performed. Next, an intermediate sum for each group of M-initial sums according to a respective initial carryout value of each initial sum is then generated. Once generated, an intermediate carryout value for each generated intermediate sum is then calculated. Finally, a final sum is calculated from the intermediate sums generated according to a respective intermediate carryout of each intermediate sum.

Abstract: An apparatus for adding a first value and a second value each including a plurality of bits includes combiner units, a carry creation unit and summation units. Bits corresponding to bit positions of the first and the second value form respective columns. Each of the combiner units may provide a generate and propagate bit pair in response to receiving respective bits of the first and the second value which correspond to a plurality of the respective columns. The carry creation unit may create an ordered plurality of carry bits each corresponding to one or more of the generate and propagate bit pairs. Each of the summation units may generate a plurality of sum bits in response to receiving the respective bits of the first and the second value which correspond to the plurality of respective columns.

Abstract: A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in a redundant form to also subtract numbers received in redundant form, including numbers received from a bypass circuit. A non-propagative comparator circuit is then used to compare a given value with a result from the arithmetic circuit to determine if the result is equal to the given value. All of the operations described above can be accomplished without propagating carry signals throughout the circuitry.

Abstract: A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from a plurality of 4-input/1-output logical functions depending on configuration data. A 4-2 carry block generates a 4-2 carry output from the second to fourth logical inputs. A first signal is generated from at least the logical output, a second signal from at least the first logical input, a third signal from at least a 4-2 carry input signal, and a fourth signal from at least the 4-2 carry input signal. A multiplexer selects one of the second and third signals depending on the first signal to produce a carry output signal. An exclusive OR circuit produce an exclusive-ORed result from the logical output and the fourth signal.

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.