Abstract: A system includes a device, a BIOS, and a processor. The BIOS includes a storage operable to store predefined identifier/user defined name pairs. The processor is operable to, detect the device, determine a predefined identifier for the device, and access the storage to locate a predefined identifier/user defined name pair corresponding to the predefined identifier. The processor is further operable to provide a user defined name of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is present, and provide the predefined identifier of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is not present.

Abstract: A processing system with multiple processing units may support separate operating systems (OSs) in separate partitions. During an initialization process, a preboot manager in the processing system may copy software to a sequestered area of memory in the processing system. The preboot manager may also configure the processing system to hide the sequestered area of memory from a first partition of the processing system. Also, the preboot manager may use a first processing unit in the processing system to boot an OS on the first partition, and the preboot manager may transmit a boot trigger from the first processing unit to a second processing unit in the processing system. The boot trigger may cause the second processing unit to use the software in the sequestered area of memory to boot a second partition of the processing system. Other embodiments are described and claimed.

Abstract: A processing system and method for connecting to a remote USB device automatically. The processing system and method provide a user computer to be connected to or disconnected from a USB device via a network system and a USB server connected to the USB device. In the beginning, the user computer finds a USB device for the user computer from the USB server via the network system; when detecting that the user computer issues request messages, the USB server connects the user computer with the USB device, and the USB device executes corresponding services according to the request messages issued by the user computer; in the last, after detecting that the USB device has finished the corresponding services according to the request messages issued by the user computer, the USB server is enabled to disconnect the user computer from the USB device.

Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.

Abstract: A first computing device receives one or more messages, wherein the one or more messages includes information regarding one or more components, wherein each component is part of one or more systems and wherein each system includes one or more sub systems. The first computing device determines that a first system has changed based on the first computing device comparing the one or more messages to a hierarchical model, wherein the change to the first system includes a change associated with a first component of the first system. The first computing device determines a position of the first component within the first system and within one or more sub-systems of the first system based on the one or more messages. The first computing device updates the hierarchical model to include the first component in a hierarchical location that corresponds to the determined position of the first component.

Abstract: Techniques for using hardware-based mechanisms for updating computing resources are described herein. At a time after receiving a code update request, one or more hardware-supported system management capabilities of processors within a computing system are invoked at least to interrupt execution of currently running instructions. While the system management capabilities are active and instruction execution is suspended, programmatic routines are updated. After the updates are complete, instruction execution is resumed.

Abstract: Implementations of the present disclosure involve methods and systems for component placement in a datapath block of a microelectronic circuit design. In particular, implementations provide for collecting groups of common components in the datapath block that form a row or partial row. A preliminary layout of the datapath block is performed with the component set rows and any other components of the datapath block design. Common components are then collected into groups or sets to form additional rows within the datapath layout, with at least some consideration to the wire lengths between components in the rows. By collecting common components into rows with consideration to the wire lengths between interconnected components, the timing performance of the datapath block may be improved.

Abstract: A domestic appliance (1) with a bus (2) is disclosed. A plurality of modules (3) are connected to the bus, each controlling an operational component (4). Initial programming of the modules may take place from a single connection point (61). The modules may be configured to control the domestic appliance jointly and non-hierarchically. Suitably, all modules are identical up to content of a data memory provided therein.

Abstract: There is provided a communication address detection apparatus, a connector with a built-in control circuit, and a communication address detection method capable of preventing abnormal operations even in cases when a voltage level to be input to any one of a plurality of communication address setting terminals has inverted due to some faults. In a communication address detection apparatus for detecting a communication address in accordance with a combination of voltage levels of high or low levels input to a plurality of communication address setting terminals, the combination of the voltage levels with the assigned communication address is set which is stored in a communication address information storing unit (172) is set so as to become a combination of the voltage levels that has no assigned communication address when any one of the voltage levels in the combination of the voltage levels has inverted.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract: The invention relates to a cluster coupler in a time triggered network for connecting clusters operating on the same protocol. Further, it relates to a triggered network having a plurality of clusters, which are coupled via the cluster coupler. It also relates to a method for communicating between different clusters.

Abstract: The portable electronic device includes an operation unit, a storage unit, a setting unit, and a control unit. The operation unit inputs characters. The storage unit stores a first conversion table and a second conversion table different from the first conversion table. The second conversion table is different from the first conversion table. The setting unit sets a first mode and a second mode. In a case in which the first mode has been set by the setting unit, the control unit refers to the first conversion table when characters input by way of an operation of the operation unit are converted into another type of characters or character set. In a case in which the second mode has been set by the setting unit, the control unit refers to the second conversion table when characters input by way of an operation of the operation unit are converted into another type of characters or character set.

Abstract: A system for providing situational awareness outside a temporary incident area network includes a prioritized connection module for connecting a mesh network at the incident area to one of a plurality of available communications channels, with the selection based not only on the availability of a communications channel but also on the associated expense, speed, reliability or bandwidth, so that high bandwidth traffic such as video and pictures can be reliably sent from the incident area to a location outside of the incident area. In one embodiment switching to a satellite phone network bypasses problems with terrestrial networks such as cell phone networks and landlines which may be down.

Abstract: A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

Abstract: A monitoring device includes a detection unit which is inserted between the device to be monitored and a processing apparatus performing processing for the device to be monitored and detects a failure which occurs in the device to be monitored, a notification unit generating failure information indicating a content of the failure detected by the detection unit and notifying the generated failure information and the occurrence of the failure to the processing apparatus, and an acquisition unit acquiring status information after the occurrence of the failure of the device to be monitored from the device to be monitored and storing the acquired status information in a storage unit as the failure occurs.

Abstract: Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit. The control signal generator generates an inverted control signal including a first bit and a second bit using a decoded signal in response to a test enable signal. The first data input unit inverts a first bit of input data in response to the first bit of the inverted control signal to generate a first bit of first internal data. Further, the first data input unit inverts a second bit of the input data in response to the second bit of the inverted control signal to generate a second bit of the first internal data.

Abstract: A method may be performed by an electronic device coupled to a volatile system memory. The method includes entering a hibernation mode of the electronic device, where in the hibernation mode, the volatile system memory is powered off. The method further includes detecting a triggering event and, in response to detecting the triggering event, exiting the hibernation mode. While exiting the hibernation mode, the volatile system memory is powered and a pre-hibernation state of the volatile system memory is restored.

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract: A method of distinguishing at least one key of a key array. The method can include, via a processor, detecting initial startup of a processing system. The method further can include, during the initial startup, distinguishing at least a first key of the key array from other keys of the key array, wherein the first key is selectable to access a system startup menu or system function.

Abstract: Methods and systems for a device are provided. The device includes physical function (PF) representing a physical component and is assigned to an XF group. The XF group includes a plurality of virtual functions (VFs) associated with the PF, each VF identified by a unique number. A number of XF group that are assigned to the PF is configurable depending on the function of the physical component.

Abstract: A system for controlling bus-networked devices includes a gateway including a memory unit and having an interface to an open field bus. A power supply unit supplies primary power for the gateway and bus subscribers. An auxiliary power supply unit supplies auxiliary power for the bus subscribers independent of bus functionality. A pluggable connection cable is electrically connects the gateway to the bus subscribers and transmits the primary and the auxiliary power and control and/or status information between the gateway and the bus subscribers. An application bus networks the bus subscribers to each other and is operable by the connection cable. A bus controller writes a target bus configuration of the application bus and stores the target bus configuration in a non-volatile manner in the memory unit. The bus controller is also configured to overwrite the target bus configuration with a present, actual bus configuration.

Abstract: Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration.

Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.

Abstract: Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents super-standard features supported by each device. Mutually supported super-standard features are enabled for further communications between the devices. If no super-standard features are mutually supported or if the second device is non-enhanced, no super-standard features are enabled in further communications between the devices.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: The present embodiments relates to wireless adaptors. In one embodiment, a method is provided. The method may include obtaining an adaptor-device identification that identifies both a wireless adaptor and a wired device coupled with the wireless adaptor; and communicating with a network device via a wireless network using the adaptor-device identification, the wired device being distinguishable from other wired devices using the adaptor-device identification.

Abstract: A method for providing virtualization of information handling resources includes accessing a information handling system and a information handling resource, accessing a first virtual function configured to cause virtualized access to the information handling resource through the interface, accessing a second virtual function configured to cause virtualized access to the information handling resource through the interface, and selectively mapping the first virtual function and the second virtual function to information handling systems of the system. The selective mapping includes preventing the first virtual function and the second virtual function from both being mapped to the same information handling system.

Abstract: A tool for dynamically naming network ports and switch ports in a chassis. The tool retrieves, by one or more computer processors, chassis specifications of the chassis. The tool retrieves, by one or more computer processors, identifying information for components of the chassis. The tool determines, by one or more computer processors, a plurality of network ports and a plurality of switch ports within the chassis not assigned an alternative port name. The tool constructs, by one or more computer processors, alternative port names for the plurality of network ports and the plurality of switch ports within the chassis not assigned an alternative port name.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: A method, apparatus, and program product deploy a workload on a host within a computer system having a plurality of hosts. Different hosts may be physically located in proximity to different resources, such as storage and network I/O modules, and therefore exhibit different latency when accessing the resources required by the workload. Eligible hosts within the system are evaluated for their capacity to take on a given workload, then scored on the basis of their proximity to the resources required by the workload. The workload is deployed on a host having sufficient capacity to run it, as well as a high affinity score.

Abstract: A computer system includes a receiver configured to pair with a set of peripheral devices and have active connections with a first subset of the peripheral devices and inactive connections with a second subset of the peripheral devices. The first and the second subsets of peripheral devices are subsets of the set of peripheral devices. If a select one of the peripheral devices in the inactive set of peripheral devices is operated, the receiver is configured to activate a connection with the select one of the peripheral devices in a latency period that is below human perception levels of the latency period.

Abstract: A setting value management service apparatus which is communicably connected to at least one image forming apparatus and manages configuration data of the image forming apparatus, comprises: a holding unit configured to hold configuration data of the image forming apparatus; an update unit configured to update configuration data held in the holding unit; and a communication unit configured to transmit/receive configuration data of the image forming apparatus to/from the image forming apparatus, wherein the configuration data contains control information about permission of update, and the communication unit transmits, to the image forming apparatus in accordance with the control information, configuration data, update of which is permitted for the setting value management service apparatus, out of configuration data held in the holding unit.

Abstract: A memory structure with reduced-reflection signals at least includes a processing unit; a lumped circuit unit, connected to the processing unit; a plurality of memories, connected to the lumped circuit unit; and a reflected signal absorption unit, disposed at one end of the lumped circuit unit. Thereby, with the cooperation of the processing unit with each memory for signal transmission, the reflected signal absorption unit can be used to absorb the reflected signals so as to reduce the number of reflected signals during signal transmission, achieving the effect of stable operation for the memories.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: In one embodiment, a computer implemented method is provided for generating a network patch plan. The method can include selecting at least two devices to be interconnected. The method can include selecting a role for each of the at least two devices. The method can include identifying a patching template. The method can include determining a priority order of available logical ports associated with each of the at least two devices. The method can include generating a patch plan based on the priority order.

Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.

Abstract: In one embodiment, a computer system comprises one or more processors, a circuit board assembly having at least one SATA port, a general purpose input/output port proximate the SATA port, signal generating logic to generate a signal when the general purpose input/output port is coupled to a connector, and a memory module communicatively connected to the one or more processors and comprising logic instructions stored in a computer readable medium which, when executed on the one or more processors, configure the one or more processors to configure the SATA port according to the signal generated by the signal generating circuitry.

Abstract: An image forming system includes an upstream apparatus for forming an image on a sheet, a downstream apparatus for applying sheet processing to the sheet on which the image is formed by the upstream apparatus, an exclusive communication path for communicating information which is necessary only for an operation of each apparatus in a state in which a communication partner is fixed between the upstream apparatus and the downstream apparatus, and a general-purpose communication path for communicating information in a state in which a communication partner is selectable between the upstream apparatus and the downstream apparatus. The exclusive communication path and the general-purpose communication path communicate information which respective paths can handle by sharing the information with each other.

Abstract: In a portable computing device having a system-on-chip (SoC) Acorn RISC Machine (ARM)-based resource architecture, a peripheral component interconnect express (PCIe) bus is used to insert PCIe device memory into system memory absent a PCIe driver. During a PCIe initialization, the contents of PCIe base address registers (BARs) are mapped or otherwise updated to coincide with values assigned to the PCIe device in the advanced configuration and power interface (ACPI) tables.

Abstract: A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.

Abstract: A host bus driver verifying apparatus is connected, through a host bus adapter, to a higher-order system and includes a storage device preliminarily storing correspondence relation information that correlates an operating system type operating in the higher-order system, a host bus adaptor type, and a driver type of the host bus adaptor; and a processor that obtains for the host bus adaptor, the driver type to be set in the higher-order system to which connection is made. The processor obtains the driver type based on the correspondence relation information, and connection information that includes information concerning the operating system type and the host adaptor type and that is received, via host bus adapter, from the higher-order system to which connection is made. The processor further verifies whether the obtained driver type matches a driver type set for a host bus adaptor in the higher-order system to which connection is made.

Abstract: A mobile computing device is provided. The device includes a first port having a pinout configuration that is configured to support at least one data format, a data source configured to provide data of a second data format that is different from the at least one data format, and a first multiplexer configured to selectively direct data from the data source towards the first port. The pinout configuration is modified to enable the first port to support the second data format.

Abstract: A wireless memory device may include logic configured to detect that first data has been written by a microcontroller to a first address of a memory space of the wireless memory device; incorporate the first data into a first packet, in response to detecting that the first data has been written to the memory space, wherein the first packet includes the first address; and provide the first packet to a wireless chipset to wirelessly transmit the first packet to a destination device. The logic may be further configured to receive a second packet from the wireless chip set, wherein the second packet was received wirelessly from the destination device; retrieve a second memory address from the second packet; retrieve second data from the second packet; and write the second data to the retrieved second memory address in the memory space of the wireless memory device.

Abstract: The disclosure provides an HVAC data processing and communication network and a method of manufacturing the same. In an embodiment, the network includes a first subnet controller and a system device. The first subnet controller is coupled to a data bus and configured to arbitrate with a second subnet controller for control of the subnet. The system device is configured to transition from a reset state to a first state that includes pre-startup tasks, and transition from the first state to a second state that includes waiting for the subnet controller to provide configuration parameters to the system device.

Abstract: In one embodiment, a user selects a primary component of a multimedia system to be configured in a configuration user interface of a mobile device. The configuration user interface of the mobile device displays a photo-realistic depiction of a back panel of the primary component. The photo-realistic depiction of a back panel includes photo-realistic depictions of connection ports located thereon. The user selects another component to be connected to the primary component. One or more classes of potential connections are determined between the another component and the primary component, and for each class of potential connection, the configuration user interface on the mobile device graphically guides the user to select a particular connection port on the photo-realistic depiction of the back panel of the primary component for the class of potential connection. Based on selections of particular connection ports from the user, a set of configuration data is generated.

Abstract: When transmitting serial data from a master device to a slave device, it is possible to promptly detect a communication error if any occurs. Serial data transmitted from the master device to the slave device has two or more continuous bytes of dummy data having an identical structure. When the slave device recognizes the dummy data, communication error processing is executed. Assume that the serial data is shifted by an affect of a noise. In this case, “a text end control code (ETX)” is also shifted and the serial data cannot be recognized and no data reception end process is executed. However, during a period after this, a part of the first dummy data and a part of the second dummy data are received and one dummy data is recognized. Thus, the slave device can promptly execute the communication error processing.

Abstract: A server system includes a chassis having a plurality of insertion slots that receive a plurality of server plug-in modules; at least one printed circuit board including at least one first microcontroller and arranged in the chassis to contact server plug-in modules received in the insertion slots; and a first server plug-in module including a first system management controller and arranged in a first insertion slot and coupled to the at least one printed circuit board, wherein the first microcontroller and the first system management controller are coupled together via at least one first signal line, and the first microcontroller is arranged to provide the first system management controller with at least one chassis-specific configuration value.