Abstract: A method is described for transmitting data between participants of a serial, ring-shaped communications arrangement in which the participants are serially connected to one another, wherein a data packet is passed from a participant provided as a master to further participants provided as slaves, wherein the data packet is passed from slave to slave, and wherein address information of the data packet is altered by each slave.

Abstract: A control system controls safety-critical and non-safety-critical processes and/or system components. The system includes a first control unit for controlling the non-safety-critical process and/or the non-safety-critical system components, at least one input/output unit connected to the first control unit, a communication coupler, which is connected to the first control unit via an internal coupler bus, and a second control unit for controlling the safety-critical process and/or the safety-critical system components. For providing safety-related functions, the second control unit includes a first dual-port RAM and at least two processors, only one of which is connected to the first dual-port RAM.

Abstract: Partitioning execution of a program between a client device and a cloud of network resources, exploits the asymmetry between the computational and storage resources of the cloud and the resources and proximity of the client access device to a user. Programs may be decomposed into work units. Those work units may be profiled to determine execution characteristics, modeled based on current state information and the profile, and a model performance metric (MPM) generated. Based on the MPM, work units may be partitioned between the client and the cloud.

Abstract: Provided is a method for controlling multiple devices in an automatic interworking manner, by which the multiple devices are controlled, according to a set of operation mstoringodes including combined functions of the multiple devices, through one central control device without individually controlling the functions of each of the multiple devices. The method includes an operation mode setting step for setting an operation mode in which performable functions of the electronic devices are combined and performed in a specific order and for storing the set operation mode in the central control device, an operation mode selecting step for selecting an operation mode to be executed in a plurality of set operation modes, and a controlling step for controlling the electronic devices according to the selected operation mode.

Abstract: An electronic device associates first information and at least a first portion of a first image, and uses a second image that includes a portion corresponding to at least the first portion of the first image to access the associated first information.

Abstract: A method of operating a module is disclosed. The method includes determining a voltage between an I2C clock connection and a ground connection, setting a module communication address based on the determined voltage, receiving via the I2C clock connection and the I2C data connection a first command addressed to the module communication address, and responding to the first command. Other methods and devices are disclosed.

Abstract: A method and system for validating presence of a communication device in a confined area using a wireless local area network (WLAN) includes sending a first handshake message including a generated first key over a second network connection different from the WLAN connection by a device. A next step includes generating a second key to be returned to the device in a second handshake message over the same connection. A next step includes sending a WLAN probe request that has been modified to include the second key via the WLAN. A next step includes validating whether the device is present within the confined area using a second communication network; whereafter allowing communication access over the second network using both the first and second keys if the device is validated as being present within the confined area, and taking appropriate action if the device is not validated as being present within the confined area.

Abstract: The disclosure relates to a field bus network having two masters and at least one slave which are connected to one another in a dual ring comprising a first ring and a second ring and each of the two masters being configured for generator data packets and sending out a generated data packet on each of the rings at regular time intervals. The at least one slave being configured for receiving a data packet at an input and forwarding it at an output. Each of the two masters being configured for receiving a data packet coming from the other master in each case at an input and forwarding it at an output.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: A storage apparatus comprises a storage controller and multiple storage devices. The storage controller sends, to either a storage device which is a copy source of copy-target data, or a storage device which is a copy destination of the copy-target data, a copy indication showing areas of the copy source and the copy destination, and the storage device, which receives the copy indication, copies data of the copy-source area to the copy-destination area based on the copy indication without going through the storage controller.

Abstract: In the case of forming an audio network system in which a plurality of processors each having two sets of transmission I/Fs and reception I/Fs are connected and a TL frame generated by a master node and including a plurality of storage regions for audio signals circulates among the processors in each constant period to transport audio signals the among processors, the system is configured such that when a transmitted TL frame does not return to the reception I/F on the forward side but returns to the reception I/F on the backward side in a single mode of transmitting the TL frame to the forward side and circulating the TL frame through one transmission route, the system shifts to a twin mode of transmitting and circulating TL frames through two transmission routes.

Abstract: A semiconductor chip that may be configured to function as either a master chip or a slave chip. The semiconductor chip may be included in a microelectronic assembly including a plurality of vertically stacked semiconductor chips, with each of the chips containing functional circuit blocks that enable each semiconductor chip to function as either a master chip or a slave chip under in accordance with a state input stored on the same chip, or received from another chip in the stacked assembly or from another component of a system in which the stacked assembly is configured to operate.

Abstract: A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Abstract: Embodiments of the invention describe driving data onto a bus. The embodiments include a data driver circuit having a data capture circuit coupled to the bus. The data capture circuit receives data relative to a write strobe signal and captures a first digit of the data responsive to a first edge of the write strobe signal and at least a second digit responsive to a second edge of the write strobe signal. The data driver circuit includes a feedback capture circuit that captures each digit in substantially the same manner as the data capture circuit, and generates a latch control signal indicative of when each digit is latched. The latch control signal is provided to a write control circuit that determines which digit was latched first relative to a timing, and generates a select control signal to drive captured digits onto the bus in the order the digits were received.

Abstract: There are provided a method and an apparatus for scroll information input in an electromagnetic induction way. The method comprises steps of: definition of scroll bars, where a horizontal scroll bar and a vertical scroll bar are defined for an electromagnetic board by means of a controller of the electromagnetic board; implementation of scrolls, where virtual scrolls for the scroll bars of the electromagnetic board are achieved based on positional changes of an electromagnetic pen over the horizontal scroll bar and the vertical scroll bar of the electromagnetic board; and mapping of scrolls, where the virtual scrolls for the scroll bars of the electromagnetic board are mapped into scrolls for scroll bars in a computer by means of the controller.

Abstract: A bus interface receives, via a bus, a control signal for controlling an electronic circuit, and outputs a signal corresponding to the received control signal to the electronic circuit. A signal maintaining circuit maintains the value of the signal to be output from the bus interface to the electronic circuit in accordance with an instruction from a reset control circuit. When the bus becomes unusable due to termination of operations of the control device or the like, the reset control circuit causes the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently resets the bus interface so as to restore the bus.

Abstract: Exemplary embodiments are directed to a safety module for connection to an automation device or automation system which is provided for control of safety critical and non-safety critical processes and/or plant components. The module includes a communication board that includes a processing unit which is connected via an input/output bus slave and an external input/output bus connected to a central processing unit, and one or more secure processing units arranged on one or more circuit boards having safety oriented input/output circuits for safety oriented functions. A serial communication master is connected via communication links to at least one of the circuit boards so that the at least one circuit board receives messages sent by the communication board, transmits safety oriented messages from and/or to the processing unit of the communication board via one of the secure processing units.

Abstract: A network control system for managing several switching elements. The network control system includes first and second controllers for generating data for managing first and second sets of switching elements. The first controller is further for serving as a master controller of the first set of switching elements. The second controller is further for serving as a master controller of the second set of switching elements. The master controller for a particular set of switching elements is the only controller that is allowed to propagate data to the particular set of switching elements data for managing the particular set of switching elements.

Abstract: A synchronous data transmission system for transmission of data between two communication partners, of which one serves as a transmitter and one as a receiver, comprising a clock signal producer which produces a transmission clock signal with a transmission clock signal rate from the transmitter to the receiver, which during the occurrence of one of the events equals an event specific transmission clock signal rate associated with the arising event and during an event free period of time equals a fundamental clock rate different of all event specific transmission clock signal rates.

Abstract: A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.

Abstract: An example method is provided and includes receiving, from a host device, a first signal over a two-wire bus to an address on the two-wire bus corresponding to a small form factor (XFP) module, the host device being located outside the XFP module, the two-wire bus coupling the host device with a first controller inside the XFP module and a second controller inside the XFP module that share the address such that the first controller and the second controller receive the first signal, and blocking a second signal from the second controller to the host device using digital isolation buffers. A third signal from the first controller to the host device over the two-wire bus is not blocked. In specific embodiments, the first controller includes a XFP compliant controller and the second controller includes an optical controller.

Abstract: Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.

Abstract: An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.

Abstract: The present invention relates to a control circuitry module group, an electrical device, and a modem device. The control circuitry module group is configured for communication and/or power supply between a master control module and at least one slave modules in an electrical device. The control circuitry module group comprises: a bus; a bus control module coupled to the master control module and the bus, configured to receive a control signal from the master control module, add a target address in the control signal, and send to the bus the control signal with the target address; and at least one slave control modules each coupled to a corresponding slave module and the bus, respectively, and configured to receive the control signal with the target address via the bus, and controlling power supply to the slave module in response to the control signal.

Abstract: The invention relates to the use of an IO link for linking a field device to a master assembly.

Abstract: A field bus system includes at least one bus module designed as a master module with at least one connecting device for connection to a network and with at least one port for connecting a parameterizable IO link device. The field bus system uses a data storage device which is designed as an IO link device and which can be connected to the at least one port for connecting an IO link device and in which all parameters of the IO link devices connected to the master module are stored and can be read by the master module.

Abstract: This document discusses, among other things, a multi-address Inter-Integrated Circuit (I2C) selection circuit configured to receive a number (N) of identification (ID) signals from a corresponding number (N) of ID pins of a slave I2C device and at least one of a data signal from a serial data line (SDA) of an I2C bus or a clock signal from a serial clock line (SCL) of the I2C bus, and to determine one of 4 to the power of N (4N) selectable I2C addresses using the number (N) of ID signals and at least one of the data signal or the clock signal. In an example, the multi-address I2C selection circuit can determine 4 selectable I2C addresses using a single ID signal from a single ID pin of the slave I2C device.

Abstract: An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically selected from the group of functions. The approach further allows the master function to perform a disruptive adapter data collection while inhibiting performance of disruptive adapter data collection processes by the other (non-master) functions.

Abstract: An intelligent connector is disclosed having a signal processing unit, a first port, and a second port. The signal processing unit communicates signals between a bus and a slave module. The first port is coupled between the bus and the signal processing unit, and is connected to a power supply line. The second port is coupled between the signal processing unit and the slave module, and is positioned to provide a power supply to the slave module.

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. An address list may associate each of a plurality of slave devices coupled to a control data bus with a plurality of slave device identifiers. Access to the control data bus may be controlled based on the address list such that, in a first mode of operation information may be broadcast to multiple slave devices using a first group slave device identifier and, in a second mode of operation, information may be exchanged with a single slave device using an individualized slave device identifier.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: A first external tool (10A) serially connected to an electronic controller (20A) through a pair of communication lines (LANH, LANN) applies a high voltage (Vaa) higher than a normal control voltage (Vcc) to the communication line (LANH) when a program is written. The electronic controller (20A) recognizes connection of the first external tool (10A) by a comparison circuit (212A) for monitoring a received voltage and a write-mode determination circuit (218A), initializes a microprocessor (200), and receives and stores an total control program (TCPRG) in a program memory (204A) based on a content of a boot program memory (201). During an operation of the electronic controller (20A), the external tool (10A) is removed and the high voltage (Vaa) is not applied to the communication line (LANH). Therefore, the electronic control apparatus is not erroneously placed in the write mode.

Abstract: A system-on-chip bus system and an operating method of the same are provided. The bus system includes a master device, a slave device and an interconnector coupled between the master device and the slave device. The interconnector includes a synchronization/compaction block to control traffic provided from a master device to a slave device. When a write request traffic and a corresponding write data traffic are all provided from the master device, the synchronization/compaction block may transfer the two traffics to the slave device.

Abstract: A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

Abstract: A bus system includes a plurality of master devices each of which issues a transaction request having a first transaction identifier with a first bit width and a slave device responding to the transaction request having a second transaction identifier with a second bit width and supplying a transaction response having the second transaction identifier to the plurality of master devices. The embodiment further comprises a bus configured to connect one of the plurality of master devices and the slave device; and an ID converter configured to connect the bus and the slave device and to map the first transaction identifier to the second transaction identifier for providing the second transaction identifier to the slave device and map the second transaction identifier to the first transaction identifier for providing the first transaction identifier to the one of the plurality of master devices.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A data storage expanding apparatus is electrically coupled to a terminal equipment and multiple data storage groups. Each data storage group includes a plurality of data storage devices. The data storage expanding apparatus configured to transmit an operating data between the terminal equipment and to a particular data storage device. The data storage expanding apparatus includes a data storage expanding module and multiple signal expanding modules. The data storage expanding module is electrically coupled to the terminal equipment. The signal expanding modules are electrically coupled in series, and to the data storage groups, respectively. One of the signal expanding modules is electrically coupled to the data storage expanding module. The operating data signal is transmitted to the signal expanding module via the data storage expanding module electrically connected to the signal expanding module, and then transmitted to particular data storage device via the signal expanding module.

Abstract: A server system includes a baseboard management controller and calculation modules. Each calculation module includes a system on chip, slave devices and a switch. The switch is connected with the baseboard management controller, the system on chip and the slave devices. The switch issues an address selection signal to select one of the slave devices to be connected with the switch. The switch switches the baseboard management controller and the system on chip to be connected with one of the slave devices by a control signal.

Abstract: A bus interface couples a master device and one or more slave devices. Upon detecting a condition on the bus, one or more of the slave devices may force an extension of the bus condition for a predetermined time period. The forced extension may comprise forcing a voltage level, causing other devices on the bus to change modes. A master on the bus may detect an out-of-variance bus condition and, in response, take action to change the bus state to a stable condition. The bus interface may include power contacts and a single-wire bus for communicating between a host device and one or more battery packs.

Abstract: Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.

Abstract: A method for setting addresses of slave devices in a communication network is provided. In the communication network, a master device identifies address-collided slave devices and requests the address-collided slave devices to return their unique identification data. The master device sets addresses of the address-collided slave devices so that each of the slave devices in the communication network has a different address from one another.

Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two or more devices within an electronic apparatus. Embodiments disclosed herein relate to scanning for slave identifiers (SIDs) on a CCIe bus. A disclosed method includes transmitting a first inquiry on a control data bus, where the first inquiry includes a first configuration of bits, determining presence of a slave device that has a slave identifier that includes a second configuration of bits that matches the first configuration of bits, and repetitively transmitting additional inquiries on the control data bus with different configurations of bits until all bits of the slave identifier are determined The slave device may assert a response to each inquiry that includes a configuration of bits that matches a corresponding configuration of bits in the slave identifier.

Abstract: In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus.

Abstract: A plurality of slave devices is coupled to a control data bus along with at least one master device that is managing access of slave devices to the control data bus. At least one slave device operates in a sI2C protocol mode of operation and at least one other slave device operates in a CCIe mode of operation. At least the slave devices using sI2C protocol mode use the control data bus for interrupt requests. In order to maintain the integrity of CCIe communications, the slave devices using the sI2C protocol mode disables issuing IRQs when the control data bus operates according to the CCIe mode.

Abstract: Systems and methods for flow control within a Serial Peripheral Interface without additional signal lines are included herein. In one example, a method includes generating a flow control command. The method also includes sending the flow control command from a master device to a slave device with a Serial Peripheral Interface. In addition, the method includes sending a memory address from the master device to the slave device. Furthermore, the method includes detecting a ready indicator in the master device. The method also includes waiting to receive a ready indicator and communicating with the slave device in response to the ready indicator.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: A serial interface comprises a clock line, a request line, a ready line, a master-to-slave data line, and a slave-to-master data line. A master device transmits a clock signal to a slave device over the clock line. In a first transaction, the master device sends a master transmission request signal to the slave device over the request line; in response, the slave device sends a slave transmission accept signal over the ready line, which causes the master device to transmit binary data to the slave device over the master-to-slave data line. In a second transaction, the slave device sends a slave transmission request signal over the ready line; in response, the master device sends a master transmission accept signal over the request line, which causes the slave device to transmit binary data to the master device over the slave-to-master data line. In at least one of the transactions, the master and slave devices transmit binary data at the same time as each other.