Abstract: When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped.

Abstract: Disclosed is a method for automatically setting ID in UART ring communication in which a master and a plurality of slaves are formed in a ring-type network, the method including initializing the master to output a master ID (initializing step), receiving, by the plurality of slaves, the master ID, setting its own IDs by adding the master ID to a reference value and outputting the set ID (slave ID setting step), changing, by the plurality of slaves, its own IDs based on whether its own ID is same as the received ID, receiving, by the master, the IDs outputted by the plurality of slaves, and changing a currently highest value of slave IDs stored in the master in response to values of received slave IDs (changing step), and finishing the ID setting or re-setting the slave IDs, in response to the Current Max Slave ID (finish determining step).

Abstract: A device is provided comprising a control data bus including at least a first line. A master device may be coupled to the control data bus and configured to control the control data bus. A plurality of slave devices may be coupled to the control data bus and share the first line. The master device may be configured to send a single global wake up signal on the control data bus that causes any sleeping slave devices to wake up. Alternatively, the master device may send a global wake up signal followed by a targeted sleep signal to non-targeted slave devices to implement a “targeted wake up” of specific slave devices. The master device may send the single global wake up signal by bringing the first line low for a predetermined period of time.

Abstract: Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

Abstract: An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component.

Abstract: The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board.

Abstract: A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.

Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract: An address polling method and system for communicating unique slave address values to a master device over a shared bus. The method includes receiving a request signal from the master device requesting that a slave address from each slave device coupled to the data line be sent to the master; causing, in a serial manner, the data line to be placed in logic states corresponding to bit values in a first slave address; and upon the data line being placed in a logic state that is different from a corresponding bit value of the first slave address, determining that another slave device is placing its slave address on the data line and temporarily entering an idle state until such other slave device has finished communicating its slave address to the master device.

Abstract: The present application is directed towards systems and methods for coordination and management of a shared resource in a multi-core system. In a multi-core system, multiple cores may be utilizing a shared resource. However, internal resources common to the shared resource may need to be initialized by only one core, and independent and uncoordinated initialization by multiple cores may cause errors. The present invention provides systems and methods for coordinating such initialization and use through a handshaking protocol.

Abstract: Disclosed herein is a peripheral equipment control device controlling data flow via a peripheral equipment, the peripheral equipment control device including: a peripheral equipment control processor that can control an operation of one or more peripheral equipment; and a bus adapted to connect the peripheral equipment control processor, a main processor, and the one or more peripheral equipment, the main processor being provided outside the peripheral equipment control device to control the operation of the one or more peripheral equipment, in which the bus stores addresses that are referenced by the main processor and the peripheral equipment control processor to access the one or more peripheral equipment, and the bus prohibits access to the peripheral equipment by the peripheral equipment control processor while the main processor is active.

Abstract: When transmitting serial data from a master device to a slave device, it is possible to promptly detect a communication error if any occurs. Serial data transmitted from the master device to the slave device has two or more continuous bytes of dummy data having an identical structure. When the slave device recognizes the dummy data, communication error processing is executed. Assume that the serial data is shifted by an affect of a noise. In this case, “a text end control code (ETX)” is also shifted and the serial data cannot be recognized and no data reception end process is executed. However, during a period after this, a part of the first dummy data and a part of the second dummy data are received and one dummy data is recognized. Thus, the slave device can promptly execute the communication error processing.

Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.

Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.

Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.

Abstract: The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.

Abstract: The disclosure provides a technique of enabling to appropriately confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus includes a master and a slave which is connected with the master by a plurality of signal lines. The master and the slave are configured to perform a handshake by changing a signal level of a respective data signal line for a period of time longer than a cycle of a clock each other.

Abstract: In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

Abstract: Methods and systems for memory module communication control are disclosed. A method includes receiving a message associated with a memory module in communication with a controller via a bus including a clock line. Further, the method includes determining whether the bus is idle. The method also includes communicating a signal via the clock line regarding the message associated with the memory module in response to determining that the bus is idle.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: A signal transfer circuit comprising a control signal transfer unit configured to output an access request output signal and a memory address output signal to the arbiter after timings of the access request input signal of the access request and the memory address input signal input from the bus master have been adjusted, and output an access permission output signal, and a data signal transfer unit configured to output each data output signal to the corresponding bus master or the arbiter after a timing of each data input signal of the access request input from the arbiter or the bus master is adjusted, and output a data validity period output signal to the bus master after a timing of a data validity period input signal indicating a period in which each data is valid in the access request input from the arbiter is adjusted.

Abstract: Provided is a method of driving a system-on-chip (SOC). The method includes adding a first transaction to a list, allocating the first transaction to a first slot, determining whether a second transaction is redundant, and adding the second transaction to the list and allocating the second transaction to the first slot when it is determined that the second transaction is redundant. Accordingly, the SOC can increase outstanding capability and enhance performance of a system interconnection.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

Abstract: A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period.

Abstract: An information handling system includes a first managed system including a first processor and a first management controller and a second managed system including a second processor and a second management controller. The first management controller is coupled to directly communicate with the second management controller. In an embodiment, the first management controller is coupled to the second management controller via a first I2C interface.

Abstract: Embodiments of the present invention provide a storage apparatus, and a system and a method for executing access operations. The apparatus includes an interleaved bus, N memory groups, and K direct-connect bus groups, where K is less than or equal to N; the interleaved bus includes M master interfaces and S slave interfaces, where M is less than or equal to S, and each master interface among the M master interfaces is configured to receive continuous-addresses access operations; each memory group among the N memory groups includes S memories respectively connected to the S slave interfaces, where the interleaved bus is configured to decode and send the continuous-addresses access operations to at least one memory group among the N memory groups in an interleaved manner; and a first direct-connect bus group among the K direct-connect bus groups receives and sends the discrete-addresses access operations to at least one memory group.

Abstract: A system on chip (SoC) includes a first master, a slave, a bus switch transmitting a first command of the master and a first response of the slave, and a first priority controller connected between the first master and the bus switch The first priority controller measures at least one of first bandwidth and first latency based on the first command and the first response and adjusts the priority of the first command according to at least one of the measurement results.

Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Abstract: System and methods are provided. In one embodiment, a system includes serial peripheral interface (SPI) bus and a master device communicatively coupled to the serial peripheral interface (SPI) bus. The system further includes a first slave device communicatively coupled to the SPI bus. The system additionally includes a second slave device communicatively coupled to the SPI bus and to the first slave device; wherein the first and the second slave devices are communicatively coupled in parallel to the SPI bus and wherein the first and the second slave devices are communicatively coupled to each other by using a first chain line, and wherein the master device is configured to communicate with the first and with the second slave devices over the SPI bus.

Abstract: A link negotiation method for enabling communication between first and second Serial Attached Small Computer Interface (SAS) storage devices operably coupled by an optical cable. The method includes continuously transmitting a non-SAS data pattern between the first and second SAS storage devices. In response to successful exchange of the non-SAS data between the first and second SAS storage devices, a SAS data pattern is continuously transmitted between the first and second SAS storage devices. In response to successful exchange of the SAS data pattern between the first and second SAS storage devices, an initial frame is continuously transmitted between the first and second SAS storage devices. Communication between the first and second SAS storage devices is enabled in response successful communication of the initial frame between the first and second SAS storage devices.

Abstract: A control apparatus which controls an access to a memory acquires, for the access to the memory, a predetermined address corresponding to the order of addresses at which the memory is accessed, and determines whether the predetermined address is identical to the target address of the access. In a case where the predetermined address is identical to the target address, the control apparatus controls the access to the memory so as to perform page close after the end of the access to the target address.

Abstract: A hardware system comprises a digital signal generator, which generates a digital electrical signal that describes a first physical state of a first device; an analog electrical signal generator, which generates an analog electrical signal that describes a second physical state of the first device; a hybrid digital state signal generator, which generates a hybrid digital state signal that comprises the analog electrical signal overlaid onto the initial digital electric signal; and a hybrid signal transmitter, which transmits the hybrid digital state signal from the first device to a second device, wherein the second device comprises a hybrid signal receiver/decoder that extracts the analog electrical signal from the hybrid digital state signal.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed.

Abstract: A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Abstract: Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Abstract: A sensor system utilizing adaptively selected carrier frequencies is disclosed. The system includes a system bus, a bus master, and a sensor. The system bus is configured to transfer power and data. The bus master is coupled to the system bus and is configured to provide power to the bus and receive data from the bus. The sensor is coupled to the system bus and is configured to transfer data on the bus using an adaptively selected carrier frequency.

Abstract: A sensor interface system includes a system bus, a bus master and a sensor. The bus master is coupled to the system bus. The bus master is configured to provide voltage regulation at a first band and perform data transmission within or at a second band. The sensor is also coupled to the system bus. The sensor is configured to receive or utilize the voltage regulation and to perform data transmission within or at the second band.

Abstract: A method of implementing remote transactions between system on a chip (SoC) nodes of a node interconnect fabric includes determining that a bus transaction initiated at a first one of the SoC nodes specifies a target at a second one of the SoC nodes, providing a virtual on-chip bus between the first and second SoC nodes within the fabric, and providing the bus transaction to the second one of the SoC nodes over the virtual link on-chip bus.

Abstract: A bidirectional communications link between a master device and a slave device includes first endpoint circuitry coupled to the master device generating forward data packets, second endpoint circuitry coupled to the slave device for receiving reverse data packets, and bidirectional communication circuitry for transferring forward data packets from the first endpoint circuitry to the second endpoint circuitry and reverse data packets from the second endpoint circuitry to the first endpoint circuitry. In response to a power down condition requiring a power down of at least one of the first endpoint circuitry and the second endpoint circuitry, performance of said power down is deferred until both said outstanding forward credit signal and said outstanding reverse credit signal have been de-asserted.

Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

Abstract: An apparatus and method for adaptively changing clock frequencies of a Central Processing Unit (CPU) and a bus in a digital system are provided. The system includes an Adaptive Frequency Scaling (AFS) controller and a clock controller. The AFS controller determines whether to change a clock frequency of the CPU according to operation information of the CPU, and determines whether to change a clock frequency of the bus according to operation information of the bus. The clock controller generates a clock frequency of the CPU and a clock frequency of the bus according to the determination of the AFS controller.

Abstract: A method and system for managing a computing system by using a hierarchy of autonomic management elements are described. The autonomic management elements operate in a master-slave mode and negotiate a division of management responsibilities regarding various components of the computing system.

Abstract: A data communication system includes a master and a slave. The master transmits a first subject signal including a first subject data to the slave via a transmission line. The slave extracts a clock signal from the first subject signal by performing a clock data recovery process and determines the first subject data based on the first subject signal. The slave transmits a second subject signal including a second subject data to the master during an existing period of the first subject signal without interfering an extracting of the clock signal and a determination of the first subject data. The master receives the second subject signal and cancels a waveform component of the first subject signal from a waveform of the second subject signal, and then determines the second subject data based on the second subject signal.

Abstract: Disclosed is a communication system that includes a source device outputting video contents, a sink device inputting the video contents, and a control transmission line and a video transmission line both connecting with the source device and the sink device to transmit data therebetween via the control transmission line and the video transmission line. The source device includes a control data I/O unit, a video data output unit, a control feature corresponding memory unit, a control unit. The sink device includes a control data I/O unit, a video data input device inputting video data via the video transmission line, a control feature corresponding memory unit, a control unit.

Abstract: A method for automatic lambda control of an internal combustion engine, in which, upon detection of a predetermined operating state of the internal combustion engine, a calibration factor (KAL) is determined and in which, during the operation of the internal combustion engine, a lambda measuring signal (iP) is corrected by the calibration factor (KAL) and is set as the actual lambda value (Lam(IST)) for the automatic lambda control of the internal combustion engine. The predetermined operating state is recognized when an engine coastdown is initiated.

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.