Abstract: A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

Abstract: It is determined that, when starting of direct memory access is newly requested, whether or not the direct memory access can be started, using a rate of using the bus at the present time by data transfer performed by all the direct memory access controllers which have already started direct memory access until then and all the processors, a data transfer rate needed by the newly requested direct memory access, a size of data which is transferred in one direct memory access operation or a size of data which a memory can accept, a latency for accessing the memory, and a latency for bus-right arbitration. The newly requested direct memory access is started when it is determined that the direct memory access can be started. Starting of the newly requested direct memory access is kept waiting when it is determined that the direct memory access cannot be started.

Abstract: An agent retrieves a request, which is part of a bus transaction, from a bus. The agent then stores an identifier of the bus transaction and responds to the bus transaction after a predetermined period of time, provided the agent was not the target of the request and the target agent did not respond. In one embodiment, the agent includes a queue and a timer. A controller within the agent starts the timer if the agent is not the target of the request, a snoop phase has occurred for the request, and the request is at the top of the queue. If the timer expires without the request having received a response, then the agent responds to the request.

Abstract: A computer system includes a first device on a first data bus, a second device on a second data bus, and a bridge device that delivers data transactions between the two devices. The bridge device includes an execution queue that stores only a higher priority transaction and transactions initiated before the higher priority transaction, and a controller that selects transactions from the execution queue to be completed on one of the data buses.

Abstract: A hardware implemented command queuing system in a hardware accelerated command interpreter engine. The command queuing system is an integral component of an autonomous hardware accelerated command interpreter type data processing engine that executes a programmable set of data processing commands in response to a stimulus from a host processor. The command queuing system is a configuration of registers and logic blocks that interact with a local host processor and other components within the command interpreter engine itself. The local host processor generates the commands to execute and the command queuing system queues the commands for seriatim execution by components within the command interpreter system.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent, a retry identification register, and a completion counter. The initiator PCI agent is adapted to couple to a PCI bus and communicate with a target PCI agent via the PCI bus by initiating a data transaction. The retry identification register is coupled to the initiator PCI agent. The retry identification register is adapted to store a target address and a transaction type corresponding to the target PCI agent when the target PCI agent issues a retry to the initiator PCI agent. The completion counter is coupled to the initiator PCI agent and is adapted to measure a latency period of the target PCI agent.

Abstract: A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.

Abstract: An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

Abstract: A bridge device for delivering data transactions between devices on two data buses in a computer system includes, for each pair of devices that may transact across the bridge device, a dedicated storage area that aids in completing transactions between the devices in the pair. The bridge device also includes a controller that allows transactions in one dedicated storage area to be completed without regard to the completion of earlier-issued transactions in another dedicated storage area.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.

Abstract: The present invention discloses a method, apparatus, and article of manufacture comprising a high performance interface for sending data to a remote device and receiving data from a remote device via a data communications device coupled to a processor. In performing these functions, the high performance interface supports asynchronous input/output operations. Moreover, the high performance interface transfers the data directly to and from the address space of a calling program, thereby eliminating use of intermediate buffers. In those instances where the calling program has not invoked the high performance interface, data can be stored in the address space of the operating system until the high performance interface is invoked by the calling computer program. Further, status can be returned to a remote device using back-channel capabilities.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract: A priority queue structure and algorithm for managing the structure which in most cases performs in constant time. In other words, most of the time the inventive algorithm performs its work in an amount of time that is independent on the number of priority classes or elements that exist in the queue. The queue itself consists of a linked list of elements ordered into subqueues corresponding to priority classes, with higher priority subqueues appearing earlier in the queue. An array of priority pointers contains an entry for each subqueue that points to the last element of each subqueue. Elements are removed for processing from the top of the queue. Removal takes constant time. Items are inserted into an appropriate subqueue by linking it at the end of its respective subqueue.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle.

Abstract: A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the secondary bus. The inventive method contemplates the bus extender arbitrating for control of the primary bus after a conflict is detected, and releasing control of the secondary bus if control of the primary bus is obtained. A target device on the secondary bus can then rearbitrate for control of the secondary bus. Once the target device controls the secondary bus, it can direct a RESELECTION signal to the bus extender, which responsively directs the signal to an initiator device on the primary bus. If the bus extender is unable to gain control of the primary bus after a conflict is detected, the SELECTION operation is allowed to proceed and the target device reattempts to assert the RESELECTION operation thereafter.

Abstract: A system interconnect architecture and associated arbitration scheme that provides for the interleaving of multiple accesses to a shared system resource by multiple components on a data block by data block basis. According to one embodiment, an access request is granted "immediately" upon receipt such that the effective access latency between an access request and the transfer of a first data block (e.g. a byte. a word, a long word, and a double long word as determined by the width or throughput of the data path) for the access is the minimum access latency to the shared system resource. If a second access request is received while a first access is being performed, the second access request is granted immediately, and the first and second access are thereafter interleaved such that data blocks of the accesses are alternately transferred by the system interconnect.

Abstract: A computer system and method concurrently process transactions directed to computer devices coupled to a bus agent. The method transmits first and second transaction requests from one or more computer processors across a computer bus to the bus agent. The bus agent transmits the first transaction request to a first computer device coupled to the bus agent. In addition, the bus agent transmits the second transaction request to a second computer device before the bus agent has received a transaction response to the first transaction request from the first computer device, thereby concurrently processing the transaction requests. The bus agent includes plural device managers each uniquely associated with one of the computer devices. Each device manager employs a queue pointer into a transaction queue to track each transaction involving the computer device associated with the device. manager.

Abstract: A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of a data portion of the bus. One embodiment of the computer system includes at least one central processing unit (CPU) and a main memory coupled to a processor bus. The main memory stores data, and the CPU executes instructions stored within the main memory. The processor bus is a split transaction bus. The processor bus is divided into an address bus, a data bus, and a control bus including address, data, and control signal lines, respectively. The CPU and the main memory each include a bus interface, and are coupled to the processor bus via the bus interface. The bus interface includes a transaction queue coupled to an interface unit. The interface unit is coupled to the address, data, and control buses, and performs bus transactions (i.e., read and/or write transactions) upon the processor bus.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.