Abstract: In one embodiment of the invention, a transaction queue stores a transaction request and issues a stream transaction for the stored transaction request when a slot in a set of active stream contexts becomes available. A token generator provides a token representative of a pre-fetched request. A queue selector transfers the transaction request to the transaction queue based on a selection condition.

Abstract: A parallel processing system includes a network and a plurality of nodes which communicates asynchronously between the plurality of nodes through the network. Each of the plurality of nodes may include a plurality of CPUs and a communication control unit. Each of the plurality of CPUs as an issuing CPU generates and transmits an asynchronous communication request, retransmits the asynchronous communication request in response to a non-acceptance reply, and executes a subsequent process in response to an acceptance replay. The communication control unit determines whether the asynchronous communication request is acceptable, returns the acceptance reply to the issuing CPU when the asynchronous communication request is acceptable, and the non-acceptance reply to the issuing CPU when the asynchronous communication request is not acceptable, and executes the asynchronous communication request.

Abstract: An electronic bus architecture for supporting posting of read requests by multiple master devices to multiple slave devices. Sideband signals added to the underlying master bus architecture permit slave devices to receive posted read requests from one or more master devices. The sideband signals are used by the slave devices and associated arbitration logic to enable the slave devices with varying latencies to return requested data to the originating masters when the data becomes available. The sideband slave bus architecture may be applied to enhance performance of AMBA based bus architectures as well as other well-known bus architectures supporting one or more master devices.

Abstract: A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus access, and also receives a signal indicating the pending workload of that device, as measured by the number of operations pending in a queue in that device. Based on the workload signal, the bus arbiter breaks any arbitration conflicts by assigning priority to the device with the greatest workload. In the event of ties, the bus arbiter may use other arbitration schemes to break ties between devices with equal workloads.

Abstract: A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.

Abstract: A system and method are provided for initiating peer-to-peer communications via a network bus. The system includes a bus controller in electrical communication with the network bus for controlling communications on the network bus, such as by transmitting commands onto the network bus. The system also includes at least one network device in electrical communication with the network bus, where the network devices collectively comprise at least first and second data channels. The first data channel is configured for Surrogate operation and includes an initiator command and a surrogate command. When the bus controller transmits a command onto the network bus that matches the initiator command of at least the first data channel, at least the second data channel is capable of executing the initiator command and at least the first data channel is capable of executing the respective surrogate command.

Abstract: A slave device receives commands from a master device for execution on a first-in, first-out basis. A status register is responsive to a queue of commands to provide a COMMAND_STATUS_FULL signal when the queue is full of commands. A configuration register provides a SHUT_DOWN signal identifying a shutdown status of the slave device. A bus control is responsive to the command and to either the COMMAND_STATUS_FULL or SHUT_DOWN signal to idle the data bus and deny the requesting master device access to the data bus if the command is for a non-locked transfer, or to stall the data bus if the command is for a locked transfer request.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: To ensure fair access to upstream trunk bandwidth among a plurality of interface units, a plurality of queues is provided in a first unit. One of the queues is associated with the first interface unit. Each of the remaining queues is associated with one of a plurality of second interface units. Local data is received by the first interface unit and forwarded to the associated queue. Data received from a second, subtended interface unit is forwarded to a queue which associated with the second interface unit. Data is then issued from the queues according to a fairness algorithm. A unique identifier is assigned to each interface unit. Associating a queue with an interface unit is done by associating the queue with the respective interface unit's identifier. In each interface unit, local data is tagged with the instant interface unit's identifier, and received data is forwarded to a queue according to the data's tag.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: A method, apparatus, and system for communicating between a digital signal processor (DSP) and a packet processor.

Abstract: An apparatus and technique off-loads responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. A logic circuit enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until all pending (read) requests complete. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor.

Abstract: A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Abstract: A computer network is provided for handling ordered transactions between a chipset and a memory controller. The chipset provides an interface with a first bus segment and a second bus segment. The chipset may include logic to attach a destination code to ordered transactions transmitted from the chipset. The memory controller may also include logic to parse the destination code from ordered transactions and apply a fence with respect to a first queue and a second queue of the memory controller.

Abstract: A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines in which upon the falling edge of the grant signal from the memory controller for a first memory transaction and prior to the completion of the servicing of the first memory transaction, a second memory transaction can be issued. Once a first address corresponding to the first memory transaction request is transmitted to the memory controller, the address lines are available for transmitting a second address corresponding to the second memory transaction request to the memory controller. The memory controller then stores the second address in a buffer whereupon the completion of servicing the first memory transaction request, the second request can be serviced without waiting for the second request arbitration process or for the address to be transmitted to the memory controller.

Abstract: A two-dimensional hardware control block execution queue includes a plurality of initiator queues where each initiator queue includes at least one hardware control block. Each of the initiator queues is a queue of hardware command blocks, e.g., SCSI control blocks (SCBs) for a specific initiator device on the I/O bus. There is only one initiator queue for each initiator device. One head hardware control block, and only one head hardware control block of each initiator queue, is included in a common queue. Only a common queue head pointer is stored in a memory. An initiator command block tail pointer is stored in the head hardware control block for that initiator queue.

Abstract: A host channel adapter is configured for servicing a work notification, supplied by a host process to an assigned destination address accessable by the host channel adapter, based on matching the assigned destination address with a stored notification address from one of a plurality of queue pair context entries stored within the host channel adapter. The host channel adapter receives a queue pair context entry including a notification address, based on creation of a corresponding queue pair for a host process. The queue pair enables the host process to post a work descriptor and output a work notification to the host channel adapter by writing the work notification to an assigned destination address. The host channel adapter matches the assigned destination address with a stored notification address, and services the work descriptor based on the corresponding queue pair attributes specified in the identified queue pair context entry.

Abstract: A data processing arrangement comprises a plurality of processors and a memory interface via which the processors can access a collective memory. The memory interface comprises an interface memory (SRAM) for temporarily storing data belonging to different processors. The memory interface also comprises a control circuit for controlling the interface memory in such a manner that it forms a FIFO memory for each of the different processors. This makes to possible to realize implementations at a comparatively low cost in comparison with a memory interface comprising a separate FIFO memory for each processor.

Abstract: A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources.

Abstract: The present invention is built on a time out control apparatus to control the time out when a packet is transferred between terminal units connected to different buses. In the time out control apparatus, delay measuring means measures the delay time required for a response packet to be received after a request packet is sent to a terminal unit (control unit) connected via a bus. Delay information list generating means generates a delay information list in which the delay times measured by the delay measuring means are related to the individual identification information on the respective terminal units. Information output means reads out the delay time from the delay information list in accordance with a request from the terminal unit and outputs the delay time to the terminal unit. This sets the delay time on the time out register of the terminal unit.

Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.

Abstract: A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.

Abstract: A motor vehicle lighting system includes a master controller, a smart light, and a hot bus. The master controller is electrically couplable to a power supply and is adapted to receive an input signal corresponding to a left turn signal, a right turn signal, a run signal, or a brake signal. The master controller also includes a digital command signal output that is produced in response to the input signal. The smart light includes a light controller and a plurality of light emitting diodes (LED's). The light controller is adapted to control the LED's in response to the command signal. The hot bus electrically couples the master controller to the smart light. Power and the command signal are provided to the smart light over the hot bus.

Abstract: A method and system of managing resources in a host bridge by determining whether resources are deficient, preventing a second device from obtaining further resources and if this measure does not enable a first device to obtain resources, guaranteeing all resources to the first device.

Abstract: A computer system includes a processor, a cache, a system bus, a memory-control subsystem, an external memory bus, RAM memory, and flash memory. All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller, a flash-memory controller, and a memory interface between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer. During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers.

Abstract: If an uncachable write from a processor 300 is held in a processor request buffer 130 when a request control circuit 180 detects that a transaction for a cachable read to the processor 300 has been issued to a system bus 400, a retry control circuit 160 requests the transaction to be retried so as to prevent reversal in sequence between a preceding uncachable write and a following cachable read.

Abstract: A PCI and PCI-X bus-bridging method and apparatus is described. Posted memory write requests and requests not allowed to execute before a prior posted memory write are written to one queue. Requests that are allowed to pass a posted memory write are written to a separate second queue. Requests at the head of these queues receiving a RETRY response or failing to execute completely are removed from the queue and stored in a Retry List. Requests execute depending on which one of them wins control of the destination bus. The posted memory writes queue and any request not allowed to pass a posted memory write are blocked from executing if there is a location in the Retry List occupied by a posted memory write.

Abstract: A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals that allow these PCI-compliant units to request the use of the PCI bus system for data transfer. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop The request signals are assigned to either the first-layer access sequence loop or the second-layer access sequence loop in a predetermined manner. The user can change the assignment of a certian request signal from one loop to the other through PC's BIOS (Basic Input/Output System), so as to allow the associated PCI-compliant unit to have a higher priority level to the use of the PCI bus system.

Abstract: A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requestor will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requestor to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus.

Abstract: A portable computer can be “hot” docked to one or more expansion devices, such as a drive wedge and a port replicator. As such, the expansion devices can be connected to and disconnected from the portable computer while portable computer is powered on and fully operational. The portable computer includes control logic that detects when an expansion device is connected to or disconnected from the portable computer and asserts an SMI or equivalent interrupt signal to the computer's CPU to initiate a sequence of events by which the computer determines whether an expansion device has been connected or disconnected. If the CPU determines that the expansion device has been connected to the computer, the CPU appropriately reconfigures itself to communicate with the expansion device. If the expansion device is disconnected, the CPU also appropriately reconfigures itself to preclude communications with the disconnected device.

Abstract: Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. A number of memory locations within the isochronous queue may define the data level range of the isochronous queue. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue. The level of data within the isochronous queue may be a number of memory locations between a write pointer and a read pointer.

Abstract: A data processing arrangement comprises a plurality of processors. These processors share a collective memory. The arrangement comprises private buses. A private bus enables data communication exclusively between a processor and the collective memory. A memory interface provides access to the collective memory in data bursts while it produces substantially steady data streams on the private buses.

Abstract: An apparatus and method for permitting write posting with global ordering in a multipath system. The apparatus and method including a bus adapter having an input port to receive one or more operations from a processor. A queue controlled by the bus adapter buffers information from the one or more operations. A control circuit, coupled to the queue, generates an output signal that relates to the information from the one or more operations. The output signal is transmitted to the processor. An interconnect fabric, coupled to each bus adapter, transmits the one or more operations. A device, connected to the interconnect fabric, receives the transmitted operations, where the device sends a acknowledgment signal to the processor upon receiving the transmitted operation.

Abstract: A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second interface to receive a second request from the processor where the second request does not have the attribute. The memory interface unit also has a third interface to read/write information from/to a system memory. A method is also described that involves forwarding a processor request along a first path to a memory interface unit if the request has one or more attributes; and forwarding the request along a second path to the memory interface unit if the processor request does not have the one or more attributes.

Abstract: The present invention provides a bridge device and a method for generating message signaled interrupts to indicate completion of write transactions from one or more secondary bus devices to a primary bus device. The bridge device is coupled between a first bus and a second bus. The one or more secondary bus devices are coupled to the second bus and the primary bus device is coupled to the first bus. The bridge device includes a bridge FIFO and control circuitry, a first register, and an interrupt generation logic. The bridge FIFO and control circuitry is arranged to control data transfer between the one or more secondary bus devices and the primary bus device. The bridge FIFO and control circuitry is further configured to store and transfer write data from the one or more secondary bus devices to the primary bus device. The first register is arranged to store a set of interrupt bit numbers.

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The memory management unit transfers the network data between the transmit and receive state machines and the respective buffers based on prescribed interface protocol signals between the memory management unit and the transmit and receive state machines.

Abstract: In one embodiment, a system has a first device, a second device, and two sets of bi-directional buses that couple the first and second devices. The devices are to perform transactions with each other over the buses, such that each set of buses has a dominant, but not exclusive, direction, for sending transaction information and data, that is opposite the other. This configuration may allow the number of turnaround cycles on split transaction buses to be reduced, thus helping increase bandwidth.

Abstract: A method and apparatus for reducing flow control and minimizing interface acquisition latency in a hub interface is a method of transferring data between a control hub coupled to a hub interface which is coupled to an input-output hub including the following: Transferring the data in packets. Prioritizing isochronous transfers over asynchronous transfers. Limiting asynchronous transfers to 32 bytes per packet when an agent requests the hub interface, and limiting asynchronous transfers to 64 bytes per packet when no requests for the hub interface are recognized.

Abstract: A synchronous dynamic random access memory (“SDRAM”) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A two-dimensional hardware control block execution queue facilitates multiple command delivery to a single target device over an I/O bus, such as a SCSI bus. The two-dimensional hardware control block execution queue includes a plurality of target queues where each target queue includes at least one hardware control block. Each of target queues is a queue of hardware command blocks, e.g., SCSI control blocks (SCBs) for a specific target device on the I/O bus. There is only one target queue for each target device. One head hardware control block, and only one head hardware control block of each target queue, is included in a common queue. When a selection is made by a host adapter for a target device based upon a hardware control block addressed by a head pointer to the common queue, all hardware control blocks in the target queue within the two-dimensional hardware control block queue, which are accepted by the target device, are transferred to the target device.

Abstract: A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g.

Abstract: A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a storage location other than the command queue and executed out-of-order. Data movements specified by memory modifying commands already in the command queue and affecting the cache line in question are also performed out-of-order and the memory modifying command is discarded when it is removed in-order from the command queue.

Abstract: A queuing system that avoids live-locking is provided. A representative implementation of this system 1) selects a first queue item pointed to by a rotating pointer if the first queue item is ready to be serviced, 2) selects a second queue item pointed to by a find-first-pointer if the first queue item is not ready to be serviced, and 3) updates the rotating pointer so that the rotating pointer points to a third queue item.

Abstract: A method and apparatus for combined transaction reordering and buffer management. The apparatus may include a buffer, a first generator circuit and a second generator circuit. The buffer is configured to store memory transaction responses received from a memory controller in a plurality of addressable locations. The first generator circuit is configured to generate a first memory transaction request encoded with a first tag corresponding to an address in the buffer in response to receiving a first memory request. The second generator circuit is configured to generate a second tag using the size of said first memory request added to the first tag. The first generator circuit may be further configured to generate a second memory transaction request encoded with the second tag corresponding to a second address in the buffer in response to receiving a second memory request successive to the first memory request.

Abstract: A method and system for flow control of ordered, pipelined transaction requests within a system of intercommunicating electronic devices. The method and system rely on information stored within a producing node, information stored within a consuming node, and information added to certain transaction requests as they are transmitted from the producing node to the consuming node. In the producing node, outstanding transaction requests are maintained within a source input queue, each transaction request associated with a retry bit. When a message is transmitted from the producing node to the consuming node, a special marker bit may be included to flag certain messages as special to the consuming node. The consuming node maintains a retry vector having a retry bit corresponding to each producing node.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A computer system is presented which implements a “flush” operation providing a response to a source which signifies that all posted write operations previously issued by the source have been properly ordered within their targets with respect to other pending operations. The computer system includes multiple processing nodes within a processing subsystem and at least one input/output (I/O) node coupled to a processing node including a host bridge. The host bridge receives non-coherent posted write commands from the I/O node and responsively generates corresponding coherent posted write commands within the processing subsystem. Each posted write command has a target within the processing subsystem. The host bridge includes a data buffer for storing data used to track the status of non-coherent posted write commands. The I/O node issues a flush command to ensure that all previously issued non-coherent posted write commands have at least reached points of coherency within the processing subsystem.

Abstract: Method and apparatus for arbitrating access to a pci bus by a plurality of functions in a multi-function master. The arbitrating method is performed among the multiple functions of a multi-function master. The arbiter includes a rotating inquiry scheduler (RIS) and a heuristic inquiry initiator (HII). The RIS receives the local inquiry signal from the functional circuit and stores it. According to the local inquiry signal, a bus inquiry signal is generated and sent to the HII, and is sent to the PCI bus to request a use of the PCI bus. If the PCI bus responds a delay transaction termination, the HII can repeatedly send the bus inquiry signal to the PCI bus until the PCI bus grants the privilege to use the PCI bus. The HII then informs the RIS, which arranges the functional circuit to transmit data through the PCI bus.

Abstract: A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the input queue (12). The input queue (12) queues commands and requests a number of output queue credits in response to receiving a command. The input queue (12) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue (14) queues commands and requests a number of output queue credits in response to receiving a command.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.