Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block communicates a single request fully describing attributes of a two-dimensional data block across the communication fabric to a second functional block capable of decoding the single request to obtain the attributes of the two-dimensional data block. At least one of the functional blocks transmits data associated with the single request across the communication fabric.

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract: A method, apparatus and computer program product are provided for implementing enhanced autonomic data backup using multiple backup devices. A media definition object is defined for saving predefined user selections including a default backup format to be used, an order to process the libraries, a library exception size, and a maximum number of backup devices to be used serially. A list of libraries is generated by either a user specified order of the libraries or a size order of the libraries from largest to smallest. Each library in the generated list of libraries is processed to form at least one library queue of a serial device wait queue and a parallel device wait queue. A process IO procedure is called until backup completes for each library from the at least one library queue.

Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

Abstract: The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e.g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a “response memory” comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.

Abstract: A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus. To that end, each device is configured to manage its own set of buffer descriptors, unlike previous data path protocols in which only one device managed all the buffer descriptors. As such, neither device has to perform a read transaction to retrieve a “free” buffer descriptor from the other device. As a result, only write transactions are performed for transferring descriptors across the HPT bus, thereby decreasing the amount of traffic over the bus and eliminating conventional latencies associated with read transactions. In addition, because descriptors are separately managed in each device, the data path protocol also conserves processing bandwidth that is traditionally consumed by managing ownership of the buffer descriptors within a single device.

Abstract: A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Abstract: An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit can store data relating to a request to be sent, and the second circuit unit cannot store data relating to a received request. Thus, an on-chip interface is provided that may increase the overall system performance and that may support split transaction.

Abstract: A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to control criteria for determining whether control of a system bus will be released prior to completion of a write access to a peripheral. The criteria include which peripheral is being accessed, the particular bus master that is requesting the write request, and a mode of operation, such as supervisor or user write access modes. Write buffering may also be dynamically disabled for individual peripherals based on the state of a peripheral by using a hardware side band signal driven by the peripheral to override a static buffer write policy programmed in control registers.

Abstract: A host channel adapter configured for outputting packets, according to a service protocol requiring acknowledgement messages within a prescribed time interval following transmission, utilizes a retransmission table for storing entries identifying the packets awaiting respective acknowledgment messages during the respective prescribed time intervals. A retransmission manager is configured for updating the retransmission table after each access cycle, defined as a prescribed number of clock cycles. The retransmission manager also identifies a number of transmitted packets within the corresponding access cycle within a selected initial entry for the access cycle. An acknowledgment manager in the receive portion of the host channel adapter resets to zero an acknowledgment waiting bit in a selected entry in response to an acknowledgment message identifying the corresponding packet.

Abstract: A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the bus to one of a plurality of bus agents, and a fairness module imposes a desired degree of fairness to the data transfer resources by mandating data transfer resource access to bus agents whose commands have been subjected to a retry response. The degree of fairness is controllable, in order to appropriately balance the desired throughput and data transfer resource allocation for a particular application.

Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

Abstract: An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain cache coherency with data cached by one or more agents on the system bus. Transaction requests are queued within the bus bridge, transactions are snooped on the system bus, and a record of pending transaction addresses is maintained. Issuance of a queued transaction having the same cache line address as a pending transaction is stalled until the pending transaction has been completed.

Abstract: A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO.

Abstract: A technique for an enhanced transaction order queue is disclosed. A transaction order queue is used to prioritize transactions flowing through a bridge. The present technique enhances the transaction order queue by providing logic within a module, facilitating the enqueuing of a plurality of transaction entries within a single device and ensures that PCI/PCI-X ordering rules are not violated. The technique also provides that the logic device within the PCI-X bridges and buses selects and enqueues a single transaction entry from simultaneous multiple transaction entries.

Abstract: In one embodiment, a system is disclosed having a first device, a second device, and two sets of bi-directional buses that couple the first and second devices. The devices are to perform transactions with each other over the buses, such that each set of buses has a dominant, but not exclusive, direction, for sending transaction information and data, that is opposite the other. Other embodiments are also described and claimed.

Abstract: An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent for access to the interface. A pre-emptive arbiter provides arbitration between the first agent and the second agent when at least one of a first transfer request signal is asserted by the first agent for requesting access to the interface by the first agent and a second transfer request signal is asserted by the second agent for requesting access to the interface by the second agent. The pre-emptive arbiter is capable of synthesizing a transfer completion signal on the interface for preempting access of the first agent to the interface so that access may be granted to the second agent.

Abstract: Systems and methods consistent with the present invention connect a remote device to a IEEE 1394-based network through an intervening telephone line, thereby enabling the remote device to recognize, discover and control devices on the IEEE 1394-based network. A protocol repeater converts signals on the telephone line into signals understood by the IEEE 1394-based network. The protocol repeater preferably is transparent to the remote device so the remote device thinks that it is directly connected to the 1394-based network.

Abstract: A communication system for issuing commands from an initiator to a target, thereby allowing the target to write or read out data into/from a memory area which the initiator has and exchanging the data. The initiator transmits read and write commands for the memory area to the target so as not to exceed the total number of commands which can be held by the target. The target holds the received read and write commands, holds references to the commands by different queues, and independently processes the commands, so that the number of the commands to be transmitted can be managed efficiently.

Abstract: A system and method for replacing file system processors, also known as hot swapping, is described. The system and method operate on a fault-tolerant network file system that includes a first file server that is operably connected to a network fabric and a second file server that is operably connected to the network fabric. The fault-tolerant network file system includes a first disk array that is operably coupled to the first file server and to the second file server and a second disk array that is operably coupled to the first file server and to the second file server. First file system information is loaded on the first file server. The first file system information includes a first intent log of proposed changes to first metadata. Second file system information is loaded on the second file server. The second file system information includes a second intent log of proposed changes to second metadata.

Abstract: The method and apparatus presented are targeted to improve the performance of moving data between memory portions connected by a system bus where writes have higher performance than reads, such as the PCI bus. Due to the PCI bus design, read requests from memories connected across the PCI bus take a significantly longer time to complete than performing a write operation under the same circumstances. The present invention uses the faster write operations across the PCI bus, and queue management techniques, to take advantage of the relative speed of writes in a PCI system. The overall result is significant performance enhancement, which is especially useful in service aware networks (SAN) where operation at wired-speed is of paramount importance.

Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.

Abstract: A microprocessor prioritizes cache line fill requests according to request type rather than issuing the requests in program order. In one embodiment, the request types include blocking accesses at highest priority, non-blocking page table walk accesses at medium priority, and non-blocking store allocation and prefetch accesses at lowest priority. The microprocessor takes advantage of the fact that the core logic clock frequency is a multiple of the processor bus clock frequency, typically by an order of magnitude. The microprocessor accumulates the various requests generated by the core logic each core clock cycle during a bus clock cycle. The microprocessor waits until the last core clock cycle before the next bus clock cycle to prioritize the accumulated requests and issues the highest priority request on the processor bus.

Abstract: A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a memory interface and a plurality of pre-fetch queues. In one embodiment each pre-fetch queue is assigned to a master agent. In an alternate embodiment the pre-fetch queues are dynamically assigned to master agents. The bus interface services memory read requests, memory write requests, and pre-fetch requests. Data may be pre-fetched from main memory and stored in the pre-fetch queues. This reduces the latency for memory read requests and improves the efficiency of the memory interface with the main memory.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: Provided are a method, system, and program for processing operations in a system including a bus, a target device and devices capable of accessing the target device over the bus. The target device receives a transaction request from one of the devices over the bus and determines whether a delayed read request is pending after receiving the transaction request. The target device issues a command to disconnect the device initiating the transaction request from the bus. The device initiating the transaction request is allowed to reconnect to the bus and complete the transaction request after the delayed read request is completed.

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Abstract: An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface with a serial bus and parse a bitstream through the serial bus into a command and an address. Also, the apparatus includes bridge logic, an arbitrator and a decoder. The decoder is used to decode the command. If the command represents a predetermined request for access to a resource bus, the decoder passes the predetermined request associated with the address to the queue. Whenever the predetermined request occurs, the arbitrator grants the resource bus to the predetermined request and allows the queue to output the predetermined request as well as the associated address. The bridge logic is provided to transfer data to and from computer system resources according to the predetermined request and the address.

Abstract: A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence.

Abstract: Provided are a system and method for time-based scheduling in a communications environment. In one example, the method includes assigning at least one token to each of multiple active queues during a predefined period of time. Each token authorizes an amount of data to be dequeued from the queue. The method also includes waiting until the end of the predefined period of time before starting a new round of assigning. At least one of the queues is nominated based on the token assigned to the queue, where the nomination authorizes the dequeuing of the amount of data from the queue. The nomination is sent to a memory system to dequeue the data and send the data to a network uplink.

Abstract: A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

Abstract: A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

Abstract: The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Abstract: A host channel adapter configured for outputting packets according to InfiniBand™ protocol is implemented using partitioned link modules configured for performing selected link operations prior to outputting the packets. A pre-link module is configured for ordering work queue entries in an order based on determined service level and virtual lane priorities. The pre-link module outputs the ordered work queue entries to a transport service module configured for generating a transport layer header for the packets based on the respective work queue entries. Once the transport layer headers have been generated, a post-link module is configured for retrieval of the transport layer header and transport data and preparing the transmit data packets for transmission on the network by constructing the link layer fields. The post-link module outputs the transmit data packets based on the ordering and the flow control protocol for the appropriate virtual lanes.

Abstract: In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after completing processing the previous bus operation information structure. A processor forms the bus operation information structures and sets control over each bus operation information structure to a sequencer for processing. When a next bus operation information structure is ready for processing after completing processing the previous bus operation information structure, the sequencer checks whether it has control over the next bus operation information structure, and if so, begins processing the next bus operation information structure without being instructed to do so by the processor.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices and the central hub also communicates with a processor cluster and system memory over respective processor and memory buses. Thus, all components within the system are capable of communicating with each other through the hub. By communicating over the link buses via the link bus protocol, satellite devices can report events to other devices without dedicated wiring/pins between the devices as is currently performed in the prior art. In addition, the flushing of data buffers is governed by the protocol such that only targeted data buffers are flushed, which improves overall system performance.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to 5D) can gain bus access is a percentage of the total bus time.

Abstract: An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution.

Abstract: A computer system may include a processor, at least one memory coupled to the processor and having a plurality of scattered memory locations each having a pointer associated therewith, and a receiver interface circuit coupled to the at least one memory. The receiver interface circuit may include a scatter pointer queue for storing available pointers corresponding to available scattered memory locations. The scatter pointer queue may also store unavailable pointers corresponding to unavailable scattered memory locations. The receiver interface circuit may also include a receiver for receiving the data and writing the received data to the available scattered memory locations based upon the available pointers in the scatter pointer queue.

Abstract: Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware around a distributed reservation table. The apparatus manages access to a logical device, with first and second nodes with respective bus controllers communicatively coupled to each other and to a logical device by means of a bus. The first controller receives a request to reserve the logical device and, in response, communicates a reservation request for the logical device over the bus to the second controller for execution by the second controller. In response to the communicated reservation request, the second controller reserves the logical device for the first node.

Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second buffer circuit. The first buffer circuit may include a first plurality of buffers and the second buffer circuit may include a second plurality of buffers, each of which are coupled to receive control commands from a first and second source, respectively. Each buffer of the first and the second plurality of buffers corresponds to a respective virtual channel of a plurality of virtual channels and may be configured for storing selected control commands that belong to said respective virtual channels. Each scheduler unit may also include an arbitration unit for arbitrating between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit.

Abstract: An apparatus and technique off-loads responsibility for maintaining order among requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. The present invention comprises an ordering circuit that enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until a previous (read) request directed to the same address completes. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The ordering circuit maintains ordering in an efficient manner that is transparent to the processor.

Abstract: A method and system for a pipelined bus interface macro for use in interconnecting devices within a computer system. The system and method utilizes a pipeline depth signal that indicates a number N of discrete transfer requests that may be sent by a sending device and received by a receiving device prior to acknowledgment of a transfer request by the receiving device. The pipeline depth signal may be dynamically modified, enabling a receiving device to decrement or increment the pipeline depth while one or more unacknowledged requests have been made. The dynamic modifications may occur responsive to many factors, such as an instantaneous reduction in system power consumption, a bus interface performance indicator, a receiving device performance indicator or a system performance indicator.

Abstract: A system is designed to avoid problems that may occur if a physical layer misunderstands the kind of signal it receives and erroneously changes its state to a suspend state. When a node B receives an idle signal (i.e., a request cancel signal) from a node A (child node), the node B changes its state to a wait grant state where the node B waits to receive a grant signal from a node C (parent node) while keeping the request signal to the node C. The node B confirms that it has received the grant signal from the node C, and after that, changes its state from the wait grant state to a wait idle state where the node B transmits an idle signal to the node C, and waits until the grant signal from the node C changes into an idle signal. The node B confirms that it has received the idle signal from the node C, and after that, returns its state from the wait idle state to an idle state.