Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

Abstract: Provided herein may be a priority determination circuit and a method of operating the priority determination circuit. The priority determination circuit may receive request signals from a plurality of microcontrollers respectively corresponding to the plurality of planes, and output response signals corresponding to the request signals depending on a determined priority.

Abstract: Embodiments of the present disclosure relate to a method and an apparatus for backup communication. The method comprises: detecting a failure of a management interface between a processor and a baseboard management controller; in response to detecting the failure of the management interface, performing backup communication between the processor and the baseboard management controller using a control interface, wherein the baseboard management controller can obtain a physical parameter of the processor via the control interface; and transmitting a packet between the processor and the baseboard management controller via the control interface.

Abstract: A processor controlling access to a memory includes: a physical layer controller executing data access to the memory; a memory controller accepting an access request to the memory from a plurality of bus masters and causing the physical layer controller to execute the access request; and a CPU. The CPU shifts the memory controller into a busy state to accept the access request and stand by for execution, when a condition to turn the memory into a power-saving state is satisfied. The CPU executes control to turn the memory into the power-saving state, with the memory controller being in the busy state.

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract: There is disclosed techniques for managing data storage. In one embodiment, the techniques comprise recording index information in a block-based segment of a file system. The index information relates to an extent list in a virtual block map (VBM) pointing to the block-based segment. The techniques also comprise detecting an error in connection with the VBM. The techniques also comprise rebuilding the VBM based on the index information in response to detecting the error.

Abstract: Embodiments of the present disclosure relate to a method and an apparatus for backup communication. The method comprises: detecting a failure of a management interface between a processor and a baseboard management controller; in response to detecting the failure of the management interface, performing backup communication between the processor and the baseboard management controller using a control interface, wherein the baseboard management controller can obtain a physical parameter of the processor via the control interface; and transmitting a packet between the processor and the baseboard management controller via the control interface.

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract: According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.

Abstract: A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed.

Abstract: A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed.

Abstract: Systems and methods herein provide for managing connection requests through a Serial Attached Small Computer System Interface (SAS) expander. In one embodiment, the expander receives a low priority open address frame (OAF) that includes a source address and a destination address. The expander also receives a high priority OAF that includes a source address and a destination address. The high priority OAF requires at least a portion of a partial path acquired by the low priority OAF for which connection request arbitration is in progress. The expander determines whether the high OAF source address matches the low OAF destination address, and in response to a determination that the high OAF source address is different than the low OAF destination address, acquires pathway resources from the low priority OAF and forwards the high priority OAF in accordance with its destination address.

Abstract: In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.

Abstract: Method, system, bus arbitration device for accessing a memory are described. According to one embodiment, priorities of N function modules accessing the memory are compared to obtain location information of a function module with the highest priority. A bus of the function modules accessing the memory is switched to the function module with the highest priority by performing logic operation on the location information and bus information of each function module. Further, a bus arbitration device including a priority arbitration unit and a bus switching unit is described.

Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.

Abstract: A duplicate-aware disk array (DADA) leaves duplicated content on the disk array largely unmodified, instead of removing duplicated content, and then uses these duplicates to improve system performance, reliability, and availability of the disk array. Several implementations disclosed herein are directed to the selection of one duplicate from among a plurality of duplicates to act as the proxy for the other duplicates found in the disk array. Certain implementations disclosed herein are directed to scrubbing latent sector errors (LSEs) on duplicate-aware disk arrays. Other implementations are directed to disk reconstruction/recovery on duplicate-aware disk arrays. Yet other implementations are directed to load balancing on duplicate-aware disk arrays.

Abstract: The present invention relates to a far-end control method with a security mechanism including a host transmitting an identification code through the PSTN (Public switched telephone network) to the I/O control device of the far-end. The I/O control device has a CPU to receive the identification code and judge whether the identification code matches with the predetermined value stored therein; if the identification code matches with the predetermined value, the mobile internet connection between the host and the I/O control device is activated to enable the host to mutually transmit information or signals with a far-end control device from the I/O control device through the mobile internet, and the connection will be disabled after the information or signal transmission is completed.

Abstract: An arbitration circuit includes a use frequency setting block that sets a setting value for limiting a bus use frequency for each of a plurality of masters. A use request management section holds the bus use request from each of the plurality of masters and selects a use request that has not been granted from among the held use requests. A use frequency limitation block limits the use request selected by the use request management section such that the bus use frequency of each of the plurality of masters will not exceed its setting value. A use request grant block grants a use request of any one of the plurality of masters from among use requests not limited by the use frequency limitation block received from the plurality of masters.

Abstract: An elevator electronic safety system in which reliability of malfunction check can be improved by performing a malfunction check on memory data, an address bus, and a data bus. A check on the address bus and the data bus is executed periodically by a hardware circuit and software processing, and a memory data malfunction check circuit. A designated address and designated data used to verify both cases of “0” and “1” for each of all bit signals on the address bus and the data bus in a memory system are input to or output (the address is only output) from a CPU periodically. For the address bus, plural designated addresses are detected by a designated address detection circuit. For the data bus, plural pieces of designated data are written into and read out from memories and the data before and after writing are compared with each other.

Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holing unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.

Abstract: Method of processing data of at lease one data stream, data processing module for processing at a of at least one data stream, data processing system comprising such module, computer program product, data storage system and method of use thereof. For a time-based transfer of data to or from a device, data streams may be given a system ID and it is proposed to dynamically distribute available stream IDs. The proposed concept provides for indicating a type of data stream, providing and/or handling a set of stream IDs comprising a number of stream IDs and issuing a stream ID from the set of stream IDs to the data stream depending on the type of data stream. In a preferred embodiment, it is proposed to reserve one stream ID for an audio-video request, characterized by having no error handling time available. A further stream ID may be reserved for best effort requests.

Abstract: Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes associated with memory channels of the shared memory system, assigning priorities to the requests based at least in part on the power modes, and scheduling the requests based on the assigned priorities. Latency characteristics and page hit rate are also considered for assigning the priorities.

Abstract: Mechanisms for differentiating traffic types in a multi-root PCI Express environment are provided. The mechanisms generate a first mapping data structure that, for each single-root virtual hierarchy in the multi-root data processing system, associates a plurality of traffic classes with a plurality of priority groups and maps each traffic class in the plurality of traffic classes to a corresponding virtual channel in a plurality of virtual channels. Moreover, a second mapping data structure is generated that maps each virtual channel in the plurality of virtual channels to corresponding virtual link in a plurality of virtual links of the multi-root data processing system. Traffic of a particular priority group is routed from a single-root virtual hierarchy to a particular virtual link in the plurality of the virtual links based on the first mapping data structure and second mapping data structure.

Abstract: An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.

Abstract: Provided is a bus arbitration circuit including: a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit. The determination adjustment circuit masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other.

Abstract: A device includes an M-bit input request for service bus, a NEGATE component that may perform a negation operation on the M-bit input bus, an AND component that may perform a Boolean AND operation on the M-bit input signal and the negated input, and an M-bit 1-HOT grant output bus that indicates which request for service is being granted.

Abstract: The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit.

Abstract: A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal.

Abstract: The disclosure relates to a method for operating a bus system, in which a plurality of subscribers communicate with one another over the same bus line and all subscribers are assigned a subscriber address from a limited address set. To avoid address conflicts, it is suggested that by each subscriber newly added to an existing bus system, the bus traffic will be monitored before the first send access to the bus with the current subscriber address, in order to form a list of already used subscriber addresses. The subscriber then assigns itself an address from the as yet unused address space according to a predefinable schema.

Abstract: An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device.

Abstract: Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the service-providing bus users. The resource manager reserves a service from a providing bus user if the service can be used, and sends a response to a requesting bus user, allowing the requesting bus user to use the service from the providing bus user via the data bus. Information about the provided services is provided on the data bus via a standard interface by the bus users and a change in the provision of a service by a bus user is made available to the resource manager via the standard interface. The resource manager controls the service engagement on the basis of a priority information item.

Abstract: An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates in response a critical rank vector comprising at least first and second components. An arbitrator receives the critical rank vectors generated by rival the agents and applies a maximum or minimum extracting mechanism to at least one of the two components of the critical rank vectors to uniquely identify the block accessing the resource. Thus, functional blocks can be separated from arbitration control, the agents implementing the arbitration control and being solely responsible for it.

Abstract: A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.

Abstract: A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface for receiving a first bus access request signal from a first bus device; 2) a delay circuit that receives the first bus access request signal from the input interface and generates a time-delayed first bus access request signal; and 3) a comparator circuit that receives the first bus access request signal from the input interface and the time-delayed first bus access request signal from the delay circuit and generates a line driver enable signal only if both of the first bus access request signal and the time-delayed first bus access request signal are enabled. The comparator circuit disables the line driver enable signal if either of the first bus access request signal or the time-delayed first bus access request signal is disabled.

Abstract: The present invention provides a method and a control apparatus (1) for sequentially controlling the spinning up of a number of IDE_HDDs (30) included in one computer or network server. The method and apparatus works by assigning different ID numbers to different pairs of IDE_HDDs and causing a delay between the start of spin up of each pair. The control apparatus includes a host (10), a plurality of controllers (20), a plurality of power switches (40) and a plurality of IDE_HDDs. When the control apparatus is booted up, each controller receives an ID number from the host and delays activating the power switches connecting a power supply (50) to the IDE_HDDs by a time proportional to the ID number. The present invention thereby avoids too high an instantaneous peak current during booting up and prevents the power supply from being burnt out.

Abstract: A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface for transferring streamed data from the streaming data bus to the core-processing engine, a DMA interface for transferring DMA data from the DMA data bus to the core-processing engine, and an arbiter for coordinating data transfer with the core-processing engine between the streaming interface and DMA interface. The arbiter may operate in a split-bus-mode wherein the arbiter performs the address phase for more than one channel prior to entering into the data phase. The flexible I/O interface may include a common address bus and data bus between the processing engine and the interfaces. Alternatively, a switching fabric may couple separate address and data buss of the interfaces with the processing engine.

Abstract: A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined algorithm in response to a bus request from one of the functional blocks; and a plurality of bus connectors each of which connects a corresponding functional block to the ring bus, transmits data from the corresponding functional block to the ring bus, and transmits data from the ring bus to the corresponding functional block. The method includes synthesizing and laying out a bus system, simulating a case where a short-cut bus is used when data is transmitted between functional blocks and a case where the short-cut bus is not used, and generating a bus selection table, to be referred to for selection of a bus, based on the simulation results.

Abstract: A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.

Abstract: A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Abstract: When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage. However, custom designs are more expensive in terms of testing and development time. Rather than designing an integrated peripheral, an existing design (for example, peripheral 420) for the peripheral with attendant communications bus interface (for example, interface 424) is combined with an existing communications bus interface (for example, peripheral bus interface 410) to produce an integrated circuit (for example, integrated circuit 405). The use of existing designs greatly reduces development and test time, along with costs.

Abstract: A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority.

Abstract: A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in response to a first signal indicating a delay in a transfer between a first master of a plurality of masters and a slave on the bus, and (C) controlling the bus mastership using the first arbitration scheme in response to a second signal ending the delay in the transfer between the first master and the slave.

Abstract: A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

Abstract: A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into frames of equal length. When a bus request is received the technique determines whether the bus request in a current frame is for an asynchronous transaction or an isochronous transaction. If an asynchronous transaction bus request exists it is processed, otherwise an isochronous transaction bus request is processed. Bus requests for an isochronous transaction are queued if received while an asynchronous transaction is currently being processed. Asynchronous transactions are given priority until a current frame time has ended. In one embodiment, at the start of a new frame (which becomes the current frame) any queued isochronous transactions are processed before asynchronous transactions of the current frame are given priority.

Abstract: A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a range of addresses assigned to the second bus device. The configuration data is stored on the first and second bus devices. The processor transmits on the host bus a transaction request directed to an address within a range of addresses assigned to the second bus device. The first bus device determines that it should not transmit a response to the transaction request based on the configuration data stored in the first bus device. The first bus device may include a set of configuration registers for storing configuration data regarding the first bus device and a set of shadow configuration registers for storing configuration data regarding the second bus device.

Abstract: A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a plurality of memory regions and a plurality of control logic sections arranged in a matrix of rows and columns. The control logic sections in each one of the rows thereof is connected to a corresponding one of the plurality of memory regions. The control logic sections in each one of the columns thereof is connected to a corresponding one of the control/data buses. Each one of the rows of control logic sections are interconnected through an arbitration bus. The control logic section is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic section.

Abstract: A data storage system includes a plurality of control/data buses. A memory section is coupled to the plurality of control/data buses. The memory section includes a memory and a plurality of control logic sections interconnected through an arbitration bus. Each one of the control logic sections is coupled between a corresponding one of the control/data buses and the memory. Each one of such control logic sections includes a control logic for controlling transfer of data between the memory and the one of the plurality of control/data buses coupled to said one of the logic sections. The control logic is adapted to produce a control/data bus request for the one of the control/data buses coupled thereto and is adapted to effect the transfer in response to a control/data bus grant fed to the control logic. Each one of the control logic sections also includes a bus arbitration section coupled to the arbitration bus.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: A method for transmitting data on a bus having multiple data lines is disclosed. Each of the data lines within the bus is assigned a unique binary value. During data transmissions, only one of the data lines within the bus is activated at a time, and each activation of one of the data lines represents its associated unique binary value. Thus, an aggregate of consecutive activations represents the same information as if the data were transmitted in parallel.