Abstract: Techniques and solutions are described for partitioning data among different types of computer-readable storage media, such as between RAM and disk-based storage. A measured workload can be used to estimate data access for one or more possible partition arrangements. The partitions arrangements can be automatically enumerated. Scores for the partition arrangements can be calculated, where a score can indicate how efficiently a partition arrangement places frequently accessed data into storage specified for frequently-accessed data and placed infrequently accessed data into storage specified for infrequently accessed data.

Abstract: Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command.

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

Abstract: A method includes: if it is determined that a currently available resource of a task processing system cannot satisfy a resource requirement of a to-be-executed current task set of a plurality of task sets, scheduling, for execution, one or more tasks in the current task set that can be supported by the currently available resource; creating, based on one or more tasks that have not been scheduled in the current task set, a to-be-scheduled task set for a next round of scheduling; determining, in a next task set of the plurality of task sets that follows the current task set, a subset of tasks that are independent of the one or more tasks in the to-be-scheduled task set, where the next task set is dependent at least in part on the current task set; and moving the subset from the next task set into the to-be-scheduled task set.

Abstract: A hybrid bus apparatus is provided. The hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple a master(s) with one or more auxiliary slaves via heterogeneous communication buses. The hybrid bus bridge circuit and the auxiliary slaves are associated with respective unique slave identifications (USIDs). The master(s) can only support a fixed number of the USIDs, and thus a fixed number of the auxiliary slaves. The hybrid bus bridge circuit is configured to opportunistically mask some or all of the auxiliary slaves such that the respective USIDs associated with the masked auxiliary slaves can be reused by the master(s) to support additional slaves. As such, it may be possible to extend the capability of the master(s) to support more slaves than the fixed number of USIDs the master(s) can provide, thus enabling flexible heterogeneous bus deployment in an electronic device incorporating the hybrid bus apparatus.

Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.

Abstract: Disclosed embodiments describe a system for managing spillover via a plurality of cores of a multi-core device intermediary to a plurality of clients and one or more services. The system may include a spillover limit of a resource. and a plurality of packet engines operating on a corresponding core of a plurality of cores of the device. The system may include a pool manager allocating to each of the plurality of packet engines a number of resource uses from an exclusive quota pool and shared quota pool based on the spillover limit of a resource. The device determines that the number of resources used by a packet engine has reached the allocated number of resource uses of the packet engine, and responsive to the determination, forwards to a backup virtual server a request of a client received by the device for the virtual server.

Abstract: According to one embodiment of the present invention, a system on chip (SoC) including one or more intellectual properties (IPs) and a BUS, and a power control method using the same are provided, the SoC comprising: an IP-BUS activity monitor for measuring activity based on activity information of the respective IPs, for comparing with a pre-set activity threshold and for generating a first voltage control signal for the respective IPs based on the comparison result; and a voltage regulator for supplying voltage to the respective IPs based on the generated first voltage control signal.

Abstract: Technology for a memory pool arbitration apparatus is described. The apparatus can include a memory pool controller (MPC) communicatively coupled between a shared memory pool of disaggregated memory devices and a plurality of compute resources. The MPC can receive a plurality of data requests from the plurality of compute resources. The MPC can assign each compute resource to one of a set of compute resource priorities. The MPC can send memory access commands to the shared memory pool to perform each data request prioritized according to the set of compute resource priorities. The apparatus can include a priority arbitration unit (PAU) communicatively coupled to the MPC. The PAU can arbitrate the plurality of data requests as a function of the corresponding compute resource priorities.

Abstract: A method for controlling a distributed system. The distributed system includes a plurality of nodes and a bus. The plurality of nodes is associated with a plurality of timers. The method includes assigning a plurality of timer values including a first timer value and a second timer value to the plurality of timers in response to no data being loaded on the bus, defining an initial timer value equal to the first timer value, counting down the plurality of timer values with a given rate by activating the plurality of timers, stopping counting down the plurality of timer values in response to the first timer value reaching zero by stopping the plurality of timers, replacing the first timer value with a reference value, and sending data from the first node to the bus. The first timer value is assigned to a first timer of the plurality of timers, and the second timer value is assigned to a second timer of the plurality of timers.

Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.

Abstract: A connection management method for a plurality of networked devices, the method constituted of: assigning a priority value to each of the devices, the priority value representing a priority level associated with the respective device; receiving a plurality of connection requests, each of the connection requests being associated with a respective one of the plurality of devices; for each of the received connection requests, tracking the amount of time the respective device has been waiting for connection; for each of the received connection requests, assigning an arbitration wait time value representing the tracked amount of time; responsive to the assigned priority values and the assigned arbitration wait time values, connecting the device associated with one of the received connection requests to an expander port; and responsive to the connection, adjusting the respective priority value assigned to the connected device.

Abstract: A storage device includes memory devices and a controller. The controller translates a logical address received from a host to a physical address for the memory devices. The controller manages first correspondence information associated with correspondence relationships between logical addresses and physical addresses. The controller manages translation information that includes information of a minimal perfect hash (MPH) function. The MPH function is generated by using logical addresses indicating a memory region of a reference size as key values, when a size of a memory region indicated by logical addresses managed in the first correspondence information reaches the reference size. The controller manages second correspondence information associated with correspondence relationships between the logical addresses used as the key values and the MPH function of the translation information.

Abstract: A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node.

Abstract: Generally discussed herein are systems, devices, and methods for conflict resolution. A method can include identifying, by processing circuitry, whether a conflict exists between two or more nodes requesting access to a resource, in response to identifying a conflict exists, identifying a priority value for each of the nodes in conflict, the priority value for each of the nodes consistent with a probability distribution of possible priority values for each respective node, comparing the identified priority values to determine which priority value of the identified priority values corresponds to a highest priority value, and allocating access to the resource to the node corresponding to the determined highest priority value.

Abstract: A method, system, and computer program product for allocating one or more available ports on a data storage system, the data storage system having one or more data storage volumes, to enable communication with the one or more data storage volumes on the data storage system, the method, system, and computer program comprising filtering the one or more available ports on the data storage system to determine a balanced allocation of a port of the one or more available ports through one or more storage components on the data storage system, and allocating the port to the data storage volume thereby enabling access to the data storage volume through the one or more storage components.

Abstract: A programmable switch fabric can allow dynamic path selection for a specific class of packets using programmable action codes. Multiple packet processors inside a switch can process an incoming packet simultaneously and can make a decision (e.g., drop, forward, copy, etc.) related to the packet. A specific reassignment action code can be associated with the decision that needs to be prevailed for a specific class of packets. A priority arbiter can reassign the priority based on the specific reassignment action code so that the action associated with that action code prevails in the decision provided by the priority arbiter.

Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.

Abstract: A method for a storage area network includes setting a priority indicator in a signal of a storage request to form a high priority storage request for a storage target in the storage area network. The method further includes transmitting the high priority storage request to the storage target before the transmission of at least one normal priority storage request. The high priority storage request then traverses the storage area network with a higher priority than a normal priority storage request to the storage target. Upon receiving the high priority storage request, the storage target executes the high priority storage request prior to executing at least one normal priority storage request.

Abstract: A bus arbiter (101) is provided to a bus (107). The bus (107) is connected to a plurality of bus masters, such as a CPU (410) and a serial I/F (413), to each of which a priority is given. The bus arbiter (101) changes the priorities of the plurality of bus masters at cycles determined in advance. The bus arbiter (101) receives a request signal for making a request for use of the bus (107) from at least one bus master. Based on the priorities of the respective bus masters at a time when the request signal is received, the bus arbiter (101) identifies one bus master given the highest priority among the at least one bus master that has transmitted the request signal. The bus arbiter (101) transmits a grant signal for permitting the use of the bus (107) to the identified one bus master.

Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.

Abstract: Systems, methods, computer program product embodiments for an active/push notification façade for a passive database are described herein. An embodiment includes an event listener configured to poll (or query) a passive database and selectively retrieve data objects based on the poll results. Such a selective database read operation may be based on the priority of an event occurring in the passive database. If events of a low priority occur, the event listener does not open the passive database immediately to retrieve additional information related to the low priority event but defers reading the passive database by a pre-determined amount of time. If a higher priority event occurs, the passive database is immediately read to retrieve details related to the high priority event from the passive database. In another embodiment, event listener reads the passive database based on event timestamp information in the passive database and stored timestamp information.

Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.

Abstract: A technique for data prefetching for a multi-core chip includes determining memory utilization of the multi-core chip. In response to the memory utilization of the multi-core chip exceeding a first level, data prefetching for the multi-core chip is modified from a first data prefetching arrangement to a second data prefetching arrangement to minimize unused prefetched cache lines. In response to the memory utilization of the multi-core chip not exceeding the first level, the first data prefetching arrangement is maintained. The first and second data prefetching arrangements are different.

Abstract: A more efficient asynchronous protocol transmits data from a transmitter circuit at a first time to a receiver circuit and transmits a next data from the transmitter circuit to the receiver circuit at a second time so that the next data arrives at the receiver circuit at approximately the same time an acknowledge signal of the first data from the receiver circuit arrives at the transmitting circuit. The propagation delay may be measured at the beginning of a transfer to help determine when to send data.

Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract: An arbiter configured to selectively grant access to a shared bus to a plurality of requestors. The arbiter includes a plurality of request shapers each configured to receive a request signal corresponding to a request, from a respective one of the plurality of requestors, to access the shared bus, a base priority signal indicating a base priority level of the respective one of the plurality of requestors, and a delta period signal indicating a counter value threshold. The counter value threshold corresponds to a threshold amount of time, and the counter value threshold is different for each of the plurality of requestors. Each of the plurality of request shapes is configured to separately output the request signal and a priority signal indicating a priority level of the request based on the base priority level, the counter value threshold, and a counter value.

Abstract: A circuit arrangement, method, and program product for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block.

Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.

Abstract: Disclosed herein are tools and techniques for storing and using video processing tool configuration information that can identify combinations of video processing tools to be used for processing video. In one exemplary embodiment, video processing tools of a computing system are identified. The performance of a combination of the video processing tools is measured. The performance measurement is compared with another performance measurement of another combination of the video processing tools. Based on the comparison, video processing tool configuration information is set. In another exemplary embodiment, video processing tool configuration information indicating a combination of video processing tools is accessed, and video data is processed using the combination of video processing tools based on the video processing tool configuration information.

Abstract: A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.

Abstract: Systems and methods are disclosed for processing messages using a dynamic messaging bus. An example system includes a plurality of services residing in a dynamic messaging bus including a plurality of sub-buses. Each service is assigned to a sub-bus of the plurality of sub-buses. The example system also includes a performance monitoring module that monitors a performance of one or more services executing on a sub-bus to which the respective one or more services is assigned. A first service is assigned to a first sub-bus and a second service is assigned to a second sub-bus. The example system further includes a swapping module that determines, based on the monitored performances of the first and second services, whether to swap the assignments of the first and second services such that the first service is assigned to the second sub-bus and the second service is assigned to the first sub-bus.

Abstract: A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit.

Abstract: Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants privilege levels, which control access. For example, a high privilege level can grant access and a low privilege level can deny access. A status register indicates when an interface with a high privilege level is busy accessing the memory array.

Abstract: A connection apparatus that connects a plurality of storage units and a controller that establishes connection with the respective storage units in response to a connection request issued from each of the plurality of storage units and accesses the storage units includes a processor; and a memory, wherein the processor transmits a connection request selected based on priority information that represents priority associated with the connection among a plurality of received connection requests to the controller, the priority information being stored in the memory, and changes priority information included in a connection request received from a certain storage unit among the plurality of storage units so that the priority information has higher priority than the priority information included in connection requests received from the other storage units for a period where a connection request is successively received from the certain storage unit and a predetermined condition is satisfied.

Abstract: A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal.

Abstract: A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor.

Abstract: A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor.

Abstract: In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3).

Abstract: In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped.

Abstract: A bus host controller and a method thereof are provided. If a terminal device coupled to the bus is a non-periodic device, the bus host controller places a higher priority on data packet transferring request than start-of-frame (SOF) packet transferring request.

Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.

Abstract: An arbitration device and method including validating a second signal after a first signal is selected for a given number of times when the first signal and the second signal conflict, where the first signal has a first priority based on a priority order corresponding to a plurality of processes and the second signal has a second priority lower than the first priority.

Abstract: A system for controlling priority in a SCA-based application having a plurality of components wherein each of the components has a plurality of ports, includes: a priority component scheduler, interworking with the plurality of components wherein component priority order of the components is arranged therein; and a priority port scheduler that is provided in each of the components including the plurality of the ports which are associated with connections between the components, wherein port priority order of the ports included in each of the components is arranged therein. The priority component scheduler may be generated by using domain profiles in which component priority values of the components are set and the priority port scheduler may be generated by using domain profiles in which port priority values of the ports included in each of the components are set. Further, the domain profiles may be XML files.

Abstract: Various exemplary systems and methods for dividing a communications channel are disclosed. In at least some embodiments the method may comprise: coupling a plurality of storage devices to a communication channel, detecting whether the communication channel has been divided into multiple sub-channels, and coupling either a first backplane controller or a second backplane controller to the storage devices based on whether the communication channel has been divided.

Abstract: An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).