Dynamic Bus Prioritization Patents (Class 710/116)
  • Patent number: 10158712
    Abstract: A technique for source-side memory request network admission control includes adjusting, by a first node, a rate of injection of memory requests by the first node into a network coupled to a memory system. The adjusting is based on an injection policy for the first node and memory request efficiency indicators. The method may include injecting memory requests by the first node into the network coupled to the memory system. The injecting has the rate of injection. The technique includes adjusting the rate of injection by the first node. The first node adjusts the rate of injection according to an injection policy for the first node and memory request efficiency indicators. The injection policy may be based on an injection rate limit for the first node. The injection policy for the first node may be based on an injection rate limit per memory channel for the first node.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: December 18, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Eric Christopher Morton
  • Patent number: 10091132
    Abstract: Generally discussed herein are systems, devices, and methods for conflict resolution. A method can include identifying, by processing circuitry, whether a conflict exists between two or more nodes requesting access to a resource, in response to identifying a conflict exists, identifying a priority value for each of the nodes in conflict, the priority value for each of the nodes consistent with a probability distribution of possible priority values for each respective node, comparing the identified priority values to determine which priority value of the identified priority values corresponds to a highest priority value, and allocating access to the resource to the node corresponding to the determined highest priority value.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: October 2, 2018
    Assignee: Raytheon Company
    Inventor: Keith C. Smith
  • Patent number: 10067794
    Abstract: A method, system, and computer program product for allocating one or more available ports on a data storage system, the data storage system having one or more data storage volumes, to enable communication with the one or more data storage volumes on the data storage system, the method, system, and computer program comprising filtering the one or more available ports on the data storage system to determine a balanced allocation of a port of the one or more available ports through one or more storage components on the data storage system, and allocating the port to the data storage volume thereby enabling access to the data storage volume through the one or more storage components.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: September 4, 2018
    Assignee: EMC Ip Holding Company LLC
    Inventors: Thomas L. Watson, Anoop G. Ninan, Ameer Jabbar, Hala El-Ali
  • Patent number: 10009291
    Abstract: A programmable switch fabric can allow dynamic path selection for a specific class of packets using programmable action codes. Multiple packet processors inside a switch can process an incoming packet simultaneously and can make a decision (e.g., drop, forward, copy, etc.) related to the packet. A specific reassignment action code can be associated with the decision that needs to be prevailed for a specific class of packets. A priority arbiter can reassign the priority based on the specific reassignment action code so that the action associated with that action code prevails in the decision provided by the priority arbiter.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 26, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Bijendra Singh, Mark Anthony Banse
  • Patent number: 9996431
    Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 12, 2018
    Assignee: GM Global Technology Operations LLC
    Inventors: Shige Wang, Xiaofeng F. Song, Xian Zhang
  • Patent number: 9983801
    Abstract: A method for a storage area network includes setting a priority indicator in a signal of a storage request to form a high priority storage request for a storage target in the storage area network. The method further includes transmitting the high priority storage request to the storage target before the transmission of at least one normal priority storage request. The high priority storage request then traverses the storage area network with a higher priority than a normal priority storage request to the storage target. Upon receiving the high priority storage request, the storage target executes the high priority storage request prior to executing at least one normal priority storage request.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 29, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Mark J. Karnowski, Jon Infante
  • Patent number: 9665515
    Abstract: A bus arbiter (101) is provided to a bus (107). The bus (107) is connected to a plurality of bus masters, such as a CPU (410) and a serial I/F (413), to each of which a priority is given. The bus arbiter (101) changes the priorities of the plurality of bus masters at cycles determined in advance. The bus arbiter (101) receives a request signal for making a request for use of the bus (107) from at least one bus master. Based on the priorities of the respective bus masters at a time when the request signal is received, the bus arbiter (101) identifies one bus master given the highest priority among the at least one bus master that has transmitted the request signal. The bus arbiter (101) transmits a grant signal for permitting the use of the bus (107) to the identified one bus master.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 30, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirotaka Seki
  • Patent number: 9542341
    Abstract: In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: January 10, 2017
    Assignee: ST-ERICSSON SA
    Inventor: Rowan Nigel Naylor
  • Patent number: 9524312
    Abstract: Systems, methods, computer program product embodiments for an active/push notification façade for a passive database are described herein. An embodiment includes an event listener configured to poll (or query) a passive database and selectively retrieve data objects based on the poll results. Such a selective database read operation may be based on the priority of an event occurring in the passive database. If events of a low priority occur, the event listener does not open the passive database immediately to retrieve additional information related to the low priority event but defers reading the passive database by a pre-determined amount of time. If a higher priority event occurs, the passive database is immediately read to retrieve details related to the high priority event from the passive database. In another embodiment, event listener reads the passive database based on event timestamp information in the passive database and stored timestamp information.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: December 20, 2016
    Assignee: IANYWHERE SOLUTIONS, INC.
    Inventor: Ponnusamy Jesudoss Durai
  • Patent number: 9507596
    Abstract: A processor includes a core, a prefetcher, and a prefetcher control module. The prefetcher includes logic to make speculative prefetch requests through a memory subsystem for an element for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to determine counts of memory accesses to two types of memory and, based upon the counts and the type of memory, reduce the speculative prefetch requests of the prefetcher.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Ashok Jagannathan, Prabhat Jain, Krishna N. Vinod, Avinash Sodani
  • Patent number: 9465744
    Abstract: A technique for data prefetching for a multi-core chip includes determining memory utilization of the multi-core chip. In response to the memory utilization of the multi-core chip exceeding a first level, data prefetching for the multi-core chip is modified from a first data prefetching arrangement to a second data prefetching arrangement to minimize unused prefetched cache lines. In response to the memory utilization of the multi-core chip not exceeding the first level, the first data prefetching arrangement is maintained. The first and second data prefetching arrangements are different.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jason Nathaniel Dale, Miles R. Dooley, Richard J Eickemeyer, Jr., John Barry Griswell, Jr., Francis Patrick O'Connell, Jeffrey A. Stuecheli
  • Patent number: 9419782
    Abstract: A more efficient asynchronous protocol transmits data from a transmitter circuit at a first time to a receiver circuit and transmits a next data from the transmitter circuit to the receiver circuit at a second time so that the next data arrives at the receiver circuit at approximately the same time an acknowledge signal of the first data from the receiver circuit arrives at the transmitting circuit. The propagation delay may be measured at the beginning of a transfer to help determine when to send data.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: August 16, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Greg Sadowski
  • Patent number: 9208109
    Abstract: A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: December 8, 2015
    Assignee: Altera Corporation
    Inventors: Michael H. M. Chu, Jeffrey Schulz, Chiakang Sung, Ravish Kapasi
  • Patent number: 9064050
    Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: June 23, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Cristian Duroiu, Jaya Prakash Subramaniam Ganasan, Vinod Chamarty, Mark Michael Schaffer, Joshua H. Stubbs, Robert N. Gibson, Kris Tiri, Moinul H. Khan, Bohuslav Rychlik, Serag GadelRab, Simon Booth
  • Patent number: 9037767
    Abstract: An arbiter configured to selectively grant access to a shared bus to a plurality of requestors. The arbiter includes a plurality of request shapers each configured to receive a request signal corresponding to a request, from a respective one of the plurality of requestors, to access the shared bus, a base priority signal indicating a base priority level of the respective one of the plurality of requestors, and a delta period signal indicating a counter value threshold. The counter value threshold corresponds to a threshold amount of time, and the counter value threshold is different for each of the plurality of requestors. Each of the plurality of request shapes is configured to separately output the request signal and a priority signal indicating a priority level of the request based on the base priority level, the counter value threshold, and a counter value.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: May 19, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Bhaskar Chowdhuri
  • Publication number: 20150081941
    Abstract: A circuit arrangement, method, and program product for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to a shared receive queue for a first IP block. Receipt of the messages at the shared receive queue may be controlled based on receive credits allocated to each transmitting IP block. The allocation of receive credits for each transmitting IP block may dynamically managed such that the allocation of receive credits may be dynamically adjusted for each transmitting IP block based at least in part on message traffic associated with each transmitting IP block and/or a priority associated with each transmitting IP block.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey D. Brown, Robert A. Shearer
  • Patent number: 8982942
    Abstract: Disclosed herein are tools and techniques for storing and using video processing tool configuration information that can identify combinations of video processing tools to be used for processing video. In one exemplary embodiment, video processing tools of a computing system are identified. The performance of a combination of the video processing tools is measured. The performance measurement is compared with another performance measurement of another combination of the video processing tools. Based on the comparison, video processing tool configuration information is set. In another exemplary embodiment, video processing tool configuration information indicating a combination of video processing tools is accessed, and video data is processed using the combination of video processing tools based on the video processing tool configuration information.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: March 17, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wenfeng Gao, Shyam Sadhwani
  • Patent number: 8984198
    Abstract: A digital processor has a default bus master having a highest priority in a default mode, a plurality of secondary bus masters having associated priorities, wherein the plurality of secondary bus masters have a predetermined priority relationship to each other, and a data space arbiter. The data space arbiter is programmable in a non-default mode to raise a priority of any of the secondary bus masters to have a priority higher than the priority of the default bus master while maintaining the predetermined priority relationship to only those secondary bus masters for which the priority level also has been raised above the priority of the default bus master.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: March 17, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Michael I. Catherwood, Ashish Desai
  • Publication number: 20150067213
    Abstract: A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.
    Type: Application
    Filed: December 27, 2012
    Publication date: March 5, 2015
    Applicant: NEC Corporation
    Inventor: Toshiki Takeuchi
  • Publication number: 20150058508
    Abstract: Systems and methods are disclosed for processing messages using a dynamic messaging bus. An example system includes a plurality of services residing in a dynamic messaging bus including a plurality of sub-buses. Each service is assigned to a sub-bus of the plurality of sub-buses. The example system also includes a performance monitoring module that monitors a performance of one or more services executing on a sub-bus to which the respective one or more services is assigned. A first service is assigned to a first sub-bus and a second service is assigned to a second sub-bus. The example system further includes a swapping module that determines, based on the monitored performances of the first and second services, whether to swap the assignments of the first and second services such that the first service is assigned to the second sub-bus and the second service is assigned to the first sub-bus.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Applicant: Red Hat, Inc.
    Inventors: Filip Nguyen, Filip Eliás
  • Patent number: 8930601
    Abstract: A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: January 6, 2015
    Assignee: ARM Limited
    Inventor: Arthur Laughton
  • Patent number: 8918594
    Abstract: Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants privilege levels, which control access. For example, a high privilege level can grant access and a low privilege level can deny access. A status register indicates when an interface with a high privilege level is busy accessing the memory array.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: December 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Albini, Emanuele Confalonieri, Francesco Mastroianni
  • Patent number: 8856405
    Abstract: A connection apparatus that connects a plurality of storage units and a controller that establishes connection with the respective storage units in response to a connection request issued from each of the plurality of storage units and accesses the storage units includes a processor; and a memory, wherein the processor transmits a connection request selected based on priority information that represents priority associated with the connection among a plurality of received connection requests to the controller, the priority information being stored in the memory, and changes priority information included in a connection request received from a certain storage unit among the plurality of storage units so that the priority information has higher priority than the priority information included in connection requests received from the other storage units for a period where a connection request is successively received from the certain storage unit and a predetermined condition is satisfied.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Limited
    Inventors: Toshihiko Suzuki, Hidenori Takahashi, Hisano Osanai
  • Publication number: 20140244875
    Abstract: A method of priority based connection arbitration in a SAS topology is disclosed introducing a PRIORITY field to an SAS open Address Frame (OAF). As the expander arbitrates the multiple OAFs in competition for an Expander Link, it compares the PRIORITY fields of the arbitrating OAFs. The OAF with highest value of PRIORITY is awarded the destination connection path. In case of equal PRIORITY, the next arbitration is based on the value of Arbitration Wait Time (AWT). This priority based arbitration ensures high availability of SAS connection links to the SAS targets with high priority OAFs which in turn will lead to better quality of service for those SAS targets. PRIORITY field in the OAF is set by the SAS targets based on the current OAF priority and also set by directly attached SAS storage expanders through a modification of the OAF during transit through the expander.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: LSI CORPORATION
    Inventors: Shankar T. More, Vidyadhar C. Pinglikar, Prasad Ramchandra Kadam
  • Publication number: 20140223056
    Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Sundeep Chandhoke
  • Publication number: 20140223055
    Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: NATIONAL INSTRUMENTS CORPORATION
    Inventor: Sundeep Chandhoke
  • Patent number: 8793420
    Abstract: A system-on-chip (SoC), an electronic system including the same, and a method of operating the same are provided. The method includes setting real-time information indicating whether a master block is a real-time block in a real-time information register of the master block. A weight is set in a weight register of the master block. Buffer information of the master block is checked. A quality-of-service (QoS) signal is generated using the buffer information and the weight. A priority of the master block to use the bus is determined based on the QoS signal.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hong Ho Roh
  • Publication number: 20140201408
    Abstract: A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor.
    Type: Application
    Filed: June 8, 2013
    Publication date: July 17, 2014
    Inventors: Parin Bhadrik Dalal, Stephen Paul Belair
  • Publication number: 20140201409
    Abstract: A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor.
    Type: Application
    Filed: June 8, 2013
    Publication date: July 17, 2014
    Inventors: Parin Bhadrik Dalal, Stephen Paul Belair
  • Publication number: 20140201410
    Abstract: In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB3).
    Type: Application
    Filed: March 29, 2012
    Publication date: July 17, 2014
    Inventor: Florian Hartwich
  • Patent number: 8769175
    Abstract: In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventor: Lei Liu
  • Patent number: 8732367
    Abstract: A bus host controller and a method thereof are provided. If a terminal device coupled to the bus is a non-periodic device, the bus host controller places a higher priority on data packet transferring request than start-of-frame (SOF) packet transferring request.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 20, 2014
    Assignee: Asmedia Technology Inc.
    Inventors: Ching-Chih Lin, Pao-Shun Tseng, Wen-Hung Peng
  • Patent number: 8694705
    Abstract: To improve processing performance of an information processing device as a whole by controlling priority in units of processes. There are provided a bus for data transfer and a plurality of function modules each having a processing function performing processing in units of processes and capable of issuing a data transfer request for the bus. Further, there is provided a process identification information holding unit capable of holding process identification information set for each of the processes in association with the function module performing processing of the process. Furthermore, there is provided a bus arbiter determining a priority order of processing for each piece of the corresponding process identification information for each data transfer request from the function module and arbitrating contention of data transfer requests for the bus according to the priority order. Processing performance is improved by performing priority order control in units of processes.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hirotaka Hara, Tatsuya Kamei, Takahiro Irita
  • Patent number: 8650347
    Abstract: An arbitration device and method including validating a second signal after a first signal is selected for a given number of times when the first signal and the second signal conflict, where the first signal has a first priority based on a priority order corresponding to a plurality of processes and the second signal has a second priority lower than the first priority.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: February 11, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaki Okada
  • Patent number: 8650573
    Abstract: A system for controlling priority in a SCA-based application having a plurality of components wherein each of the components has a plurality of ports, includes: a priority component scheduler, interworking with the plurality of components wherein component priority order of the components is arranged therein; and a priority port scheduler that is provided in each of the components including the plurality of the ports which are associated with connections between the components, wherein port priority order of the ports included in each of the components is arranged therein. The priority component scheduler may be generated by using domain profiles in which component priority values of the components are set and the priority port scheduler may be generated by using domain profiles in which port priority values of the ports included in each of the components are set. Further, the domain profiles may be XML files.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: February 11, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Chul Oh, Nam Hoon Park
  • Patent number: 8639866
    Abstract: Various exemplary systems and methods for dividing a communications channel are disclosed. In at least some embodiments the method may comprise: coupling a plurality of storage devices to a communication channel, detecting whether the communication channel has been divided into multiple sub-channels, and coupling either a first backplane controller or a second backplane controller to the storage devices based on whether the communication channel has been divided.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 28, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Raghavan V. Venugopal, Stephen A. Kay
  • Publication number: 20140019655
    Abstract: An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Inventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
  • Publication number: 20140006665
    Abstract: A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 2, 2014
    Inventors: Hiroshi Amano, Daisuke Iwahashi
  • Patent number: 8619554
    Abstract: An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is op
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: December 31, 2013
    Assignee: ARM Limited
    Inventors: Andrew David Tune, Robin Hotchkiss
  • Patent number: 8566491
    Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 22, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Srinjoy Das, Philip Crary, Alexander Raykhman
  • Patent number: 8560746
    Abstract: An access control apparatus which establishes a connection based on connection establishment requests from connected devices and controls accesses to a connection target device. The access control apparatus includes a connection information managing unit which manages connect wait conditions to the connection target device of the connected devices based on criterion information in a connection request transmitted from the connected devices and determination for selecting one connected device from the connected devices. The access control apparatus includes a selecting unit which selects one of the connected devices which has a delay tendency related to connection based on adjustment information which is set in accordance with the connect wait conditions of the connected devices and increases a delay tendency in connection of the connected device, and a determining unit which determines the connected device selected by the selecting unit as one to be connected to the connection target device.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Nobuyuki Honjo, Atsuhiro Otaka, Atsushi Katano
  • Patent number: 8543762
    Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 24, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nakajima, Ikuya Yagisawa
  • Patent number: 8423694
    Abstract: A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 16, 2013
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Rowan Nigel Naylor
  • Patent number: 8407385
    Abstract: A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: March 26, 2013
    Assignee: LSI Corporation
    Inventor: Balaji Govindaraju
  • Patent number: 8307139
    Abstract: A communication system including a resource and an arbiter. The resource is shared among a plurality of requestors such that, at any given time, only one of the plurality of requestors has access to the resource. The arbiter is configured to receive a request from each of the plurality of requestors to access the resource, in which each request has a priority level associated with the request. The arbiter is further configured to age each request at a different rate relative to that associated with another request, and grant each requestor access to the resource based on i) the priority level and/or ii) the age of the request corresponding to the requestor.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: November 6, 2012
    Assignee: Marvell International Ltd.
    Inventor: Bhaskar Chowdhuri
  • Publication number: 20120254491
    Abstract: Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 4, 2012
    Applicant: The Regents of the University of Michigan
    Inventors: Sudhir Kumar SATPATHY, David Theodor Blaauw, Dennis Michael Sylvester, Trevor N. Mudge
  • Patent number: 8275938
    Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 25, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nakajima, Ikuya Yagisawa
  • Patent number: 8270316
    Abstract: An on-chip Radio Frequency (RF) Interconnect (RF-I) for communication between internal circuit nodes of an integrated circuit is provided. In one embodiment, an integrated circuit is provided that includes an on-chip transmission line, a first circuit node associated with an RF transmitter connected to the transmission line, and a second circuit node associated with an RF receiver connected to the transmission line. In order to transmit data from the first circuit node to the second circuit node, the RF transmitter associated with the first circuit node modulates the data onto an RF carrier frequency to provide a modulated RF signal and transmits the modulated RF signal over the transmission line. The RF receiver associated with the second circuit node receives the modulated RF signal from the transmission line and demodulates the modulated RF signal to recover the data for the second circuit node.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 18, 2012
    Assignee: The Regents of the University of California
    Inventors: Mau-Chung F. Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam, Chunyue Liu
  • Patent number: 8260993
    Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 4, 2012
    Assignee: Thomson Licensing
    Inventors: Shuyou Chen, Thomas Edward Horlander
  • Patent number: 8250253
    Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: August 21, 2012
    Assignee: Intel Corporation
    Inventors: Joon Teik Hor, Suryaprasad Kareenahalli